JPH04198782A - Semiconductor inspecting method - Google Patents
Semiconductor inspecting methodInfo
- Publication number
- JPH04198782A JPH04198782A JP2335364A JP33536490A JPH04198782A JP H04198782 A JPH04198782 A JP H04198782A JP 2335364 A JP2335364 A JP 2335364A JP 33536490 A JP33536490 A JP 33536490A JP H04198782 A JPH04198782 A JP H04198782A
- Authority
- JP
- Japan
- Prior art keywords
- test pattern
- power supply
- macro
- cells
- measurement period
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000000034 method Methods 0.000 title claims description 6
- 238000012360 testing method Methods 0.000 claims abstract description 31
- 238000005259 measurement Methods 0.000 claims abstract description 19
- 238000007689 inspection Methods 0.000 claims description 2
- 230000002950 deficient Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体集積回路の検査方法に関し、特に静
止時電源電流の評価に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for testing semiconductor integrated circuits, and particularly to evaluation of power supply current during quiescent state.
第３図は従来の半導体検査方法を示すブロック図であり
、これは半導体集積回路（以下、ＸＣと称す）の直流電
気特性の一つである静止時電源電流の測定方法を示す。FIG. 3 is a block diagram showing a conventional semiconductor testing method, which shows a method for measuring a quiescent power supply current, which is one of the DC electrical characteristics of a semiconductor integrated circuit (hereinafter referred to as XC).
図において、（１）はＩＣの一連の試験に用いられるテ
ストパターン、（２）はＩＣの特性試験を行うテスター
である。In the figure, (1) is a test pattern used for a series of IC tests, and (2) is a tester that performs IC characteristic tests.
−Ｆ記テスター（２）において、テストパターン（１）
の最終周期を被検査ＩＣに与え、該ＩＣの内部マクロセ
ルの動作を静止させて静止時電源電流を測定する。- Test pattern (1) in Tester (2) written in F.
is applied to the IC under test, the operation of the internal macrocell of the IC is stopped, and the static power supply current is measured.
〔発明が解決しようとする課！！１〕
従来の半導体検査方法では、ＩＣの静止時電源電流はテ
ストパターンの最終周期のみで測定されるので、被検査
ＩＣの静止時電源電流リーク不良を確実に検出しきれな
いという問題点があった。[The problem that the invention attempts to solve! ! 1] In conventional semiconductor testing methods, the quiescent power supply current of an IC is measured only in the final cycle of the test pattern, so there is a problem in that it is not possible to reliably detect quiescent power supply current leak defects in the IC under test. Ta.
この発明は上記のような問題点を解消するためになされ
たもので、既存テストパターンに手を加えることなく、
かつスループットを低下させずに静止時電源電流リーク
不良の検出率を高める半導体検査方法を得ることを目的
とする。This invention was made to solve the above-mentioned problems, and without making any changes to existing test patterns.
Another object of the present invention is to obtain a semiconductor inspection method that increases the detection rate of power supply current leak defects during static operation without reducing throughput.
この発明に係る半導体検査方法は、静止時電源電流の測
定周期を算出する計算機部を備えたものである。A semiconductor testing method according to the present invention includes a computer section that calculates a measurement cycle of a power supply current during a standstill.
この発明における半導体検査方法は、計算機部において
静止時電源電流の測定周期をテストパターンより決定し
半導体集積回路装置の静止時電源電流を測定する。In the semiconductor testing method according to the present invention, a measuring cycle of a quiescent power supply current is determined in a computer section based on a test pattern, and the quiescent power supply current of a semiconductor integrated circuit device is measured.
第１図はこの発明の一実施例を示すブロック図である。 FIG. 1 is a block diagram showing one embodiment of the present invention.
図において、（３）はテストパターン（１）の各周期に
対応した被検査ＩＣの各内部マクロセルの出力データ、
（４）は前記マクロセルの出力データ（３）をもとに算
出された静止時電源電流の測定周期であり、該測定周期
（４）は計算機部（５）で決定される。In the figure, (3) is the output data of each internal macrocell of the IC under test corresponding to each cycle of the test pattern (1),
(4) is the measurement cycle of the power supply current during rest calculated based on the output data (3) of the macrocell, and the measurement cycle (4) is determined by the computer section (5).
第２図は第１図のマクロセルの出力データの一例を示す
図でる。FIG. 2 is a diagram showing an example of output data of the macro cell shown in FIG. 1.
その他の構成は第３図の従来例と同様であり、同一符号
を付してその説明を省略する。The rest of the structure is the same as that of the conventional example shown in FIG. 3, so the same reference numerals are given and the explanation thereof will be omitted.
被検査ＩＣの静止時電源電流リーク不良検出率を最大に
するには前記被検査ＩＣ内の各マクロセルの論理出力値
が“Ｈ”の場合と“Ｌ”の場合に固定し、それぞれ静止
時電源電流を測定しなければならない。また、効率的に
測定するには、測定回数を最小におさえる必要がある。In order to maximize the detection rate of power supply current leak defects when the IC under test is at rest, the logic output value of each macro cell in the IC to be tested is fixed at "H" and "L", and the power supply at rest is fixed, respectively. Current must be measured. Furthermore, in order to perform measurements efficiently, it is necessary to minimize the number of measurements.
そこで、計算機部（５）において、テストパターン（１
）の各周期に対応した被検査ＩＣ内のマクロセルの出力
データ（３）より、各マクロセルの論理出力値の“Ｈ”
及び“Ｌ”の−値を包合し、かつ測定すべきテストパタ
ーン（１）の周期数を最小にするよう測定周期（４）を
算出し、テスター（２）において、テストパターン（１
）の前記測定周期（４）において、静止時電源電流を測
定する。Therefore, in the computer section (5), the test pattern (1
), the logical output value of each macrocell is "H" from the output data (3) of the macrocell in the IC under test corresponding to each cycle.
The measurement period (4) is calculated so as to include the negative values of and “L” and to minimize the number of periods of the test pattern (1) to be measured.
), the power supply current at rest is measured in the measurement period (4).
マクロセルの出力データ（３）が例えば第２図の場合、
計算機部（５）により測定周期（４）は第２、第４周期
と決定され、テストパターン（１）の第２．第４周期で
被検査ＩＣの静止時電源電流を測定すればリーク不良は
１００％検出可能となる。For example, if the output data (3) of the macrocell is as shown in Fig. 2,
The computer unit (5) determines the measurement period (4) to be the second and fourth periods, and the second and fourth periods of the test pattern (1). If the quiescent power supply current of the IC to be tested is measured in the fourth cycle, leak defects can be detected 100% of the time.
以上のように、この発明によれば静止時電源電流の測定
周期を算出する計算機部を有するように構成したので、
被検査ＩＣ内の各マクロセルの取り得る静止状態を全て
考慮しかつ測定回数を最小とすることができるため、静
止時電源電流リーク不良検出率を上げ、効率的に測定で
きるという効果がある。As described above, according to the present invention, since it is configured to include a computer section that calculates the measurement cycle of the power supply current during quiescence,
Since all possible static states of each macrocell in the IC to be tested can be taken into consideration and the number of measurements can be minimized, there is an effect that the detection rate of power supply current leak defects during static state can be increased and measurement can be carried out efficiently.
第１図はこの発明の一実施例による半導体検査方法を示
すブロック図、第２図は第１図におけるマクロセルの出
力データの一例を示す図、第３図は従来の半導体検査方
法を示すブロック図である。
図において、（１）はテストパターン、（２）はテスタ
ー、（４）は測定周期、（５）は計算機部である。
なお、図中同一符号は同一、又は相当部分を示す。FIG. 1 is a block diagram showing a semiconductor testing method according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of output data of the macro cell in FIG. 1, and FIG. 3 is a block diagram showing a conventional semiconductor testing method. It is. In the figure, (1) is a test pattern, (2) is a tester, (4) is a measurement period, and (5) is a computer section. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
装置の静止時電源電流を検査する半導体検査方法におい
て、上記静止時電源電流の測定周期を算出する計算機部
を有することを特徴とする半導体検査方法。1. A semiconductor inspection method for inspecting a quiescent power supply current of a semiconductor integrated circuit device using a test pattern and a tester, the method comprising: a computer section for calculating a measurement cycle of the quiescent power supply current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2335364A JPH04198782A (en) | 1990-11-28 | 1990-11-28 | Semiconductor inspecting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2335364A JPH04198782A (en) | 1990-11-28 | 1990-11-28 | Semiconductor inspecting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04198782A true JPH04198782A (en) | 1992-07-20 |
Family
ID=18287707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2335364A Pending JPH04198782A (en) | 1990-11-28 | 1990-11-28 | Semiconductor inspecting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04198782A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844909A (en) * | 1997-03-27 | 1998-12-01 | Nec Corporation | Test pattern selection method for testing of integrated circuit |
-
1990
- 1990-11-28 JP JP2335364A patent/JPH04198782A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844909A (en) * | 1997-03-27 | 1998-12-01 | Nec Corporation | Test pattern selection method for testing of integrated circuit |
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