JPH04344540A - Check list generation method - Google Patents

Abstract

PURPOSE:To provide a method for compressing the list length while keeping the generated check list as a higher fault detection rate than an objective fault detection rate on the check list generation checking the presence or absence of faults in the logic circuit. CONSTITUTION:In a step 2, the only when the fault detection rate of the check list is not lower than the objective fault detection rate when the check list capable of obtaining sufficient high fault detection rate on a single reduction fault is generated at the time of check list generation 1 checking the presence or absence of the fault in the logic circuit, the expectation pattern with the small number of fault detections is removed from the check lists in order.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test sequence generation method for digital circuits.

0002

[Background Art] In testing logic circuits, faults are determined by applying an input pattern in a test sequence to the external input of the logic circuit, and determining the state of the external output of the circuit, which has no faults described in the test sequence, that is, the expected value pattern. is compared with the actual state of the external output of the circuit, a so-called expected value comparison, and if they are different, it is determined that the state has been detected. Conventionally, if there is a possibility that a failure may be found by performing an expected value comparison, an expected value pattern is written in the test sequence regardless of the number of detected failure locations.

FIG. 2 shows an example of a circuit for generating a test sequence. 10 to 14 are external input signal lines, 20 and 21 are external output signal lines, and 30 to 40 are signal lines assuming a single stuck-at fault. Further, Table 1 shows an example of a test sequence composed of an input pattern and an expected value pattern for the circuit shown in FIG. 2, the faults detected by the test sequence, and the fault detection rate at that time. In the description in the detected fault column in Table 1, the number to the left of "/" indicates the signal line, and the number to the right indicates the fault in that signal line. 1 indicates a stuck-at fault, 0 indicates 0.
Indicates a stuck-at fault. Also, X in the test series represents don't care.

0004

[Table 1]

[0005]

[0006]

[Problem to be solved by the invention] However, (Table 1
), if the expected value pattern is written in the test sequence regardless of the number of detected faults, the expected value pattern that does not contribute much to increasing the fault detection rate will be The problem is that the test pattern becomes unnecessarily long. For example, when generating a test sequence with a target fault detection rate of 90%, in the case of the circuit shown in FIG. 2, it is sufficient to detect 20 faults. Therefore, the expected value patterns at times 8 and 10 shown in Table 1 do not contribute to the failure detection rate exceeding 90%.

[0007] An object of the present invention is to provide a test sequence generation method that has a fault detection rate higher than a target fault detection rate and is free from unnecessary expected value patterns.

[0008]

[Means for Solving the Problems] The present invention provides a method for generating a test sequence that can obtain a sufficiently high fault coverage rate for a single stuck-at fault when generating a test sequence to check the presence or absence of a fault in a logic circuit. Another feature is that, unless the fault coverage rate of the test sequence becomes lower than the target fault coverage rate, expected value patterns with the lowest number of detected faults are excluded from the test sequence in order.

[0009]

[Operation] According to the configuration of the present invention, the expected value pattern with a small number of detected failures, that is, the expected value pattern that does not contribute much to increasing the detection rate, does not fall below the target failure detection rate. By excluding the test sequence from the test sequence within the range, a test sequence with a higher fault coverage than the target fault coverage and without unnecessary expected value patterns is generated.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart of the process of the test sequence generation method according to the present invention.

An embodiment of the present invention will be described below with reference to the flowchart of FIG. 1, in which the target failure detection rate for the circuit shown in FIG. 2 is set to 90%.

First, in step 1, a test sequence is generated for the circuit shown in FIG. In this example, it is assumed that the test sequences shown in (Table 1) are generated.

[0013] In step 2, expected value patterns in which fewer faults are found in this test sequence are excluded from the test sequence. Here, the expected value pattern at time 8 and the expected value pattern at time 10 are used. First, the expected value pattern at time 8 is excluded from the test sequence. As a result, the 1 stuck-at fault in the signal line 33 cannot be detected, and at time 8
The failure detection rate of the test sequence excluding the expected value pattern is 9
It becomes 5.5%.

In step 3, the fault detection rate of the current test series is compared with the target detection rate, and since the fault detection rate of the current test series exceeds 90% of the target detection rate, Return to step 2.

[0015] Then, again in step 2 (Table 1)
The expected value pattern at time 10 in the middle is excluded from the test sequence. As a result, even a stuck-at-1 fault in the signal line 31 cannot be detected, and the fault detection rate of the current test series is 90.9%.

In step 3, the fault detection rate of the current test series is compared with the target detection rate, and since the fault detection rate of the current test series exceeds 90% of the target detection rate, Return to step 2 again.

[0017] Furthermore, in step 2, the next expected value pattern with fewer failures is excluded from the test sequence. Here, although the expected value patterns at time 6 and time 12 in (Table 1) are used, the expected value pattern at time 12 is first deleted. As a result, the stuck-at-1 fault in the signal line 34, the stuck-at-0 fault in the signal line 38, and the stuck-at-0 fault in the signal line 40 cannot be detected, and the fault detection rate of the current test series is 77.3%.

In step 3, the fault detection rate of the current test series is compared with the target detection rate, and since the fault detection rate of the current test series is lower than 90% of the target detection rate, step 4 is performed. Proceed to.

In step 4, the current test sequence is returned to the state before the last deletion of the expected value pattern.

As a result of the above processing, the test sequences generated, the faults detected by the test sequences, and the fault detection rate at that time are shown in (Table 2).

[0021]

[Table 2]

As described above, according to this embodiment, it is possible to generate a test sequence with a higher fault coverage than the target fault coverage and without unnecessary expected value patterns.

[0023]

[Effects of the Invention] As explained above, according to the present invention, by shortening the test sequence while maintaining a fault coverage rate higher than the target fault coverage rate, the memory used by the tester can be saved when testing actual logic circuits. , and can shorten inspection time.
Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of a test sequence generation method of the present invention.

FIG. 2 is a logic circuit diagram to which an embodiment of the present invention and a conventional example are applied.

[Explanation of symbols]

1 Step of generating a test sequence 2 Step of excluding the expected value pattern from the test sequence 3 Step of determining the detection rate 4 Step of re-adding the last deleted expected value pattern to the test sequence

Claims (1)

[Claims] Claim 1: A test sequence generation method for checking the presence or absence of a fault in a logic circuit, wherein when a test sequence that provides a sufficiently high fault coverage for a single stuck-at fault is generated, the fault coverage is set to a desired level. A method for generating a test sequence, characterized in that expected value patterns are excluded from the test sequence in descending order of the number of detected failures, as long as the number of detected failures does not become lower than the value of .