JP2002311112A - Semiconductor testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To locate a failure point in a circuit of a semiconductor device from output results of a test pattern of the semiconductor device. SOLUTION: The method comprises a step (S1) of inputting a test pattern of an optionally reduced test cycle to a semiconductor device, a step (S2) of detecting if the output of the semiconductor device fails, a step (S3) of stopping and locking the operation and condition of the device to lock a failure condition if the device fails in a test cycle, a step (S4) of acquiring a signal state in a circuit of the locked semiconductor device, a step (S5) of inputting a test pattern for a normal operation of the semiconductor device with the test cycle stopped at the same point as the test cycle stopped by the failure and acquiring a signal condition of the circuit of the device, and a step S6 of comparing the signal state in the circuit of the semiconductor device in the fail operation with that of the device being normally operating to locate the failure point in the internal circuit of the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test method and, more particularly, to a semiconductor test method in which an input signal of a test pattern is supplied to a semiconductor device, and an internal state in a normal operation is compared with an internal state in a failed state. The present invention relates to a semiconductor test method for specifying a defective circuit location.

[0002]

2. Description of the Related Art At present, semiconductor devices have become larger and more complex. In accordance with such a situation, the test is becoming difficult, and various methods for facilitating the test have been considered.

Conventionally, a test pattern is input to a semiconductor device at a constant operating frequency, an expected value output from the test pattern is compared with actual output data, and the semiconductor device is determined based on whether or not the values match. Determine whether the internal circuit of the device is normal or defective.

[0004]

In order to specify a defective portion by the above-described semiconductor test method, the test pattern must be inferred from information of output data after the test pattern has propagated in the circuit of the semiconductor device. No. Since the test pattern is diffused when propagating in the circuit of the semiconductor device, it is difficult to identify a defective portion from the data after the propagation.

[0005] The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor test method capable of easily specifying a defective portion of a semiconductor device.

[0006]

According to the present invention, a test pattern is input to a semiconductor device in synchronization with a test cycle, and it is determined whether a failure has occurred according to an output signal from the semiconductor device. In the semiconductor test method, the test pattern is input by narrowing any one of the test cycles, and it is detected whether or not a failure has occurred in the semiconductor device. The operation is stopped in the test cycle that has been performed, the signal state in the circuit of the semiconductor device when the operation is stopped is obtained, and the signal state in the same test cycle as the test cycle when the operation is stopped is obtained. Obtain the signal state in the circuit of the semiconductor device when the semiconductor device operates normally,
Comparing a signal state in the circuit of the semiconductor device when the normal operation is performed and a signal state in the circuit of the semiconductor device when the operation is stopped, and identifying a defective circuit. Semiconductor test method is provided.

According to the above method, a defective portion is specified by comparing data in an internal state and data in a normal state in a failed test cycle.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a flow of a procedure of a semiconductor test method of the present invention.

First, a test pattern is synchronized with a test cycle in a semiconductor device, and the frequency of an arbitrary test cycle is narrowed and input to the semiconductor device (S1). Then, the expected value of the output data of the input test pattern is compared with the output data actually output by the semiconductor device to detect whether or not a failure has occurred (S2). If no failure has occurred, a test pattern for the next test cycle is input (S1).

When a semiconductor device fails in a certain test cycle, input of a test pattern and operation of the semiconductor device are stopped, and a signal state in a circuit of the failed semiconductor device is fixed (S3).

The signal state in the circuit of the fixed semiconductor device is obtained (S4). Next, a test pattern for normal operation of the semiconductor device is input. At this time, the test cycle is stopped at the same test cycle as the test cycle stopped by the failure. Here, the test cycle location indicates, for example, a test pattern consisting of 1 to n pieces of data, which are input to the semiconductor device in order from 1 to n, and indicate the number of this order. Subsequently, the signal state in the circuit of the semiconductor device is obtained (S5).

Next, the signal state in the circuit of the semiconductor device at the time of a failure and the signal state in the circuit of the semiconductor device in a normal operation are compared. The defective part of the internal circuit of the semiconductor device is specified based on the parts having different signal states in comparison (S6).

Next, an embodiment of the present invention will be described. FIG. 2 is a circuit diagram of the semiconductor device. The semiconductor device 1 includes flip-flops F / F1 to F10,
Port I / O1-9, inverter Z1-3, AND
Circuit Z4, buffers Z5 to 13, and terminal System
_CLK and Scan_CLK. The circuit 2 indicates a portion including the AND circuit Z4 and the buffer Z10, and the path 3 indicates a wiring portion including the Z10 and extending to the Z4.

Terminals System_CLK, Scan_C
A clock is input to LK. This clock is supplied to flip-flops F / F1 to F1 of the internal circuit of the semiconductor device 1.
10 is supplied.

Test patterns are input to ports I / O1-3. The port I / O 4 is a port indicating an internal state of the semiconductor device 1. Flip-flop F / F1
To 3 are sequentially output in synchronization with the clock of the terminal Scan_CLK.

The port I / O 5 is a port indicating the internal state of the semiconductor device 1. Flip-flop F / F4
To 6 are sequentially output in synchronization with the clock of the terminal Scan_CLK.

The port I / O 6 is a port indicating the internal state of the semiconductor device 1. Flip-flop F / F
Data of 7 and 8 are sequentially output in synchronization with the clock of the terminal Scan_CLK.

The port I / O 7 is a port indicating the internal state of the semiconductor device 1. Flip-flop F / F
Data 9 and 10 are sequentially output in synchronization with the clock of the terminal Scan_CLK.

The port I / Os 8 and 9 are ports for outputting data whose test pattern has propagated through the internal circuit of the semiconductor device 1. Flip-flops F / F1 to 1
0 inputs data on the Data_In side in synchronization with a clock input to the terminal System_CLK, and simultaneously outputs stored data to the Data_Out side.
The flip-flops F / F1 to F10 are connected to the terminal Sca.
Scan_ in synchronization with the clock input to n_CLK
The data on the In side is input and stored, and the stored data is output to the Scan_Out side.

The inverters Z1 to Z3 invert the logic of the data and output the result. The AND circuit Z4 outputs the AND of the input data.
Performs operation and outputs. The buffers Z5 to Z13 drive the input data and output the data with the logic unchanged.

Next, the operation of the semiconductor device 1 will be described. First, the test pattern is port I / O
1 to 3 are input. The input data is at the terminal Sys
The signals are sequentially input to the flip-flops F / F1 to 3 in synchronization with the clock input to tem_CLK.

At the same time, the data of the flip-flops F / F1 to 3 transition to the flip-flops F / F4 to F / F6.
However, the logic of the flip-flop F / F1 is inverted by the inverter Z1 and the flip-flop F / F1 is inverted.
The logic of F2 passes through buffer Z5 and stays there,
The logic of the flip-flop F / F3 is based on the inverter Z2,
3 so that the state transitions as it is.

At the same time, the data of the flip-flop F / F4 passes through the buffers Z6 to Z9, and transitions to the flip-flop F / F7 with the logic unchanged. The data of the flip-flop F / F5 passes through the buffer Z10, and the data of the flip-flop F / F6 and the AND circuit Z
4 and an AND operation is performed to make a transition to the flip-flop F / F8.

At the same time, the data of the flip-flop F / F7 passes through the buffers Z11 and Z12, and transitions to the flip-flop F / F9 while keeping the logic unchanged. The data of the flip-flop F / F8 passes through the buffer Z13, and the logic of the flip-flop F / F8 remains unchanged.
Transit to F10. The data of the flip-flops F / F7 and 8 pass through the buffers Z11, Z12 and Z13, and the logic remains unchanged.
Transition to 9 and 10.

At the same time, flip-flop F / F
The data of 9 and 10 transits to port I / O 8 and 9.
By repeating the above operation, the test patterns input to the port I / Os 1 to 3 transition to the port I / Os 8 and 9 one after another. Further, in a certain transition state, the terminal Sca
When a clock is input to n_CLK, the states of the flip-flops F / F1, 4, 7, 9 are changed to the port I / Os 4 to 7 in synchronization with the clock, and the flip-flops F / F2,
The states of 5, 8, 10 are flip-flops F / F1, 4,
The states of the flip-flops F / F3 and 6 transit to the flip-flops F / F2 and 5, respectively. Sequential terminal Sca
When a clock is applied to n_CLK, the flip-flop F /
The states of F1 to F10 are sequentially output to I / Os 4 to 7.

From the above operation, the internal state of the semiconductor device 1 can be known. Next, an operation when a test pattern is input to the semiconductor device 1 will be described.

FIG. 3 is a diagram showing test pattern data input to the semiconductor device. 0 and 1 in the frame 5 of the test pattern data 4 are input to the semiconductor device 1 as a test pattern.

Inputs # 1 to # 3 correspond to ports I / O1 to 3. Test cycles 1 to 8 are connected to terminal System_C
Port I / O1-3 according to the clock input to LK
Shows the order of the test patterns to be input.

The clock rate is a clock operating frequency of a test pattern sequentially inputted. This clock operating frequency is equal to the terminal System_C of the semiconductor device 1.
LK.

H and L in the frame 6 are output data, and the test pattern input to the semiconductor device 1 is a port I / O.
This shows the state output from 8 and 9. Outputs #A and B correspond to port I / Os 8 and 9, respectively.

Output cycles 1 to 8 indicate the order of the output values of the test pattern. A test pattern of test pattern data 4 is sequentially input to the semiconductor device 1 from the test cycle 1. The input test pattern is
The circuit of the semiconductor device 1 is synchronized with the clock input to the terminal System_CLK and is output while transitioning the logic state. Since there are four flip-flops from the input to the output of the semiconductor device 1, output data can be obtained from the test cycle 5.

By comparing the data output from the input test pattern with the expected value of the predetermined output data, it can be determined whether or not the semiconductor device 1 has failed.

Next, a method of specifying which part of the circuit is defective in the semiconductor device 1 in which a failure occurs will be described. FIG. 4 is a diagram showing the contents of test pattern data in which the clock rate is sequentially reduced. 0 and 1 in the frame 8 of the test pattern data 7 are test patterns.

Inputs # 1 to # 3 correspond to ports I / O1 to 3. Test cycles 1 to 8 are connected to terminal System_C
Port I / O1-3 according to the clock input to LK
Shows the order of the test patterns to be input.

The clock rate is a clock operating frequency of a test pattern sequentially inputted. This clock operating frequency is equal to the terminal System_C of the semiconductor device 1.
LK.

H and L in the frame 9 are output data, and the test pattern input to the semiconductor device 1 corresponds to the port I / O.
This shows the state output from 8 and 9. Outputs #A and B correspond to port I / Os 8 and 9, respectively.

The output cycles 1 to 8 indicate the order of the output values of the test pattern. In the first test, a clock rate of 6 nSec is supplied to the terminal
m_CLK and the remaining test cycles 2 to 8 are 8
Input the nSec clock rate. In the second test, a clock rate of 6 nSec is input to the terminal System_CLK in test cycle 2, and a clock rate of 8 nSec is input in the remaining test cycles 1 and 3 to 8. In this manner, the clock rate of the test pattern 6 nSec is sequentially shifted to the subsequent test cycle for each test.

FIG. 5 is a diagram showing signal states in a circuit of a semiconductor device. (A) shows flip-flops F / F1 to
10 is a correspondence diagram, wherein (b) shows a signal state at the time of failure and log 1 and (c) shows a signal state at the time of normal operation and log 2. The values of 0 and 1 in FIGS. 5B and 5C are (a)
Of flip-flops F / F1 to F / F1 to F10.

First, a test pattern of test pattern data 4 is applied to the semiconductor device 1 at a clock rate of 6 nSe.
As a result of the test performed in step c, a failure occurs in the output cycle 7. Further, the semiconductor device 1 converts the test pattern of the test pattern data 4 to the clock rate 8.
No failure occurs when the test is performed in nSec.

The test pattern of the test pattern data 7 is input to the semiconductor device 1. 8 of the 8th test
It is assumed that a failure occurs in the cycle. At the same time, the operation of the semiconductor device 1 is stopped. At this time, the signal state in the circuit of the semiconductor device 1 is read by inputting a clock to the terminal Scan_CLK. Thus, the signal state log 1 in the circuit of the semiconductor device 1 at the time of the failure is acquired.

Next, when the test cycle is the eighth cycle, the signal state in the circuit of the semiconductor device 1 which does not fail is obtained. As one method for obtaining the information, a retest is performed under conditions where the semiconductor device 1 does not fail. A test pattern of test pattern data 4 is input at a clock rate of 8 nSec. At this time, a test pattern of test pattern data 7 is input, the operation of the semiconductor device 1 is stopped at the same number of test cycles (eighth cycle) in which a failure occurs, and the signal state in the circuit of the semiconductor device 1 is changed to the terminal Scan_CLK Input clock to and read.

As another method, the internal state of a circuit in a test cycle in which a failure occurs due to a simulation used at the time of circuit design or the like is simulated. The signal state in the circuit during normal operation of the semiconductor device 1 obtained by any one of the above methods is referred to as log 2.

From the above, when the log 1 and the log 2 are compared, the value of the flip-flop F / F8 is different. Therefore, erroneous data due to the failure of the circuit 2 is output to the flip-flop F /
Output to F8, the location of the defective circuit can be specified.

Next, a method for specifying a defective path of a circuit will be described. First, the signal state in the circuit one cycle before the test cycle in which the failure occurred is obtained.

As one method of obtaining information, the semiconductor device 1 is retested under the condition that a defective circuit does not fail.
The test pattern is stopped one cycle (the seventh cycle) before the test cycle in which the failure occurred. The signal state in the circuit of the semiconductor device 1 at this time is indicated by a terminal Scan_C.
A clock is input to LK and read.

As another method, a signal state in a circuit one cycle before a test cycle in which a failure occurs due to a simulation used at the time of circuit design or the like is simulated.

The path 3 inside the circuit 2 of the semiconductor device 1 can be specified by comparing the signal state obtained by any of the above methods with the log 1 and the log 2. From the above, even if there is no special semiconductor device analysis tool, if there is a circuit with scan flip-flops, there is a normal measurement test pattern, the analysis is completed only by comparing the measurement results,
Failure analysis of large-scale circuits can be completed without simulation.

Further, analysis can be performed in a short time and at low cost.
Further, it is possible to specify a defective portion and a cause without knowing the internal theory of a circuit to be analyzed.

[0049]

As described above, according to the present invention, the signal state in the circuit of the semiconductor device when the semiconductor device fails is compared with the signal state in the circuit of the semiconductor device when the semiconductor device operates normally. Defective parts can be easily specified without analogy.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of a procedure of a semiconductor test method of the present invention.

FIG. 2 is a circuit diagram of a semiconductor device.

FIG. 3 is a diagram showing test pattern data input to a semiconductor device.

FIG. 4 is a diagram showing the contents of test pattern data in which the clock rate is gradually reduced.

5A and 5B are diagrams showing signal states in a circuit of a semiconductor device, wherein FIG. 5A is a correspondence diagram of flip-flops F / F1 to F10, FIG. 5B is a signal state at the time of a failure, and FIG. The signal state at the time is shown.

[Explanation of symbols]

1 ... Semiconductor device, 2 ... Circuit, 3 ... Pass, 4 ... Test pattern data, 5, 6 ... Frame, 7 ... Test pattern data, 8, 9 ... Frame

Claims (4)

[Claims] 2. A semiconductor test method comprising: inputting a test pattern to a semiconductor device in synchronization with a test cycle; and determining whether a failure has occurred in response to an output signal from the semiconductor device. The test pattern is input by narrowing any cycle of the above, and it is detected whether or not a failure has occurred in the semiconductor device.When the semiconductor device has failed, the operation is stopped in the test cycle in which the failure has occurred, Obtaining a signal state in a circuit of the semiconductor device when the operation is stopped, the semiconductor when the semiconductor device operates normally in the same test cycle as the test cycle when the operation is stopped Acquiring the signal state in the circuit of the device, and performing the operation of the semiconductor device when the semiconductor device operates normally. Semiconductor test method comprising: the signal state of the inner, a procedure in which the operation is compared with the signal state of the circuit of the semiconductor device when it is stopped, identifies the defective circuit. 2. The semiconductor device according to claim 1, wherein the signal state in the circuit of the semiconductor device at the time of the normal operation is obtained by supplying a test pattern in a test cycle cycle in which the semiconductor device does not fail. Test method. 3. The signal state in the circuit of the semiconductor device at the time of the normal operation is obtained by using the operation simulation of the semiconductor device to obtain the signal state in the circuit assumed when the semiconductor device operates normally. 2. The semiconductor test method according to claim 1, wherein: 4. A signal state in the circuit of the semiconductor device one cycle before a test cycle when the failure occurs, a signal state in the circuit of the semiconductor device during the normal operation, and the operation is stopped. 2. The semiconductor test method according to claim 1, wherein a defective path in the defective circuit is specified by comparing a signal state in a circuit of the semiconductor device at the time of the occurrence.