JPH04128661A - Line delay testing device - Google Patents

Abstract

PURPOSE:To judge the adequacy of a signal display by providing a means for outputting a single pulse signal to a specific line, and a means for comparing the detected value data being output from the output pins of circuit elements in the specific line. CONSTITUTION:A line delay testing device is commonly provided with a line activating part 11 and a test data reading part 12, and also is provided with a pulse generator 20 which outputs a single pulse signal of a single pulse to a specific line specified by a source latch and a target latch inside an object 300 to be tested, and a test control part 10 by which respective detected test data being scanned out from respective pins of the source latch and target latch in the specific line, a logical element and LSI in the path on the basis of the single pulse signal are compared with the expected value data stored in a disk device 30 for judging the adequacy of the signal display. Thus, by only one test execution, the fault analysis of a signal display can be automatically carried out so as to cover all the paths in the specific line, and the signal display performance of the entire circuit can be detected with high accuracy and in a short time.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial application field (Figure 4) Prior art (Figures 6 and 7) Means for solving the problem to be solved by the invention (Part 1 Figure) Functional Examples (a) One embodiment of the present invention (Figures 2, 3, and 4) (b) Other embodiments of the present invention Effects of the invention [Summary] Regarding line delay test equipment that performs delay tests on signals, particularly regarding line delay test equipment that performs delay tests on logic circuit elements such as LSIs and printed wiring boards on which the same elements are mounted. The purpose of this paper is to propose a line delay testing device that can judge the overall delay performance by inspecting each via pin in the route of a specific line during test execution, and can also automatically analyze signal delay failures. , pulse signal generation means for outputting a single pulse signal to a specific line specified by a source latch and a target latch in an electric circuit; and outputting a single pulse signal from the target latch of the specific line based on the single pulse signal. and detecting and comparing means for comparing each detected value data outputted from the output pin of a circuit element in a specific line with expected value data stored in advance in an expected value data storage means, Based on this, the appropriateness of signal delay on a specific line is determined.

[Industrial application field]

The present invention relates to a line delay test device for testing the delay of signals input to the lines of an electric circuit, and in particular for delay testing of logic circuit elements such as LSIs and printed wiring boards on which the same elements are mounted. This invention relates to a line delay test device that performs.

With the recent demand for faster computer systems,
System cycle clock speeds are increasing year by year. Therefore, during system testing, a large number of steps and time are required to analyze whether it is a delay error or a logic error. Therefore, delay tests have come to be conducted in order to increase the efficiency of system tests and to check delay performance by detecting as many delay errors as possible before system tests. Here, the delay test refers to the sending side (
This method tests the propagation delay time between two FFs (source) and receiver (target) by checking whether the receiver FF can incorporate the expected logic between two clock pulses (double pulses). .

However, this delay test is different from conventional logical tests, and it is very difficult to confirm defective data using an oscilloscope or the like after the test is completed.

Therefore, the test equipment for delay testing needs to provide simpler and more detailed data to the operator.

[Conventional technology]

Conventionally, there has been a line delay testing device of this type as shown in FIG. FIG. 5 shows a schematic configuration diagram of a conventional line delay testing device. FIG. 4 shows a printed wiring board as a test object of this conventional device.

In the figure, the conventional line delay test apparatus includes a test control section 10 that is connected to a bus 400 via an interface IF and controls the entire test operation for a test object 300.
and a line activation unit 1 that activates the line between the source latch and the target latch in the device under test 300.
1, a double pulse generator 21 that outputs a double pulse to the activated line of the device under test 300, and a double pulse output from the double pulse generator 21 to the source latch and the source latch of the device under test 300. A synchronization circuit 22.23 synchronizes signals between target latches and outputs a double pulse signal CL CL2, and a test data reading section 12 that reads test data from a target latch on the line of the test object 300 to which the double pulse is input. The configuration includes the following.

The line activation section 11 includes a scan input (S I) section 1 that directly writes data for activating the line into the flip-flop (FF) in the test object 300.
1a, and a primary input (PI) section 11b that directly inputs data for line activation from the input/output terminal I10 of the device under test 300. Also,
The test data reading section 12 includes a primary output (po) section 12a that directly outputs the output signal of the target latch from the input/output terminal I10 of the device under test 300;
The configuration includes a scan output (So) section 12b that directly reads data from a target latch in the test object 300.

Next, based on the above configuration, the operation of the conventional apparatus will be described with reference to FIG. 6 for testing the printed wiring board 300 shown in FIG. 4.

First, the operator operates the keyboard 200 to set the double pulse clock pulse interval time to a predetermined interval (step 100). Based on the control of the test control section 10, the S1 section 11a detects the FFI and F in the printed wiring board 300.
Data for activating the line between the source latch and the target latch is scanned into F2.

Further, the PI section 11b inputs data from input terminals PI2 and PI3 of the printed wiring board 300. This SI section 11
Data is input by the PI unit a and the PI unit 11b, respectively, and the line between the source latch and the target latch is activated (step 102).

After the line is activated in step 102, a double pulse with the set predetermined clock pulse interval is input from the double pulse generator 20 to the clock line of the printed wiring board 300 (step 102). Based on this double pulse, the test data output from the target latch of the printed wiring board 300 is output from the 80 section 12b to the test control section 10 (step 103). Although the test data is output as scan-out, it can also be output as primary-out from the PO section.

The test control unit 10 compares the test data with the expected value stored in the disk device 30 and determines whether the signal delay on the specific line of the printed wiring board 300 is appropriate (step 104). If it is determined to be "defective" in this determination, data regarding the pinnet number of the line to be tested is stored as defective data in a specific memory area of the disk device 30 (step 105). Further, if it is determined to be "good" in step 104, the computer 10 checks whether all the various patterns divided by the combinations of input and output terminals of the printed wiring board 300 have been completed.
It is judged as 0 (step 106). If it is determined that all the patterns have been completed, the test operation ends; if not, the test operation returns to step 101 and is executed again until all the patterns are completed.

Next, while referring to the defective data stored in the disk drive 30, the pulse interval is set again in the double pulse generator, and the tests in steps 100 to 107 are performed.

By repeating this procedure many times, the delay performance of printed wiring boards was evaluated to investigate and determine the pulse interval between double pulses for the circuit under test to operate.

Furthermore, the operation timing of the conventional device will be explained based on FIGS. 5 and 7.

The double pulses output from the double pulse generator 21 apply a system clock through synchronization circuits 22 and 23. Synchronization is achieved taking into account the delay time due to differences in clock line length, etc., and the double pulse signal CLr is input to the source latch, and the double pulse signal C
L2 is input to the target latch. This double pulse signal CL CL2 has a cell opening time tS before the clock pulse rises and a hold time after the clock pulse falls 1) I is the input data, test data D D
, is the time when the source latch output 12 0 or the output value of the target latch 02 becomes unstable. Therefore, it is necessary to operate so that no data is output within the set-up time t and hold time tH.

[Problem to be solved by the invention]

Since the conventional line delay test equipment is configured as described above, it is possible to estimate the overall delay performance, but there is no way to further deepen the analysis, so incorrect judgments due to poor test data, etc. Even if erroneous judgments are made due to racing of the transmission line, there is no means to identify the pattern in which such erroneous judgments occur, which poses the problem of lowering the reliability of the test results.

Therefore, when analyzing failures in over-delay performance tests,
There are problems in which it is not possible to judge on the spot whether the test data is good or the real delay is good, and it cannot be determined without contacting the test data creation optical system, or when a certain transmission line is causing racing, over delay check This has caused a problem in that there are cases where it is judged as good.

The present invention provides a line delay testing device that is capable of determining the overall delay performance by inspecting each via pin on a specific line route by executing a - degree test, and is also capable of automatically analyzing signal delay failures. The purpose is to propose.

[Means to solve the problem] FIG. 1 shows a diagram explaining the principle of the present invention.

In the same figure, the line delay testing device according to the present invention includes a pulse signal generating means (1) that outputs a single pulse signal to a specific line specified by a source latch and a target latch in an electric circuit (5). ), and the expected value data storage means (3) stores in advance each detection value data outputted from the target latch of the specific line based on the single pulse signal and outputted from the output pin of the circuit element in the specific line. and a detection/comparison means (2) which compares the data with expected value data stored in the data transmission line, and determines whether or not the signal delay on a particular line is appropriate based on the comparison result.

[Effect]

In the present invention, by inputting a single pulse signal to a specific line and inspecting the output of the via pin on the route of this specific line, it is possible to check the entire route on the specific line by executing the test twice. Therefore, the signal delay failure analysis is automatically performed, and the signal delay performance of the entire electric circuit can be detected with high precision in a short time. In this way, the minimum delay check is executed in a pseudo manner to read the data of each passing pin, and the maximum delay data is used to perform the minimum delay test and check whether the passing logic elements, etc. are activated correctly. doing. Therefore, even if the via pin is not activated due to a test data creation error or if there is a racing failure,
It can be discovered through this process.

Furthermore, since signal delay failure analysis can be automatically performed without operator testing operations, accurate and uniform test results can be obtained.

〔Example〕

(a) One embodiment of the present invention Hereinafter, one embodiment of the present invention will be described based on FIG. 2.

FIG. 2 shows a schematic block diagram of this embodiment.

In the figure, the line delay test device according to this example is as follows:
Similarly to the conventional device shown in FIG. 5, the line activation section 11,
A pulse generator 20 is commonly equipped with a test data reading section 12, and in addition to this configuration, a pulse generator 20 outputs a single pulse signal to a specific line specified by a source latch and a target latch in the object under test 300. and a source latch for the specific line based on the single pulse signal;
Logic elements in the target rack and route (OR circuit)
A test control unit 1 that compares each detection test data scanned out from each pin of the LSI with the expected value data stored in the disk device 30 to determine the suitability of the signal delay.
0.

Next, the operation of the apparatus of this embodiment based on the above configuration will be explained based on FIG. 3, taking as an example a case where a delay test is performed on the printed wiring board 300 shown in FIG. 4.

First, step 101.10 is the operation of the conventional device.
2 (see Figure 6), in step 1.2 (Figure 3), activate the line between the source latch and the target latch, and connect the printed wiring to the source latch of this activated line. The single pulse signal is input from the pulse generator 20 via the clock line of the plate 300.

All detected test data from the output pins of the LSI in the specific line between the activated source latch and target latch are scanned out from the test data reading section 12 (step 3). The test control unit 10 compares all of the scanned out detection test data with the corresponding expected value data previously stored in the disk device 30 to determine whether the signal delay is appropriate (step 4).

If the signal delay is determined to be "defective" in step 4, various data such as the pin net number, LSI name, FF allocation address, etc. on the target specific line are processed under the control of the test control unit 10. and stores it in a specific area of the disk device 30 (step 5).

Furthermore, if the storage of various data on the specific line is completed in the step 5, or if the signal delay is determined to be "good" in the step 4, the data is stored on the same specific line activated in the step 1. On the other hand, the pulse generator 20
A single pulse signal is input from (step 6).

The test data reading unit 1 reads the detection test data from the target latch of the specific line to which the single pulse signal is input.
2 and scan out, and output the detected test data to the test control section 10 (step 7). This test control section 10
compares the detection test data with the corresponding expected value data stored in the disk device 30 to determine whether the signal delay is appropriate (step 8). Various data such as the pin number on the specified line are stored in a specified area of the disk device 30 (step 9).

If the storage of various data of the specific line is completed in step 9, or if the signal delay is determined to be "good" in step 8, the computer 100 stores the printed wiring board 3.
Determine whether or not the various patterns divided by the combination of input and output terminals of 00 are completed (step 10).
. If all the patterns have been completed in this step 10, the test operation ends; if not, the test operation returns to step 1 and is executed again until all the patterns are completed.

As described above, since the test data for line activation on a specific line is checked based on whether it has been correctly set in each FF by the first single pulse, for example, the test data is scanned into the FFI correctly by the test data creation process. If this is not the case, there will be no erroneous determination of a signal delay based on an erroneous detection result due to incorrect activation of a specific line.

In addition, since the minimum (racing) delay performance test is performed in a simulated manner, even if the transmission line has a racing failure, the minimum (racing) delay performance test can be simulated for the maximum (over) delay performance test. Since this is done using data, it can be determined that the racing is defective.

(b) Other embodiments of the present invention In the embodiments described above, printed wiring 3 equipped with an LSI
Although the present invention is configured to test 00, a configuration may also be adopted in which wiring boards of other logic elements or memory elements are tested.

Further, in the above embodiment, the test data detected by inputting the second single pulse is detected by the test data reading section 12 only from the scan at from the target latch, and the test data is compared with the expected value data by the test control section 10 for judgment. However, the test data reading section 12 scans out all the detected test data from the output pins of the LSI in the specific line between the source latch and the target latch, and reads all the scanned out test data. It is also possible to adopt a configuration in which the test control unit 10 compares the detected test data with each corresponding expected value data to determine the signal delay.

In this case, it is possible to judge the signal delay for all the specific lines that change with each single pulse,
Furthermore, the reliability of test results can be improved.

〔Effect of the invention〕

As described above, in the present invention, by inputting a single pulse signal to a specific line and inspecting the output of the transit pin on the route of this specific line, the route on the specific line can be determined by executing the test twice. This has the effect that the signal delay performance of the entire electric circuit can be detected with high precision in a short time since the failure analysis of the signal delay is automatically performed throughout the entire electrical circuit. In this way, the minimum delay check is executed in a pseudo manner to read the data of each passing pin, and the maximum delay data is used to perform the minimum delay test and check whether the passing logic elements, etc. are activated correctly. doing. Therefore, even if a transit pin is not activated due to an error in creating test data, or if racing is unnecessary, this process can be found.

Further, since signal delay failure analysis can be automatically performed without operator testing operations, accurate and uniform test results can be obtained.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a schematic block diagram of an embodiment of the present invention, Fig. 3 is an operation flowchart of the embodiment described in Fig. 2, and Fig. 4 is an example of a test object. Printed wiring board circuit diagram, Figure 5 is a schematic block diagram of a conventional line delay test device, Figure 6 is an operation flowchart of a conventional line delay test device, and Figure 7 is an operation timing chart of a conventional line delay test device. shows. 1...Pulse signal generation means 2...Detected value comparison means 3...Expected value data storage means 4...Line activation means 5...Electric circuit 10...Test control section 11... Line activation section 11a...Scan input (SI) section 11b...
...Primary input (PI) section 12...Test data reading section 12a...Primary output (PO) section 12b
...Scan output (SO) section 14...I
F...Pulse generator...Double pulse generator 0...Disk device

Claims (1)

[Claims] 1. Pulse signal generating means (1) for outputting a single pulse signal to a specific line specified by a source latch and a target latch in an electric circuit (5); Each detection value data outputted from the target latch of the specific line based on the pulse signal and outputted from the output pin of the circuit element in the specific line is stored in advance in the expected value data storage means (3). 1. A line delay testing device comprising: detection and comparison means (2) for comparing with value data, and determining whether or not a signal delay on a specific line is appropriate based on the comparison result. 2. The line delay testing device according to claim 1, wherein each detection value data detected based on a single pulse signal output from the pulse signal generating means (1) is compared by the expected value comparing means (2). After that, a single pulse signal is output from the pulse signal generating means (1) to the specific line again, and at least out of each detection value data detected based on this second single pulse signal is output from the specific line target latch. A line delay testing device characterized in that detected value data of the expected value comparison means (2) is detected by the expected value comparing means (2). 3. The line delay testing device according to claim 1, further comprising line activation means (4) for selecting and activating a specific line from among the lines of a plurality of routes in the electric circuit (5). Line delay test equipment.