JP2002107406A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device capable of testing the output voltage outputted from the output end of a DUT(device under test) at a DC test according to the variety of the DUT to be measured in a sorter time and measuring a high output voltage outputted from the output end of the DUT. SOLUTION: This semiconductor testing device is provided with a buffer means receiving a DC voltage signal from the output end of the DUT, converting it into a prescribed voltage by buffering current, and outputting and feeding it to the receiving end of a DCTU(DC test unit) by driving a station cable CB. The settling time at the receiving end of the DCTU can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus provided with a voltage measuring device for measuring a DC characteristic of a device under test (DUT). In particular, the present invention relates to a semiconductor test apparatus provided with a voltage measuring device corresponding to a case where the output impedance of the output pin of the DUT is high or a case where the output voltage output from the DUT is high.

[0002]

2. Description of the Related Art FIG. 1 is a conceptual configuration diagram of a semiconductor test apparatus. The main components include a timing generator TG, a pattern generator PG, a waveform shaper FC, a DC test unit DCTU, a pin electronics PE, a logical comparator DC, and a fail memory FM. Although the number n of channels of the pin electronics depends on the system configuration, it has, for example, 1000 channels or more.
Here, since the semiconductor test apparatus is well-known and well-known in the art, other signals and components, and the detailed description thereof will be omitted except for the main part according to the present application.

[0003] The internal configuration of the main part of the pin electronics PE according to the present application includes a DC relay K2 and an OUT relay K3.
, A driver DR, and a comparator CP. The DCTU according to the present application measures various DC characteristics while interrupting a desired IC pin of the DUT via the station cable CB having a length of several meters and the DC relay K2. Further, at the time of the DC test, the OUT relay K3 is in the OFF state, and is in a state separated from the driver DR and the comparator CP. Further, in order to improve the throughput of the device test, a voltage measuring device of a predetermined plurality of channels is provided so that simultaneous measurement can be performed. In this application,
A description will be given of an output voltage measurement function output from an IC terminal of a DUT among the DC characteristic measurement functions. Of course,
In addition, VSIM (voltage applied current measurement) and ISVM
Some of them have a measuring function of (current applied voltage measurement), but their description is omitted.

Next, the operation of measuring the sending-end voltage V1 output from the output end of the DUT will be described with reference to the principle connection diagram of one-channel DC voltage measurement in FIG. The station cable CB uses a shielded two-core shielded cable, and uses a force wire CBf, a sense wire CBs, and a shield wire as a guard wire CBg. This one end is connected to the voltage measuring unit 100, and the other end is connected to a plurality of channels of pin electronics PE. The lines of the force line CBf and the sense line CBs are as long as several meters and are connected in parallel to a plurality of pin electronics, so that distributed capacitances Cs and Cf of several hundred pico or more are formed.

The main configuration of the DCTU one-channel voltage measuring section 100 according to the present invention includes an input buffer A2, a voltage measuring section 80, and others. The DC DUT output signal (sending terminal voltage) V1 output from the DUT IC pin is
In a state where the DC relay K2 of the pin electronics is turned on and the OUT relay K3 is turned off, the pin relay is received via the station cable CB and measured by the voltage measuring unit 80.

Next, the settling time of the step response will be described with reference to FIG. FIG. 3 shows a relationship between the sending end voltage V1 output in a stepwise manner from the output end of the DUT.
3 shows a step response characteristic of the receiving end voltage V2 of the voltage measuring unit 100. The settling time ST1 depends on the source current capability or the sink current capability, which is the driving impedance of the DUT output terminal. Assuming that the drive current of the DUT is Is, the settling time Ts / V per unit voltage is in a relationship proportional to (Cs / Is).
Here, there are various DUTs to be measured, and when the output impedance of the DUT output terminal is as small as several tens of ohms, there is no problem. However, there are high impedance devices of several kilohms or more. Will be a hindrance. That is,
In the case of a DUT having a small drive current Is, the settling time becomes longer. Furthermore, in order to maintain measurement accuracy,
It is necessary to wait until the receiving end voltage V2 stabilizes to, for example, 99.8% or more, and it is necessary to lengthen the waiting time in proportion to the output impedance of the DUT output end. Therefore, in the actual measurement, the voltage measurement is started after the settling time ST1 is stabilized for a predetermined time, so that a further waiting time is required until the measurement is started. This waiting time is a factor that reduces the throughput of the device test.

On the other hand, DUTs to be measured are various,
If the output voltage of the DUT output terminal is a device having at least one output pin that outputs an allowable voltage that is acceptable by the voltage measuring unit 100, for example, a high voltage of 20 V or more, all test items cannot be tested. Become. As a result, only the relevant pin of the relevant DUT is inspected by another device. Thus, it is not preferable that there is a pin that cannot be tested, which is a practical difficulty. Note that a specific example of a device that outputs a high voltage that cannot be measured by ordinary pin electronics included in a semiconductor test apparatus is a flash memory, and the output voltage needs to be measured.

[0008]

There are various types of DUTs to be measured. Accordingly, in the prior art, the first
In the case of a device having a high output impedance at the DUT output terminal, there is a problem that the settling time ST1 when changing stepwise becomes long, and as a result, the throughput of the device test decreases. Second, in the case of a device that outputs a high voltage higher than the measurable voltage at the output terminal of the DUT, there is a difficulty that the device cannot be measured. These are undesirable and practical difficulties. Therefore, the problem to be solved by the present invention is to make it possible to measure an output voltage output from a DUT output terminal in a DC test in a shorter time in accordance with the variety of DUTs to be measured.
An object of the present invention is to provide a semiconductor test apparatus capable of measuring a high output voltage output from a DUT output terminal.

[0009]

In order to solve the above-mentioned problems, a voltage measuring device DCTU for measuring a DC characteristic of a device under test is provided in a main body of a semiconductor test device, and the DCT is provided.
U has at least a function of receiving and measuring a DC voltage at a DUT output terminal, and in a semiconductor test apparatus having at least one system of the DCTU, receiving a DC voltage signal S1 from the DUT output terminal and performing a predetermined current buffer. Buffer means 20 for outputting and driving the station cable CB of a capacitive load and supplying it to the receiving end of the DCTU
0, wherein the settling time at the receiving end of the DCTU can be reduced. According to the above invention, it is possible to realize a semiconductor test apparatus capable of measuring an output voltage output from a DUT output terminal in a DC test in a shorter time in accordance with the variety of DUTs to be measured.

In order to solve the above problems, a voltage measuring device DCTU for measuring a DC characteristic of a device under test is provided on a main body side of a semiconductor test device, and the DCTU has a function of receiving and measuring a DC voltage at a DUT output terminal. A semiconductor test apparatus including at least one DCTU, receiving a DC voltage signal S1 from the DUT output terminal, dividing the DC voltage signal into a predetermined DC voltage, outputting a current buffer, and outputting a current buffer; Buffer means 20 for driving cable CB and supplying it to the receiving end of the DCTU
There is a semiconductor test apparatus characterized in that it is possible to measure a high-voltage direct-current voltage signal S1 with 0.

Further, a voltage measuring device DCTU for measuring a DC characteristic of a device under test (DUT) is provided on a main body side of the semiconductor test device, and the DCTU is mounted on a test head side on which a DUT is mounted and which is electrically contacted. A station cable CB of a predetermined length for connecting the
Pin electronics PE provided in the test head
And at least a function of receiving a DC voltage signal S1 output from an output terminal of the DUT and measuring a DC voltage at the output terminal of the DUT via the DUT. Receiving the DC voltage signal S1 from the output terminal, a predetermined current buffer or a current buffer after dividing the voltage into a predetermined DC voltage and outputting the same, and driving the station cable CB of the capacitive load to receive the DCTU receiving terminal Buffer means 20 for supplying to
0, which makes it possible to reduce the settling time at the receiving end of the DCTU.

FIG. 4 shows a solution according to the present invention. In addition, since the above-mentioned DCTU measures, the IC of the DUT is used.
The buffer means 200 is inserted between the DC relay K2 and the station cable CB when the relay connected to the pin line L3 by interrupting the line L3 is referred to as a DC relay K2. There is a semiconductor test device.

The DCTU has a function of generating a predetermined voltage, a force line CBf for applying the DC voltage generated by the voltage generation function to the DUT, and a sense line for sensing a voltage signal S1 on the DUT side. When the station cable CB is provided in the station cable CB, the buffer means 200 is provided to be inserted into the sense line CBs, and supplies a DC voltage signal S1 from a DUT output terminal to the DUT output terminal.
Receiving the signal via the C relay K2, dividing the current into a predetermined current buffer or a predetermined DC voltage, and then supplying the current to the measurement input terminal of the DCTU via the sense line CBs. There is a test device.

FIG. 5 shows a solution according to the present invention. One aspect of the buffer means 200 is the first
When the relay K1 is provided with the relay K1, the second relay K4, the third relay K5, the fourth relay K6, and the buffer unit 220, the first relay K1 opens and closes between the force line CBf and the DC relay K2. The second relay K4 is a control relay that opens and closes between the sense line CBs and the DC relay K2.
0 when measuring the DC voltage signal S1 via
In the F state, the third relay K5 is a control relay that opens and closes between the input terminal of the buffer unit 220 and the DC relay K2, and measures the DC voltage signal S1 via the buffer unit 200. The fourth relay K6 is a control relay for opening and closing between the output terminal of the buffer section 220 and the sense line CBs, and measures the DC voltage signal S1 via the buffer means 200. The buffer unit 220 receives the DC voltage signal S1 from the DC relay K2 via the third relay K5 and divides the voltage into a current buffer or a predetermined DC voltage. Buffer the sense line CB via the fourth relay K6.
The semiconductor test apparatus described above is characterized by driving the s line.

Further, as one mode of the buffer section 220 of the buffer means 200, there is the semiconductor test apparatus described above, characterized in that at least the input DC voltage signal S1 is buffered and output.

FIG. 6 (a) shows a solution according to the present invention. Further, as one mode of the buffer unit 220 provided in the buffer unit 200, a voltage dividing unit 210 is provided, and a DC voltage signal S1 input by the voltage dividing unit 210 is provided.
Is divided at a voltage division ratio of 1 / a, and the divided voltage is output as a current buffer.

As one mode of the DC voltage signal S1 output from the output terminal of the DUT, the condition for generating the voltage signal S1 is controlled in a predetermined manner by a device test function provided in the semiconductor test apparatus (for example, stepwise). The semiconductor test apparatus described above is characterized in that it targets a DC voltage signal capable of controlling voltage generation or ON / OFF control).

As one mode of application of the buffer means 200, there is the above-mentioned semiconductor test apparatus characterized in that it is applied to at least one of the tester channels provided in the semiconductor test apparatus.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Further, the scope of the claims is not limited by the following description of the embodiments, and the elements and connection relationships described in the embodiments are not necessarily essential to the solving means.
Further, the description of the elements and connection relations described in the embodiments is an example, and is not limited to the description.

FIG. 4, FIG. 5, FIG. 6, and FIG.
This will be described below with reference to FIGS. Elements corresponding to those of the conventional configuration are denoted by the same reference numerals, and description of overlapping parts is omitted.

As shown in FIG. 4, the main configuration according to the present application is such that a buffer means 200 is additionally provided for each channel of the pin electronics PE. Others are the same as the conventional configuration.

FIG. 5 shows an example of the internal configuration of the buffer means 200. The buffer means 200 includes a relay K1,
K4, K5, and K6, and a buffer unit 220 are provided. Relays K1, K4, K5, K6 are ON / OFF from outside
It is a controllable on / off switch, and for example, a semiconductor relay can be applied. The relay K1 is controlled to the OFF state when measuring the sending end voltage V1 output from the DUT. Relay K4 is ON when buffer unit 220 is not used
The state is controlled and bypassed. Relay K
5, K6 controls both of them to the ON state when measuring the voltage using the buffer unit 220.

An example of the internal configuration of the buffer section 220 includes a voltage dividing section 210, a differential amplifier U3, and a resistor R3. As an example of the internal configuration of the voltage dividing section 210, FIG.
As shown in (a), a voltage dividing resistor R having a relatively high resistance value is obtained.
1 and R2 and phase compensation capacitors C1 and C2. As a result, a divided voltage signal S3 obtained by dividing the input signal S2 at a dividing ratio of 1 / a is output. As the voltage division ratio 1 / a, for example, a resistance value that becomes about 1/5 is used.
Since the voltage division ratio 1 / a can be corrected by calibration, there is no need to use an accurate resistance value. That is, the calibration is performed by sequentially generating voltages at desired plural points on the force line CBf,
Second, the relay K4 is turned on to sequentially measure this voltage, and second, the K5 side is turned on to sequentially measure the divided voltage. An accurate partial pressure ratio 1 / a based on both measurement results,
The offset voltage of the differential amplifier U3 can be obtained. By performing the voltage measurement correction process based on this calibration, the voltage measurement accuracy can always be maintained in the best state.

The differential amplifier U3 and the resistor R3 constitute a buffer amplifier, and outputs a buffer voltage S4 converted to a low output impedance of several tens Ω or less. Accordingly, the drive current Is2 is greatly increased, so that the distributed capacitance Cs of several hundred pico or more can be charged in a short time. That is, the settling time can be significantly reduced. For example, assuming that the output impedance of the buffer unit 220 is 10Ω,
Assuming that the output impedance of T is 1000Ω, 1
The settling time can be reduced to 0Ω / 1000Ω = 1/100.

According to the buffer section 220 having the above-described configuration, first, as shown in FIG. 7A, the receiving terminal voltage V2 has a greatly improved slew rate, and the settling time ST2 is greatly reduced. Therefore, there is obtained an advantage that the voltage measurement after the step change can be started in a short time, and as a result, a great advantage that the throughput of the device test relating to the DC test can be improved. Second,
As shown in FIG. 7B, by providing the voltage measuring unit 100 with the voltage dividing unit 210 and supplying the buffer voltage S4 obtained by dividing the sending-end voltage V1 output from the DUT to the voltage measuring unit 100, the device can also output a high voltage. Measurement can be performed. For example, the allowable voltage that the voltage measurement unit 100 can accept is 10 V
Assuming that the voltage is divided by ５, a high voltage up to 50 V can be measured practically. Therefore, a great advantage is obtained that the number of device types that can be tested by the semiconductor test apparatus can be further expanded.

Note that the technical concept of the present invention is not limited to the specific configuration examples and connection examples of the above-described embodiment. Furthermore, based on the technical idea of the present invention, the above-described embodiment may be appropriately modified and widely applied. For example, in the above-described embodiment, a specific example in which the voltage dividing unit 210 always divides the voltage to 1 / a has been described. However, if necessary, as shown in FIG. It may be configured so that measurement can be performed without applying pressure.

Further, in the case of an application mode in which the settling time is shortened but not intended for a device outputting a high voltage, the voltage dividing section 210 may be omitted as required.

The channels of the pin electronics provided with the buffer means 200 may be provided for all the channels. However, in a case where a specific small number of IC pins among the IC pins of the DUT are mostly used. May be configured to include the buffer means 200 only for a desired number of channels.

[0029]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, the buffer unit is inserted and provided between the position of the sending end voltage V1 at the DUT output terminal and the input terminal of the voltage measuring unit. There is an advantage that the settling time of the voltage measurement unit with respect to the receiving end voltage V2 can be greatly reduced, and as a result, the DC
As a result of being able to perform the test, a great advantage that the throughput of the device test related to the DC test can be improved can be obtained. Further, when the buffer means is provided with a voltage dividing section for dividing the sending end voltage V1, a DC test can be performed even on a device which outputs a high voltage. A great advantage is gained in that it can be scaled up. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram of a semiconductor test apparatus.

FIG. 2 is a principle connection diagram of a conventional one-channel DC voltage measurement.

FIG. 3 is a diagram for explaining a settling time at a receiving end of a voltage measuring unit with respect to a step response.

FIG. 4 is a principle connection diagram of one-channel DC voltage measurement of the present invention.

FIG. 5 is an example of the internal configuration of a buffer means according to the present invention.

FIG. 6 is an example of an internal configuration of a voltage dividing section according to the present invention.

FIG. 7 is a view for explaining a settling time at a receiving end of a voltage measuring unit with respect to a step response according to the present invention.

[Explanation of symbols]

 C1, C2 Phase compensation capacitor K1, K4, K5, K6, K7 Relay K2 DC relay K3 OUT relay R1, R2 Voltage dividing resistor A2 Input buffer R3 Resistance U3 Differential amplifier 80, 100 Voltage measuring unit 200 Buffer means 210 Voltage dividing unit 220 Buffer section CB Station cable CBf Force line CBs Sense line CP Comparator DCTU DC test unit DUT Device under test PE Pin electronics

Claims (8)

[Claims] 1. A semiconductor device having a voltage measuring device DCTU for measuring a DC characteristic of a device under test (DUT) provided on a main body side of the semiconductor test device, the DCTU having at least a function of receiving and measuring a DC voltage at an output terminal of a DUT, A semiconductor test apparatus having at least one system of the DCTU, receiving a DC voltage signal from the DUT output terminal, outputting a predetermined current buffer, outputting the signal, and the station cable CB.
And a buffer means for driving the DCTU and supplying the DCTU to the receiving end of the DCTU, whereby the settling time at the receiving end of the DCTU can be reduced. 2. A voltage measuring device DCTU for measuring a DC characteristic of a device under test (DUT) is provided on a main body side of a semiconductor test device, and the DCTU has at least a function of receiving and measuring a DC voltage at an output terminal of a DUT. In a semiconductor test apparatus having at least one DCTU, receiving a DC voltage signal from the DUT output terminal, dividing the voltage into a predetermined DC voltage, outputting a current buffer, and driving the station cable CB to drive the station cable CB. A semiconductor test apparatus, comprising: buffer means for supplying to a receiving end of a DCTU, capable of measuring a high-voltage DC voltage signal. 3. A voltage measuring device DCTU for measuring a direct current characteristic of a device under test (DUT) is provided on a main body side of a semiconductor test device, and the DCTU is mounted on a DUT and electrically connected to a test head. A DUT via a station cable CB of a predetermined length connecting between the test head and the main body, and a pin electronics PE provided in the test head.
Receiving the DC voltage signal output from the output terminal of the
A semiconductor test apparatus having at least a function of measuring a DC voltage at a T output terminal, wherein the semiconductor test device includes at least one system of the DCTU, receives a DC voltage signal from the DUT output terminal, and divides the signal into a current buffer or a predetermined DC voltage. A buffer means for driving the station cable CB to supply the current to the receiving end of the DCTU, and for supplying the current to the receiving end of the DCTU so that the settling time at the receiving end of the DCTU can be reduced. Semiconductor test equipment. 4. An IC of a DUT to be measured by the DCTU
The buffer means is inserted between the DC relay and the station cable CB when the relay connected to the pin line is a DC relay. Semiconductor test equipment. 5. The DCTU has a function of generating a predetermined voltage, and a DC voltage generated by the voltage generation function is supplied to a DUT.
And a sense line for sensing a voltage signal on the DUT side are connected to the station cable C.
B, the buffer means is inserted into the sense line and provided;
A DC voltage signal from the output terminal of the DUT is received via the DC relay, and a predetermined current buffer or a current buffer after dividing the voltage into a predetermined DC voltage is applied to the DUT via the sense line.
5. The semiconductor test apparatus according to claim 4, wherein the apparatus is supplied to a measurement input terminal of the CTU. 6. When the buffer means includes a first relay, a second relay, a third relay, a fourth relay, and a buffer unit, the first relay connects between the force line and the DC relay. A control relay that opens and closes, the second relay is a control relay that opens and closes between the sense line and the DC relay, and controls an OFF state when measuring a DC voltage signal via the buffer means; The third relay is a control relay that opens and closes between the input terminal of the buffer unit and the DC relay, and is turned on when measuring a DC voltage signal via the buffer means. Is a control relay that opens and closes between the output end of the buffer unit and the sense line, and turns on when measuring a DC voltage signal via the buffer means. A DC voltage signal from the receiving via a third relay, and a current buffer in the after dividing a predetermined current buffer or a predetermined DC voltage, said fourth
5. The semiconductor test apparatus according to claim 4, wherein the line of the sense line is driven via a relay. 7. The semiconductor test apparatus according to claim 6, wherein the buffer section of the buffer means current-buffers and outputs at least an input DC voltage signal. 8. A buffer provided in the buffer means includes a voltage divider, and divides a DC voltage signal input by the voltage divider at a voltage division ratio of 1 / a, and current-buffers the voltage. 7. The semiconductor test apparatus according to claim 6, wherein the output is performed.