JP2001074805A - Test board for ic tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the effect of a test by a method wherein every power- supply line which supplies a power supply to the prescribed terminal of an IC socket is provided, a GND line which grounds a terminal is provided and a plurality of signal line groups whose lengths are different according to every IC socket are provided. SOLUTION: An IC tester body 2, a test head 3 which is connected to the body 2 and a test board 5 which is connected to the test head 3 by a POGO pin 4 constitute this IC tester 1. By this constitution, (n) pieces of ICs which are to be tested are inserted respectively into corresponding sockets SO1 to SOn. When the same test is performed simultaneously in all the sockets SO1 to SOn, a through current flows to the respective ICs which are inserted into the respective sockets SO1 to SOn when a signal which is input to the respective sockets SO1 to SOn from the test board 5 is changed over. A peak current flows to the test board 5. Since the length of respective signal lines in signal line groups A1 to An id different in this constitution, the peak value of a current flowing to the test board 5 is lowered as compared with a case in which the timing of the peak is identical.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test board used for an IC tester and the like, and more particularly to a test board for an IC tester for reducing a peak current at the time of an IC test.

[0002]

2. Description of the Related Art FIG. 9 is a schematic configuration diagram showing a conventional test board for an IC tester. As shown in FIG. 9, a plurality of IC sockets, for example, two IC sockets 101a and 101b in FIG. 9 are provided with corresponding signal line groups 102a and 102b each formed of a plurality of signal lines and corresponding power supply line 103a. , 103b and the corresponding GND line 1
04a and 104b are used to connect to the test board 100. The power supply lines 103a and 103b are wirings for supplying power to predetermined terminals of the corresponding IC sockets 101a and 101b, and are GND lines 104a and 104b.
b is a wiring for grounding predetermined terminals of the corresponding IC sockets 101a and 101b.

Here, each signal line in the signal line groups 102a and 102b has the same length, and
The wiring lengths of 3a and 103b and the GND lines 104a and 104b are the same. For this reason, when the same test is performed simultaneously on all sockets, when the signal level of the test signal is switched, a through current flows through each IC inserted into each IC socket, and each IC socket 101a and 101b has Transient currents Ia and Ib flow as shown in FIG. In FIG. 10,
SIa indicates a signal waveform at a contact portion between the IC socket 101a and the IC, SIb indicates a signal waveform at a contact portion between the IC socket 101b and the IC, and Ia indicates an IC waveform.
The through current in the socket 101a and Ib indicate the through current in the IC socket 101b.

[0004]

As described above, all of the I
When a transient through current flows simultaneously in the C socket, these through currents overlap from the test board 100, and a very large peak current flows. Therefore, the number of ICs that can be tested at the same time depends on the number of drivers and the like. However, when a large current flows through a BI (burn-in) device or the like, it may be determined by the allowable current of the device. There were many. For this reason, the number of ICs that can be tested at the same time is limited, so that the test efficiency cannot be improved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an IC capable of simultaneously performing a test by shifting the timing of a peak of a transient through current flowing in each IC socket. It is an object of the present invention to obtain an IC tester test board capable of increasing the number of test boards and improving test efficiency.

[0006]

An IC tester test board according to the present invention is an IC tester test board for connecting a main body of an IC tester for testing an IC and a plurality of IC sockets. Each power supply line for supplying power to a predetermined terminal and a corresponding IC
Each GND line for grounding a predetermined terminal of the socket, and each IC
A signal line group including a plurality of signal lines of the same length which are connected corresponding to predetermined terminals of the socket and have different lengths according to the respective IC sockets.

In the test board for an IC tester according to the present invention, the power supply lines have the same length and the GND lines have the same length. It consists of a plurality of signal lines of the same length, each having a different length for each socket.

In the test board for an IC tester according to the present invention, in claim 1, each power supply line has the same length, each GND line has the same length, and each IC socket has a plurality of groups. Each signal line group is composed of a plurality of signal lines having the same length and different lengths for each group.

Further, the test board for an IC tester according to the present invention is a test board for an IC tester for connecting a main body of an IC tester for testing an IC to a plurality of IC sockets. Power supply lines for supplying power to the respective IC sockets, and ground lines for grounding predetermined terminals of the corresponding IC sockets, and GND lines having a length corresponding to the respective IC sockets;
And a signal line group including a plurality of signal lines connected to predetermined terminals of each IC socket.

In the test board for an IC tester according to the present invention, in claim 4, all signal lines constituting each signal line group have the same length, and each power supply line and each GND line are connected to each IC socket. Power supply line and GND for the same IC socket
Line lengths are the same.

Further, in the test board for an IC tester according to the present invention, in claim 4, all signal lines constituting each signal line group have the same length, and each IC socket is divided into a plurality of groups. The power supply lines and the GND lines have different lengths for each group, and the lengths of the power supply lines and the GND lines for the same IC socket are the same.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a schematic configuration diagram showing an example of an IC tester test board according to Embodiment 1 of the present invention. FIG. 1 (a) shows a front view, and FIG. 1 (b) shows a plan view. I have. In FIG. 1, an IC tester 1 which is a test device for testing an IC is connected to an IC tester main body 2, a test head 3 connected to and fixed to the IC tester main body 2, and connected to the test head 3 and pogo pins 4. Test board 5
It is composed of

The test board 5 has n pieces (n is 2 or more).
) Of IC sockets (hereinafter referred to as sockets) S
O₁~ SO_nBut each is composed of multiple signal lines
Signal line group A₁~ A_n, Corresponding power line P₁~ P_nAnd pair
Corresponding GND line G₁~ G_nAre connected using
You. Note that the power line P₁~ P_nIs the corresponding socket SO ₁
~ SO_nIs a wiring for supplying power to a predetermined terminal of
ND line G₁~ G_nIs the corresponding socket SO₁~ SO_nPlace
This is a wiring for grounding a fixed terminal.

The power supply lines P ₁ -P _n and the GND lines G ₁ -G _n have the same length, but the signal line groups A ₁ -A _n.
Are different from each other in length. On the other hand, as the length of each signal line constituting the signal line group A ₁ is the same, in each of the signal line groups A ₁ to A _n, the signal lines constituting the same length, respectively. In FIG. 1,
The case where the signal line group A ₁ length of the signal line becomes longer in the order are shown as an example.

In such a configuration, a test n
Sockets SO corresponding to each IC ₁~ SO_nTo each
Insert the same test into all sockets SO₁~ SO_n
If the test is performed at the same time,
O₁~ SO_nWhen switching signals input to the
SO₁~ SO_nThrough each IC inserted in
The current flows. Therefore, each socket SO₁~ SO_nTo, over
Test current
The peak current flows through the node 5. However, the signal line group A₁~ A_n
Flows into the socket because the length of each signal line is different
The timing at which each transient through current peaks
However, the timing at which each through current reaches a peak is
Compared to the case where all are the same,
Current peak value decreases.

FIG. 2 is a diagram showing waveforms at various parts of the test board for the IC tester shown in FIG. 1, which will be described in more detail with reference to FIG. In FIG. 2, SI _{1 to} SI
_n is a signal waveform of the contact portion of the corresponding IC socket SO ₁ to SO _n and IC, I ₁ ~I _n represents current flowing through the corresponding IC socket SO ₁ to SO _n. From the test board 5, each socket SO via the signal line group A ₁ to A _{n
For 1 to} SO _n , predetermined test signals rising from a low level to a high level are output.
Along with this, the respective contact portions of the IC in the socket SO ₁ to SO _n, the test signal are input after the delay time T ₁ through T _n caused by the signal line group A ₁ to A _n. Each signal line length in the signal line group A ₁ to A _n, since it was set to be sequentially longer from the signal line group A _1, and the delay time T ₁ <delay time T ₂ <............ <delay time T _n Become.

On the other hand, the test board 5 is connected to the test head 3 via the pogo pins 4. Here, the calibration is performed only up to the pogo pins 4 and the test board 5
Do not perform calibration of. By doing so, IC tester body 2, since it is assumed to have all the signal lines A ₁ to A _n are the same delay value, the signal at the contact portion of the IC in the socket SO _n the socket It is delayed by (delay time T _n -delay time T _n-1 ) from the signal at the contact portion with the IC at SO _n-1 .
For example, the signal at the contact portion of the IC in the socket SO _2, rather than the signal at the contact portion of the IC in the socket SO ₁ (delay time T ₂ - delay time T ₁₎ delayed by.

[0018] Thus, at the time of switching of the signal level of the test signal, in each of the through current in each IC, through current IC inserted into the socket SO _n than IC inserted into the socket SO _n-1 Is also delayed by (delay time T _n -delay time T _n-1 ). Therefore, each IC
Timing of the peak of a through current from being displaced respectively, the peak value of the current flowing from the test board 5 be smaller as compared with the case where the length of each signal line of the signal line group A ₁ to A _n in the same in I understand.

As described above, the IC according to the first embodiment
Test board tester, and a signal line group A ₁ to A _n are used to output the test board 5 a predetermined test signal to each socket SO ₁ to SO _n to different wire lengths, socket SO ₁ ... The arrival delay time of the test signal to each of the ICs inserted into .about.SO _n is made different. Therefore, the peak value of the current flowing from the test board 5 can be reduced as compared with the case where the respective wiring lengths of the signal line groups A ₁ to A _n in the same, increasing the number of IC which can simultaneously measure Therefore, test efficiency can be improved.

Embodiment 2 In the first embodiment, although the signal line group A ₁ to A _n into different wire lengths, divided socket SO ₁ to SO _n groups of a predetermined number, the wiring length of the signal line group for each said group This may be changed, and such a configuration is referred to as a second embodiment of the present invention. FIG. 3 is a schematic configuration diagram showing an example of an IC tester test board according to Embodiment 2 of the present invention.
3A shows a front view, and FIG. 3B shows a plan view. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here. Further, in the second embodiment, for the sake of simplicity of description, a case where IC sockets SO _{1 to} SO _n are divided into two groups will be described as an example.

As shown in FIG. 3, the test board 5
Includes sockets SO _{1 to} SO _n corresponding to signal line groups A _1.
To A _n, they are connected in the power supply line P ₁ to P _n and GND lines G ₁ ~G _n. The sockets SO _{1 to} SO _n are divided into two groups GR1 and GR2, and the power lines P ₁
To P _n and GND lines G _{1 to} G _n have the same length, but the length of the signal line group in the socket of the group GR1 and the length of the signal line group in the socket of the group GR2. Each is different.

Here, among the sockets SO _{1 to} SO _n , for example, each socket where n is an odd value is defined as a group GR 1, and n
Each socket having an even number is a group GR2. The wiring length of the signal line group corresponding to each socket of the group GR1 is the same, and each of the constituent signal lines is the same in each of the signal line groups of the group GR1. Similarly, the wiring length of the signal line group corresponding to each socket of the group GR2 is the same, and
Each of the constituent signal lines has the same length. In FIG. 3, the group GR2
In the example shown, the signal line group has a longer wiring length than the signal line group of the group GR1.

In such a configuration, a test n
Sockets SO corresponding to each IC ₁~ SO_nTo each
Insert the same test into all sockets SO₁~ SO_n
If the test is performed at the same time,
O₁~ SO_nWhen the test signal input to the
And each socket SO₁~ SO_nEach I inserted in
A through current flows at C. Therefore, each socket SO₁~
SO_nTransient currents flow through the test board
A peak current flows through the node 5.

However, since the length of each signal line of the signal line group of the group GR1 is different from the length of each signal line of the signal line group of the group GR2, the test board 5
The timing at which each transient through current flowing through each socket of R1 reaches a peak, and the timing from the test board 5 to the group GR
2 is different from the timing at which the transient through currents flowing through the sockets 2 are different from each other, and the peaks of the current flowing through the test board 5 are different from the case where the timings at which the respective through currents peak are all the same. The value decreases.

FIG. 4 is a diagram showing waveforms at various parts of the test board for the IC tester shown in FIG. 3, and will be described in more detail with reference to FIG. In FIG. 4, the same components as those in FIG. 2 are indicated by the same reference numerals. From the test board 5, each socket SO ₁ via the signal line group A ₁ ~A _n ~SO _n
, A predetermined test signal that rises from a low level to a high level is output. Accordingly, the respective contact portions with the ICs in the sockets of the group GR1 are provided with the respective contact portions with the ICs in the sockets of the group GR2 after the delay time Ta generated by the corresponding signal line group. Each of the test signals is input after a delay time Tb generated by the corresponding signal line group. Since each signal line length in each signal line group of the group GR2 is longer than each signal line length in each signal line group of the group GR1, the delay time Tb> the delay time Ta.

On the other hand, calibration is performed only up to the pogo pins 4 and calibration of the test board 5 is not performed. By doing so, I
C tester body 2, since it is assumed to have all the signal lines A ₁ to A _n are the same delay values, group GR2
The signal at the contact portion with the IC in each socket of the group GR1 lags behind the signal at the contact portion with the IC in each socket of the group GR1 by (delay time Tb-delay time Ta).
For example, the signal at the contact portion of the IC in the socket SO _2, rather than the signal at the contact portion of the IC in the socket SO ₁ delayed (delay time Tb- delay time Ta).

Therefore, when the signal level of the test signal is switched, the respective through currents in the respective ICs are also reduced by the I inserted in the socket of the group GR2.
The through current of C lags behind the IC inserted in the socket of group GR1 by (delay time Tb-delay time Ta). For this reason, the peak timing of the through current in each IC of the group GR1 and the peak timing of the through current in each IC of the group GR2 are shifted, so that the peak value of the current flowing through the test board 5 is the signal line group A ₁ to as compared with the case where the same respective line length a _n becomes it can be seen small.

In FIGS. 3 and 4, the socket SO₁
~ SO_nInto two groups depending on whether n is odd or even.
The above description is an example, but this is only an example.
SO₁~ SO_nTo the socket SO₁~ SO_k(K is k
<N a natural number) and the socket SO _{k + 1}~ SO_nTwo guru
May be divided into groups. Also, the socket SO₁
~ SO_nIs divided into two groups as examples.
As described above, this is an example, and the socket SO₁~ SO_nTo
Arbitrary number m (m is a natural number of 2 ≦ m <n)
The length of the signal lines in the signal line group is different for each group.
What should I do?

In this case, the peak value of the current flowing through the test board 5 decreases as the number m of groups increases, but if the length of the wiring is increased, the influence of noise or an increase in the wiring space is increased. Occurs. But,
The problem is a grouping method, for example, the number of groups m
And adjusting the balance with the allowable current of the test apparatus. Further, as the number of sockets in each group becomes substantially equal, the peak value of the current flowing through the test board 5 becomes smaller.

As described above, the IC according to the second embodiment
Test board tester, socket SO ₁ to SO _n were divided into groups of a predetermined number, the signal line group A which is used to output the test board 5 a predetermined test signal to each socket SO ₁ to SO _n and a ₁ to a _n into different wiring lengths for each group respectively, arrival delay time of the test signal to each IC inserted into the socket sO ₁ to sO _n is as different for each group. From this, test board 5
The peak value of the current flowing through can be reduced as compared with the case where the respective wiring lengths of the signal line groups A ₁ to A _n in the same, it is possible to increase the number of IC which can be simultaneously measured, the test efficiency Improvement can be achieved.

Embodiment 3 In the second first embodiment and the above embodiment has been so changing the wiring length of the signal line groups A ₁ to A _n, and the respective wiring lengths of the signal line groups A ₁ to A _n in the same, the power supply line The lengths of P _{1 to} P _n and the length of the GND lines G _{1 to} G _n may be changed, and such a configuration is referred to as a third embodiment of the present invention. FIG. 5 is a schematic configuration diagram showing an example of a test board for an IC tester according to the third embodiment of the present invention. FIG. 5 (a) shows a front view, and FIG. 5 (b) shows a plan view. I have. In FIG. 5, the case of Embodiment 1 is shown as an example, and the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here.

In FIG. 5, the lengths of the wires in the signal line groups A ₁ -A _n are the same, but the power supply lines P ₁ -P _n
, And the length of each of the GND lines G _{1 to} G _n are different from each other. On the other hand, as a wiring length of the power line P ₁ and the GND line G ₁ is the same in the socket SO _1, the wiring length of the power supply line and the GND line in the same socket are the same. In FIG. 5, with the length of the wiring between the power supply line from the power line P ₁ is sequentially increased, it is shown in the case where the length of the wiring of the GND lines are longer a GND lines G ₁ in sequence.

In such a configuration, a test n
Sockets SO corresponding to each IC ₁~ SO_nTo each
Insert the same test into all sockets SO₁~ SO_n
If the test is performed at the same time,
O₁~ SO_nWhen the test signal input to the
And each socket SO₁~ SO_nEach I inserted in
A through current flows at C. Therefore, each socket SO₁~
SO_n, Transient currents flow through each
Flows through the test board 5. However, the power line P₁~ P_nHead of
And GND line G₁~ G_nBecause the length of the
From board 5 to socket SO₁~ SO_nTransient
The timing at which each through current peaks differs
The timing at which each of the through currents peaks is the same.
Current flowing through the test board 5 compared to the same
Peak value decreases.

FIG. 6 is a diagram showing the waveform of each part of the test board for the IC tester shown in FIG. 5, which will be described in more detail with reference to FIG. In FIG. 6, the same components as those in FIG. 2 are denoted by the same reference numerals, and Ig _{1 to} Ig _n indicate through holes flowing to respective contact portions between the corresponding power supply lines P _{1 to} P _n and the test board 5. The current is shown. Test board 5
From via the signal line group A ₁ to A _n each socket SO ₁ to S
Against O _n, a predetermined test signal that rises from the Low level to the High level is outputted. Along with this, the respective contact portions of the IC in the socket SO ₁ to SO _n, the test signal are input after the delay time T caused by the signal line group A ₁ to A _n.

On the other hand, calibration is performed up to the test board 5 as usual. Sockets SO _{1 to} SO _n
Are operated at the same time, and a through current flows when the signal level of the test signal is switched. Accordingly, the socket SO ₁ each through current from the IC in to SO _n, the power supply line P ₁ to P _n and the delay time caused by the GND lines G ₁ ~G _n Tc ₁ ~Tc _n
Later, they are transmitted to the test board 5, respectively. Power line P ₁ ~P _n
Each wiring length, as well as to become sequentially longer from the power line P _1, the respective wiring lengths of GND lines G ₁ ~G _n in,
From what has been so that sequentially increase from the GND line G _1, the delay time Tc ₁ <delay time Tc ₂ <............ <delay time Tc
It becomes _n .

Therefore, the peak timing of each through current flowing through each of the sockets SO _{1 to} SO _n is shifted, so that the peak values of the current flowing through the test board 5 are the power supply lines P _{1 to} P _n and the GND lines G ₁ to G ₁ . It can be seen that the length becomes smaller compared to the case where the length of each wiring of G _n is the same.

Next, as in the second embodiment, the socket S
O _{1 to} SO _n may be divided into a predetermined number of groups, and the wiring length of the power supply line and the GND line may be changed for each group. FIG. 7 is a schematic configuration diagram showing an example of an IC tester test board in such a case.
7A is a front view, and FIG. 7B is a plan view. In FIG. 7, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 7, the IC sockets SO _{1 to} SO S are shown for easy understanding.
A case in which divided O _n into two groups is shown as an example.

As shown in FIG. 7, the socket SO ₁
To SO _n are divided into two groups GR1 and GR2, eg, n is each socket odd values a group GR1, n is a group of the socket even value GR2
And Socket SO ₁ signal line group in ~SO _n A ₁ ~
The length of the wiring of the A _n are the same respectively, the group G
The length of the power line in the socket of R1 and the length of the power line in the socket of group GR2;
The length of the GND line in the socket of the group GR1 is different from the length of the GND line in the socket of the group GR2. Note that FIG. 7 shows an example in which the power supply line and the GND line of the group GR2 have longer wiring lengths than those of the group GR1.

In such a configuration, calibration is performed up to the test board 5 as usual. The sockets SO _{1 to} SO corresponding to the n ICs to be tested
O _n respectively inserted into the case of performing simultaneously the same test on all sockets SO ₁ to SO _n, upon switching from the test board 5 of the test signal to be input to each socket SO ₁ to SO _n, each socket SO ₁ through current flows in each of the IC inserted into to SO _n. Therefore, a transient power supply current is supplied from the test board 5 to each of the sockets SO _{1 to} SO _n .

However, each power supply line of group GR1 and G
Since the respective lengths of the ND line and the respective lengths of the power supply line and the GND line of the group GR2 are different, the timing at which the transient current supplied from the test board 5 to the respective sockets of the group GR1 becomes a peak, The timing at which the peak of the transient current supplied from the test board 5 to each socket of the group GR2 differs from the timing at which the peak of the transient current is all the same. The peak value of the current flowing through the board 5 decreases.

FIG. 8 is a diagram showing waveforms at various parts of the IC tester test board shown in FIG. 7, and will be described in more detail with reference to FIG. In FIG. 8, the same components as those in FIG. 6 are denoted by the same reference numerals. From the test board 5, each socket SO ₁ via the signal line group A ₁ ~A _n ~SO _n
, A predetermined test signal that rises from a low level to a high level is output. Along with this, the respective contact portions of the IC in each socket SO ₁ to SO _n, after a delay time T caused by the corresponding signal line group A ₁ to A _n, the test signal is simultaneously inputted respectively . The ICs inserted in the sockets SO _{1 to} SO _n operate simultaneously, and a through current flows when the signal level of the test signal changes.

However, each wiring length of the power supply line and the GND line in each socket of the group GR2 is different from that of the group GR1.
Are longer than the respective wiring lengths of the power supply line and the GND line in each socket. From this, each IC of the group GR1 is:
A through current flows after a delay time Td from the input of the test signal whose signal level is switched, and a through current flows after a delay time Te from the input of the test signal whose signal level is switched to each IC of the group GR2. Time T
d <the delay time Te.

Therefore, the peak timing of the current flowing from the test board 5 to each socket of the group GR1 is different from the peak timing of the current flowing from the test board 5 to each socket of the group GR2. peak is can be seen that small compared to the case where the same respective line lengths of the power lines P ₁ to P _n and GND lines G ₁ ~G _n.

[0044] In FIG. 7 and 8, as in the second embodiment, the socket SO ₁ to SO _n, but n has been described as an example a case divided into two groups with odd or even number This is merely an example, and the sockets SO _{1 to} SO _n may be divided into two groups: sockets SO _{1 to} SO _k (k is a natural number of k <n) and sockets SO _{k + 1 to} SO _n. Good. Also, the case where the sockets SO _{1 to} SO _n are divided into two groups has been described as an example. However, this is an example, and the sockets SO _{1 to} SO _n are set to an arbitrary number m (m is 2 ≦ m).
<N is a natural number), and the length of the power supply line and the length of the GND line may be different for each group.

In such a case, the peak value of the current flowing through the test board 5 decreases as the number m of groups increases, but if the length of the wiring is increased, the influence of noise or an increase in the wiring space is increased. Occurs. But,
The problem is a grouping method, for example, the number of groups m
And adjusting the balance with the allowable current of the test apparatus. Furthermore, as the number of sockets in each group becomes substantially equal, the peak value of the current flowing from the test board 5 becomes smaller.

As described above, the IC according to the third embodiment
Test board tester, the signal line group A ₁ to A _n are used to output the test board 5 a predetermined test signal to each socket SO ₁ to SO _n with each the same wiring length, the test board power line for supplying power to each socket SO ₁ to SO _n from 5 P ₁ to P _n and GND lines G ₁ ~G _n
Of the sockets SO ₁ -SO _n
The delay time of the through current flowing through each IC inserted in each group was made different for each group. Therefore, the peak value of the current flowing through the test board 5 can be reduced as compared with the case of the same wiring length of the power line P ₁ to P _n and GND lines G ₁ ~G _n, can be simultaneously measured Since the number of ICs can be increased, test efficiency can be improved.

It should be noted that the first to third embodiments are used.
Is merely an example, and the present invention is not limited to this, and can be applied to various socket arrangements.

[0048]

According to the test board for an IC tester according to the present invention, in the signal line group used when outputting a predetermined test signal from the test board to each IC socket,
The signal lines having the same length constituting the signal line group were set to have different lengths according to the IC socket for each signal line group, and the arrival delay time of the test signal was varied according to the IC socket. From this, the peak value of the current flowing through the test board can be made smaller than when all the signal lines of all the signal line groups have the same length, and the number of ICs that can be measured simultaneously can be increased. Therefore, test efficiency can be improved.

The test board for an IC tester according to claim 2 is the same as in claim 1, but more specifically, each signal line group is
Each C socket was made up of signal lines having the same length but different lengths. Therefore, the timings at which the transient currents flowing through the IC sockets become peaks differ from each other, and the peak value of the current flowing through the test board can be reduced. Therefore, the number of ICs that can be measured simultaneously can be increased, and the test efficiency can be improved.

According to a third aspect of the present invention, in the IC tester test board according to the first aspect, each of the IC sockets is divided into a plurality of groups, and each of the signal line groups is different in length from each group. Length of each signal line,
The arrival delay time of the test signal differs for each group. From this, the peak value of the current flowing through the test board can be made smaller than when all the signal lines of all the signal line groups have the same length, and the number of ICs that can be measured simultaneously can be increased. Therefore, test efficiency can be improved.

According to the test board for an IC tester of the present invention, each signal line of a signal line group used when outputting a predetermined test signal from the test board to each IC socket has the same length. , Test board to each IC
By setting the length of the power supply line and the GND line for supplying power to the socket to a length corresponding to the IC socket, each IC
The delay time of the through current flowing through the IC inserted into the socket is changed. From this, the peak value of the current flowing through the test board can be reduced as compared with the case where all power supply lines and GND lines have the same length,
Since the number of ICs that can be simultaneously measured can be increased, test efficiency can be improved.

The test board for an IC tester according to the present invention is preferably arranged such that a specific test signal is output from the test board to each IC socket. Insert the signal lines into each IC socket by making the lengths of the signal lines the same and the length of the power supply line and the GND line that supply power from the test board to each IC socket to be different for each IC socket. The delay times of the through currents flowing through the ICs are different from each other. Accordingly, the peak value of the current flowing through the test board can be reduced, and the number of ICs that can be simultaneously measured can be increased, so that the test efficiency can be improved.

According to a sixth aspect of the present invention, in the test board for an IC tester according to the fourth aspect, all the signal lines constituting each signal line group have the same length, and each IC socket has a plurality of groups. And each power line and each GND
By setting the length of the wire to be different for each group, the delay time of the through current flowing through the IC inserted into each IC socket is made different for each group. From this, the peak value of the current flowing through the test board can be reduced as compared with the case where all power supply lines and GND lines have the same length, and the number of ICs that can be measured simultaneously can be increased. Thus, test efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating an example of an IC tester test board according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing waveforms of respective parts of the IC tester test board shown in FIG.

FIG. 3 is a schematic configuration diagram showing an example of an IC tester test board according to a second embodiment of the present invention.

FIG. 4 is a diagram showing waveforms at various parts of the IC tester test board shown in FIG. 3;

FIG. 5 is a schematic configuration diagram showing an example of an IC tester test board according to a third embodiment of the present invention.

6 is a diagram showing waveforms at various parts of the IC tester test board shown in FIG. 5;

FIG. 7 is a schematic configuration diagram showing another example of an IC tester test board according to Embodiment 3 of the present invention.

8 is a diagram showing waveforms of respective parts of the IC tester test board shown in FIG. 7;

FIG. 9 is a schematic configuration diagram showing a conventional test board for an IC tester.

10 is a diagram showing waveforms at various parts of the test board for an IC tester shown in FIG. 9;

[Explanation of symbols]

1 IC tester, 2 IC tester main body, 3 test head, 4 pogo pin, 5 test board, SO
_{1 to} SO _n socket, A _{1 to An} signal line group, P _{1 to} P _n
Power line, G ₁ ~G _n GND line, GR1, GR2
group.

Claims (6)

[Claims] An IC tester test board for connecting a main body of an IC tester for testing an IC and a plurality of IC sockets, wherein each power supply line for supplying power to a predetermined terminal of a corresponding IC socket is provided. Each GND for grounding a predetermined terminal of the corresponding IC socket
Wire and a predetermined terminal of each IC socket.
A plurality of signal lines having a plurality of signal lines of the same length, the lengths corresponding to the C sockets.
Test board for C tester. 2. The power supply lines have the same length, the GND lines have the same length, and the signal line groups have the same length different in length for each IC socket. 2. The test board for an IC tester according to claim 1, comprising a plurality of signal lines. 3. The power supply lines have the same length and the GND lines have the same length. The IC sockets are divided into a plurality of groups. 2. The I according to claim 1, comprising a plurality of signal lines of the same length, each of which has a different length.
Test board for C tester. 4. An IC tester test board for connecting a main body of an IC tester for testing an IC to a plurality of IC sockets, wherein power is supplied to predetermined terminals of the corresponding IC sockets. In accordance with each power supply line having a length corresponding to each of the IC sockets and a predetermined terminal of the corresponding IC socket are grounded, corresponding to each GND line having a length corresponding to each of the IC sockets, and corresponding to a predetermined terminal of each IC socket A test board for an IC tester, comprising: 5. All the signal lines constituting each of the signal line groups have the same length, and the power supply lines and the G lines
The I / D line according to claim 4, wherein the ND line has a different length for each IC socket, and has the same length of the power supply line and the GND line for the same IC socket.
Test board for C tester. 6. All the signal lines constituting each of the signal line groups have the same length, the IC sockets are divided into a plurality of groups, and each power supply line and each GND line are 5. The test board for an IC tester according to claim 4, wherein the power supply line and the GND line have the same length for the same IC socket.