JPWO2010007770A1 - Test equipment - Google Patents

Abstract

The PE board 10 is provided for a plurality of pins of the DUT. The plurality of I / O pins Pio are connected to the corresponding DUT pins via cables. Each of the plurality of first switches K1 is connected to the corresponding I / O pin Pio at one end. Each of the plurality of drivers DR outputs a test signal to the corresponding pin. Each of the plurality of comparators CP determines the level of the test signal output from the corresponding pin. The plurality of second switches K2 are connected to the other ends of the first switches K1 corresponding to the respective one ends. The short wiring W1 connects the other ends of the plurality of second switches K2.

Description

  The present invention relates to a semiconductor device test apparatus, and more particularly to pin electronics timing calibration technology.

  A test apparatus for testing a semiconductor device includes pin electronics. The pin electronics includes a driver that outputs a signal to a corresponding pin of the device under test (DUT) and a comparator that determines the level of the signal output from the corresponding pin. Usually, a socket board for mounting the DUT and a cable for connecting the socket board and the pin electronics are provided between the pin electronics and the pins of the DUT. Therefore, a finite delay time is required for the signal to propagate between the pin electronics and the DUT pin.

  The line length to the pins of the pin electronics and the DUT, that is, the propagation delay is different for each pin. In order to make this propagation delay uniform, a technique for calibrating a test apparatus using a calibration board (also referred to as a phase difference correction board or a short device) has been proposed (see Patent Documents 1 and 2).

FIG. 1 is a block diagram showing a configuration of a test apparatus 200 that is calibrated by a conventional calibration board. The test apparatus 200 includes a test head 204, a mother board 206, and a main frame (not shown). The test head 104 includes a plurality of pin electronics boards PE1 to PE3.
At the time of testing, a socket board (not shown) is attached to the mother board 106 instead of the calibration board 202, and a device under test is attached to the socket board. Each pin electronics board PE includes a driver DR, a comparator CP, and a switch K. The test signal output from the driver DR is supplied to the device under test via the cable 208 of the motherboard 206. A signal from the device under test is input to the comparator CP via the cable 208, and its level is determined.

  At the time of calibration, a calibration board 202 is mounted instead of the socket board. The calibration board 202 includes a plurality of wirings 203 for connecting a plurality of cables 208 provided on the mother board 206 with the same length.

JP 2000-314764 A JP 2004-157129 A

  In the configuration of FIG. 1, when the mother board 206 is newly developed, the calibration board 202 corresponding to the mother board 206 has to be redesigned, which causes problems such as a prolonged development cycle and an increase in development cost.

  The present invention has been made in view of such a situation, and an object thereof is to provide a test apparatus that can be calibrated without using a calibration board.

  One embodiment of the present invention relates to a test apparatus for testing a device under test including a plurality of pins. This test apparatus includes a pin electronics board provided for a plurality of pins of a device under test. The pin electronics board includes a plurality of input / output terminals, a plurality of first switches, a plurality of drivers, a plurality of comparators, a plurality of second switches, and wiring provided for each of the plurality of pins. Each of the plurality of input / output terminals is connected to a corresponding pin via a cable on the motherboard. One end of each of the plurality of first switches is connected to a corresponding input / output terminal. Each of the plurality of drivers outputs a test signal to a corresponding pin via a corresponding first switch and a corresponding input / output terminal. Each of the plurality of comparators receives the test signal output from the corresponding pin via the corresponding input / output terminal and the corresponding first switch, and determines its level. Each of the plurality of second switches is connected to the other end of the corresponding first switch. The wiring connects the other ends of the plurality of second switches.

  According to this aspect, since the output signal of any driver can be supplied to any comparator by controlling the on / off states of the plurality of second switches, calibration can be performed without using a calibration board. Can be realized.

  The pin electronics board may further include a termination resistor connected to one end of the wiring. By providing the termination resistor, signal reflection at the end of the wiring can be suppressed.

  Another aspect of the present invention also relates to a test apparatus for testing a device under test including a plurality of pins. This test apparatus includes a plurality of pin electronics boards provided for each of a plurality of pins of a device under test. Each pin electronics board is compatible with the corresponding pins through input / output terminals connected via cables on the motherboard, the first switch with one end connected to the input / output terminals, the first switch and the input / output terminals. A driver that outputs a test signal to the corresponding pin, a comparator that receives the test signal output from the corresponding pin via the input / output terminal and the first switch, determines its level, a correction terminal, and one end that A second switch connected to the other end of the switch and having the other end connected to the correction terminal. The plurality of pin electronics boards are configured to be connectable to a back board that connects the correction terminals provided in each of them with the same length.

  According to this aspect, by controlling the on / off state of the second switch of each pin electronics board with the backboard connected, any driver output signal can be supplied to any comparator. Calibration can be realized without using a calibration board.

  The backboard may be placed in a test head where a plurality of pin electronics boards are placed.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, calibration can be performed without using a calibration board.

It is a block diagram which shows the structure of the test apparatus calibrated with the conventional calibration board. It is a block diagram which shows a part of test apparatus which concerns on the 1st Embodiment of this invention. FIGS. 3A and 3B are circuit diagrams showing the calibration process of the PE board. It is a circuit diagram which shows the modification of the PE board which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the test apparatus which concerns on 2nd Embodiment.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

(First embodiment)
FIG. 2 is a block diagram showing a part of the test apparatus 100 according to the first embodiment of the present invention. The test apparatus 100 tests a device under test (DUT) 110 including a plurality of device pins P. The test apparatus 100 gives a test pattern PAT to the DUT 110, and compares the output data output from the DUT 110 with the expected value data EXP according to the test pattern, and measures the quality or performance of the DUT 110, or is defective. Identify the location. For example, the DUT 110 is a memory.

  First, an overview of the overall configuration of the test apparatus 100 will be described. Since the outline described here is an architecture used for a general test apparatus, details are omitted. The test apparatus 100 includes a pin electronics (PE) board 10, a pattern generator (PG) 1, a timing generator (TG) 2, a determination unit 5, a motherboard (MB) 12, and a socket board (SB) 14.

  The pattern generator 1, the timing generator 2, the determination unit 5, and the PE board 10 are arranged in a casing called a test head 16. The test head 16 is connected to a main frame (not shown). When the test program is executed by the main frame, the test head 16 tests the DUT 110 according to the program.

  The pattern generator 1 generates a test pattern PAT corresponding to the test program. At the same time, the pattern generator 1 generates expected value data EXP corresponding to the test pattern PAT. The timing generator 2 adjusts the phase (timing) of the test pattern PAT every test cycle, that is, every cycle of the test pattern PAT. The test pattern PAT whose timing is adjusted by the timing generator 2 is output to the PE board 10. Details of the PE board 10 will be described later.

  A motherboard 12 is connected to the PE board 10. The mother board 12 has a plurality of cables CBL for transmitting the test pattern. The number and arrangement (pin arrangement) of the plurality of device pins P of the DUT 110 differ depending on the DUT 110. In order to avoid a design change of the test apparatus 100 for different DUTs 110, a socket board 14 is mounted between the motherboard 12 and the DUT 110. The socket board 14 has a pin arrangement corresponding to the mother board 12 on one side, and a pin arrangement corresponding to the DUT 110 on the other side. The socket board 14 is used by being exchanged according to the pin arrangement of the DUT 110.

  The test pattern PAT output from the timing generator 2 is supplied to the corresponding device pin P of the DUT 110 via the PE board 10, the motherboard 12, and the socket board 14. Further, output data output from a device pin P with the DUT 110 is input to the determination unit 5 via the socket board 14, the motherboard 12, and the PE board 10. The determination unit 5 compares the output data Dout and the expected value data EXP for each test cycle, and outputs pass / fail data PASS indicating matching or mismatching.

  In FIG. 2, for simplicity of explanation and ease of understanding, the pattern generator 1, the timing generator 2, and the determination unit 5 are shown only for a single channel. The same is provided for the channel.

  The above is the overall configuration of the test apparatus 100. The test apparatus 100 according to the present embodiment is characterized by the PE board 10. Hereinafter, the configuration of the PE board 10 will be described in detail.

  The PE board 10 is provided in common for a plurality of pins of the DUT 110. The number of PE boards 10 is determined according to the total number of pins of the DUT 110 and the number of pins assigned to one PE board 10.

  The PE board 10 includes a plurality of drivers DR, a plurality of comparators CP, a plurality of first switches K1, a plurality of second switches K2, a plurality of input / output terminals (I / O pins) Pio, and a short wiring W1. It is mounted on the circuit board.

  A plurality of I / O pins Pio are provided for each of a plurality of device pins P of the DUT 110. FIG. 2 shows a case where three I / O pins Pio are assigned to three device pins P, respectively, but the number is not limited and can be arbitrarily designed. Each of the plurality of I / O pins Pio is connected to the corresponding device pin P via the cable CBL and the socket board 14 on the motherboard 12. That is, the PE board 10 outputs the test pattern PAT to the DUT 110 via these I / O pins Pio or receives the output data Dout from the DUT 110.

  The plurality of first switches K1 are provided for each of the plurality of device pins P. One end of each of the plurality of first switches K1 is connected to the corresponding I / O pin Pio.

  The plurality of drivers DR are provided for each of the plurality of device pins P. Each of the plurality of drivers DR receives the test pattern PAT from the timing generator 2 and applies the test pattern PAT (test signal) to the corresponding device pin P via the corresponding first switch K1 and the corresponding I / O pin Pio. Is output.

  The plurality of comparators CP are provided for each of the plurality of device pins P. Each of the plurality of comparators CP receives the output data Dout (test signal) output from the corresponding device pin P via the corresponding I / O pin Pio and the corresponding first switch K1. Each comparator CP compares the level of the input output data Dout with a predetermined threshold voltage, and determines the level. More specifically, the comparator CP latches the output data Dout at a timing corresponding to the strobe signal output from the timing generator 2. Therefore, the comparator CP is also referred to as a timing comparator.

  The plurality of second switches K2 are provided for each of the plurality of device pins P. Each of the plurality of second switches K2 has one end connected to the other end of the corresponding first switch K1. The short wiring W1 connects the other ends of the plurality of second switches K2. Preferably, the short wiring W1 connects the other ends of the adjacent second switches K2 with the same length.

  The above is the configuration of the PE board 10. According to the PE board 10 described above, the timing of the driver DR and the comparator CP can be adjusted without using a calibration board as described below.

FIGS. 3A and 3B are circuit diagrams showing the calibration process of the PE board 10. In the calibration process, all the first switches K1 are turned off. In the first step, any two of the plurality of second switches K2 are turned on and the rest are turned off. In the first step shown in FIG. 3A, the second switches K2 ₁ and K2 ₂ for the first channel and the second channel are turned on, and the second switch K2 _{3 for} the third channel is turned off.

In the first step, the timings of the driver DR and the comparator CP connected to the turned on second switch K2 are adjusted. Specifically, the following two processes are performed.
(1) A test pattern (calibration pattern) PAT is output from the driver DR1 of the first channel, and the value is evaluated by the comparator CP of the second channel.
(2) The test pattern PAT is output from the driver DR2 of the second channel, and the value is evaluated by the comparator CP1 of the first channel.
Through these steps, the timings of the drivers DR1 and DR2 and the comparators CP1 and CP are adjusted.

Subsequently, the process proceeds to the second step. In the second step, one of the plurality of second switches K2 turned on in the first step (in this example, the second switch K2 ₂ of the second channel) and one turned off in the first step (this In the example, the second switch K2 ₃ ) of the third channel is turned on.

  Also in the second step, the timings of the driver DR and the comparator CP connected to the turned-on second switch K2 are adjusted by the same procedure as in the first step.

Through the first step and the second step, as the two reference drivers DR2 and comparator CP2 is connected to the second switch K2 ₂ which is turned on in both steps, align the timing of all drivers DR2 and comparator CP2 be able to.

  As described above, when the PE board 10 according to the embodiment is used, the timing of each channel can be calibrated without attaching the calibration board to the motherboard 12 as in the prior art. Further, the conventional system shown in FIG. 1 has a problem in that, since the calibration data passes through the cable on the motherboard at the time of calibration, the influence cannot be ignored when the cable is long. On the other hand, in the test apparatus 100 of FIG. 2, since calibration can be performed without going through the cable on the motherboard, the calibration accuracy can be increased.

  FIG. 4 is a circuit diagram showing a modification of the PE board 10 according to the first embodiment. The PE board 10a according to the modification further includes a first termination resistor RT1 and a second termination resistor RT2 in addition to the configuration of FIG. The first termination resistor RT1 and the second termination resistor RT2 are connected to both ends E1 and E2 of the short wiring W1, respectively.

When using a PE board 10 of FIG. 2, in a first step of FIG. 3 (a), of the short wires W1, a portion to be connected to the second switch K2 ₃ to turn off the open. Therefore, the test pattern PAT output from the drivers DR1 and DR2 may be reflected and affect the calibration accuracy. Therefore, by providing the second termination resistor RT2 on the edge E2 side, reflection at the end of the short wiring W1 can be suppressed, and the calibration accuracy can be improved. For the same reason, the reflection in the second step of FIG. 3B can be suppressed by providing the first termination resistor RT1.

(Second Embodiment)
FIG. 5 is a circuit diagram showing a configuration of a test apparatus 100b according to the second embodiment. The test apparatus 100b includes a plurality of PE boards 10b _{1 to} 10b ₃ . The plurality of PE boards 10b are provided for each of the plurality of device pins P of the DUT 110 (not shown) and have the same configuration. Each of the PE boards 10b _{1 to} 10b ₃ includes an I / O pin Pio, a driver DR, a comparator CP, a first switch K1, a second switch K2, and a correction terminal Pcal.

  The I / O pin Pio is connected to a corresponding device pin via a cable on a motherboard (not shown). One end of the first switch K1 is connected to the I / O pin Pio. The driver DR outputs the test pattern PAT to the corresponding device pin via the first switch K1 and the I / O pin Pio. The comparator CP receives the output data Dout output from the corresponding device pin via the I / O pin Pio and the first switch K1, and determines its level. The second switch K2 has one end connected to the other end of the first switch K1 and the other end connected to the correction terminal Pcal.

The plurality of PE boards 10b _{1 to} 10b ₃ are arranged in the test head 16 adjacent to each other. The plurality of PE boards 10b _{1 to} 10b ₃ are configured to be connectable to the back board 18. A short wiring W2 is formed on the back board 18, and the correction terminals Pcal1 to Pcal3 provided on each of the plurality of PE boards 10b _{1 to} 10b ₃ are connected with an equal length.

The back board 18 is disposed in the test head 16 in the same manner as the plurality of PE boards 10b _{1 to} 10b ₃ . The backboard 18 may be connected to the PE board 10b in the test head 16 only at the time of calibration, and may be removed from the test head 16 when the calibration is completed. Alternatively, the PE board 10b may be connected not only during calibration but also during a normal test. In this case, it is necessary to turn off all the second switches K2 during the test.

  Note that at least one of the termination resistors RT1 and RT2 may be provided at both ends of the short wiring W2 on the backboard 18 as in FIG. In this case, reflection can be suppressed.

  The calibration in the test apparatus 100b in FIG. 5 is executed by the same procedure as in FIGS. 3 (a) and 3 (b).

  Compared to the test apparatus 100 of FIG. 2, the test apparatus 100b needs to prepare a separate backboard 18, but has the following advantages. That is, the backboard 18 is not affected by the mother board side, and therefore the backboard 18 can be used as it is even when the design of the motherboard is changed.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

DESCRIPTION OF SYMBOLS 100 ... Test apparatus, 110 ... DUT, 10 ... PE board, 12 ... Mother board, 14 ... Socket board, 16 ... Test head, 18 ... Back board, Pio ... I / O pin, Pcal ... Correction terminal, DR ... Driver, CP ... Comparator, K1 ... First switch, K2 ... Second switch, W1 ... Short wiring, RT1 ... First termination resistor, RT2 ... Second termination resistor, 1 ... Pattern generator, 2 ... Timing generator, 5 ... Determination Department.

  According to an aspect of the present invention, calibration can be performed without using a calibration board.

Claims (4)

A test apparatus for testing a device under test having a plurality of pins,
A pin electronics board provided for the plurality of pins of the device under test;
The pin electronics board is:
A plurality of input / output terminals provided for each of the plurality of pins, each of which is connected to a corresponding pin via a cable on the motherboard;
A plurality of first switches provided for each of the plurality of pins, each one end of which is connected to the corresponding input / output terminal;
A plurality of drivers provided for each of the plurality of pins, each of which outputs a test signal to a corresponding pin via the corresponding first switch and the corresponding input / output terminal;
A plurality of comparators provided for each of the plurality of pins, each of which receives a test signal output from a corresponding pin via the corresponding input / output terminal and the corresponding first switch, and determines a level thereof;
A plurality of second switches provided for each of the plurality of pins, each one end of which is connected to the other end of the corresponding first switch;
Wiring connecting the other ends of the plurality of second switches;
A test apparatus comprising: The pin electronics board is:
The test apparatus according to claim 1, further comprising a termination resistor connected to one end of the wiring. A test apparatus for testing a device under test having a plurality of pins,
A plurality of pin electronics boards provided for each of the plurality of pins of the device under test;
Each pin electronics board
I / O terminals connected via corresponding pins and cables on the motherboard,
A first switch having one end connected to the input / output terminal;
A driver for outputting a test signal to a corresponding pin via the first switch and the input / output terminal;
A comparator that receives a test signal output from a corresponding pin via the input / output terminal and the first switch, and determines a level thereof;
A correction terminal;
A second switch having one end connected to the other end of the first switch and the other end connected to the correction terminal;
Including
The test apparatus according to claim 1, wherein the plurality of pin electronics boards are configured to be connectable to a backboard that connects the correction terminals provided at the same length.   The test apparatus according to claim 3, wherein the backboard is disposed in a test head in which the plurality of pin electronics boards are disposed.

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