TWI384240B - Test apparatus - Google Patents

Description

Test device

The present invention is a test apparatus for a semiconductor component, particularly a technique for timing calibration of a pin electronics.

In the test set of the test semiconductor component, a foot interface circuit is provided, the foot end dielectric circuit comprises: a driver, a signal outputting to a corresponding foot end of the tested component (DUT); and a comparator for determining the corresponding foot The level of the signal output by the terminal. Typically, between the foot interface circuit and the foot end of the DUT, a socket board is provided for mounting the DUT, and a cable is used to connect the socket board and the foot interface circuit. Therefore, a limited time delay occurs when a signal is transmitted between the foot interface circuit and the foot of the DUT.

The length of the line between the foot interface circuit and the foot of the DUT is the transmission delay, which is different at each leg. In order to uniformize the transfer delay, it is proposed to use a calibration board (also referred to as a phase correction board or a short device) to correct the test apparatus (refer to Patent Documents 1 and 2).

FIG. 1 shows a block diagram of the configuration of the test apparatus 200 using a previous calibration plate. The test apparatus 200 is configured to include a test head 204 and a motherboard 206 and a main frame (not shown). The test head 204 includes a plurality of foot interface boards PE1~PE3.

At the time of testing, the motherboard 206 device socket board (not shown) replaces the calibration board 202, and the tested components are mounted on the socket board. Each of the foot interface circuit boards PE is provided with a driver DR, a comparator CP and a switch K, respectively. The test signal output from the driver DR is supplied to the device under test through the cable 208 of the motherboard 206. The signal output from the device under test is input to the comparator CP through the cable 208 to determine its level.

At the time of calibration, the calibration plate 202 is placed on the motherboard 206 in place of the socket board. The calibration board 202 is provided with a plurality of wires 203 for connecting with the plurality of cables 208 of the motherboard 206 at the same length.

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2000-314764

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2004-157129

According to the configuration of FIG. 1, when the mother board 206 is newly developed, the calibration board 202 corresponding to the mother board 206 must be redesigned, so that the development cycle is prolonged and the development cost is increased.

In view of the foregoing, it is an object of the present invention to provide a test apparatus that can be calibrated without the use of a calibration plate.

One aspect of the invention is a test apparatus for testing a component under test having a plurality of foot ends. The test device is provided with a foot interface circuit board relative to a plurality of foot ends of the component under test. The foot interface circuit board includes: a plurality of input and output terminals disposed for each of the plurality of foot ends, a plurality of first switches, a plurality of drivers, a plurality of comparators, a plurality of second switches, and wiring. A plurality of input and output terminals are respectively connected to corresponding foot ends through cables on the motherboard. One end of each of the plurality of first switches is connected to a corresponding input and output terminal. The plurality of drivers respectively output test signals to the corresponding foot ends through the corresponding first switches and corresponding input and output terminals. The plurality of comparators respectively receive the test signals outputted from the corresponding foot ends through the corresponding input and output terminals and the corresponding first switches, and determine the level thereof. A plurality of second switches, one end of each being connected to the other end of the corresponding first switch. Wiring is connected to the other ends of the plurality of second switches.

According to this aspect, by controlling the ON and OFF states of the plurality of second switches, the output signals of any of the drivers can be supplied to any of the comparators, and the calibration can be performed even without the calibration plate. .

The foot interface board can also include a terminal resistor connected to one end of the wiring. Since the terminating resistor is provided, the reflection of the signal at the wiring terminal can be suppressed.

Another aspect of the invention is also a test apparatus for testing a component under test having a plurality of foot ends. The test device is provided with a plurality of foot interface circuit boards disposed on each of the plurality of leg ends of the device under test. Each of the foot interface circuit boards includes: an input/output terminal connected to the corresponding foot end through a cable on the motherboard; and a first switch, one end of which is connected to the input and output terminals; and a driver that passes through the first switch and the input and output terminals The corresponding foot end outputs a test signal; and the comparator receives the test signal outputted from the corresponding foot end via the input/output terminal and the first switch, and determines the level of the signal; and the correction terminal; and the second switch One end is connected to the other end of the first switch, and the other end is connected to the correction terminal. The plurality of foot interface boards are configured to be connectable to a back board such that the correction terminals provided in the respective foot interface boards can be connected in equal lengths.

According to this aspect, in the state in which the backplane is connected, by controlling the on/off state of the second switch of each of the foot interface boards, the output signal of any of the drivers can be supplied to any of the comparators, so even Calibration can also be performed without the calibration plate.

The backplane can also be disposed in a test head equipped with a plurality of foot interface boards.

Further, any combination of the above constituent elements or the replacement of the constituent elements or expressions of the present invention between methods, apparatuses, systems, and the like is also an effective form of the present invention.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments of the present invention will be described with reference to the drawings, and the same or equivalent components, components, or processes are denoted by the same reference numerals in the drawings. The present invention is not limited by the scope of the invention, and all features or combinations described in the embodiments are not necessarily limited to the essentials of the invention.

(First Embodiment)

2 is a block diagram of a portion of a test apparatus 100 in accordance with a first embodiment of the present invention. The test apparatus 100 is used to test a device under test (DUT) 110 having a plurality of component foot ends P. The test apparatus 100 supplies the test pattern PAT to the DUT 110, and compares the data (data) output by the DUT 110 in response to the test pattern with the expected value data EXP, and determines whether the DUT 110 is good or bad, or specifies a defective place. For example, the DUT 110 is a memory.

First, an outline of the overall configuration of the test apparatus 100 will be described. The outline described here is a structure used in a general test apparatus, and detailed description thereof will be omitted. The test apparatus 100 includes a foot interface circuit (PE) board 10, a pattern generator (PG) 1, a timing generator (TG) 2, a decision section 5, a motherboard (MG) 12, and a socket board (SB) 14.

The pattern generator 1, the timing generator 2, the determination unit 5, and the PE panel 10 are disposed in a casing of a so-called test head 16. The test head 16 is connected to a host not shown. When the test program is executed by the host, the test head 16 tests the DUT 110 for the program.

The pattern generator 1 generates a test pattern PAT corresponding to the test program. At the same time, the pattern generator 1 generates an expected value data EXP corresponding to the test pattern PAT. The timing generator 2 adjusts the phase (timing) of the test pattern PAT every cycle, that is, each period of the test pattern PAT. The test pattern PAT adjusted by the timing generator 2 is output to the PE board 10. The details of the PE board will be described later.

The PE board 10 is connected to the motherboard 12. The motherboard 12 has a plurality of cables CBL for transmitting test patterns. The number of component P ends of the DUT 110 and their configuration (foot configuration) vary from DUT to DUT. For different DUTs 110, to avoid design changes to the test device, a socket board 14 is disposed between the motherboard 12 and the DUT 110. The socket board 14 is provided with a leg end arrangement corresponding to the motherboard 12 on one side thereof, and a leg end arrangement corresponding to the DUT 110 on the other side. The socket board 14 is used interchangeably corresponding to the foot end configuration of the DUT 110.

The test pattern PAT output from the timing generator 2 is supplied to the corresponding component leg of the DUT 110 via the PE board 10, the motherboard 12, and the socket board 14. Further, the output data outputted from one of the leg ends P of the DUT 110 passes through the socket board 14, the mother board 12, and the PE board 10, and is input to the determination unit 5. The determination unit 5 compares the output data Dout with the expected value data EXP in each test cycle, and outputs a pass-fail data PASS indicating coincidence or inconsistency.

In addition, in FIG. 2, for the sake of simplification and ease of explanation, the pattern generator 1, the timing generator 2, and the determination unit 5 only indicate a single channel, but actually all of the other channels can be provided.

The above is the overall configuration of the test apparatus 100. The test apparatus 100 of the present embodiment has features in its PE board 10. The configuration of the PE board 10 will be described in detail below.

The PE board 10 is commonly disposed for the plurality of legs of the DUT 110, and the number of the PE boards 10 is determined according to the total number of legs of the DUT 110 and the number of legs allocated by the PE board 10.

The PE board 10 includes a plurality of drivers DR, a plurality of comparators CP, a plurality of first switches K1, a plurality of second switches K2, a plurality of input/output terminals (I/O terminals) Pio, and short wirings W1, which are mounted on On a common circuit board.

A plurality of I/O terminals Pio are disposed at each of the plurality of component leg ends P of the DUT 110. In Fig. 2, the case where the three I/O terminals Pio are individually assigned to the component pin terminals P is shown, but the number thereof is not limited and can be arbitrarily designed. Each of the plurality of I/O terminals Pio passes through the cable CBL and the socket board 14 on the motherboard 12, and is connected to the corresponding component leg end P. That is, the PE board 10 outputs the test pattern PAT to the DUT 110 via the I/O terminals Pio or receives the data Dout outputted from the DUT 110.

A plurality of first switches K1 are provided at each of the plurality of component leg ends P. One of the plurality of first switches K is connected to the corresponding I/O terminal Pio.

A plurality of drivers DR are provided at each of the plurality of component leg ends P. Each of the plurality of drivers DR receives the test pattern PAT outputted by the timing generator 2, and outputs a test pattern PAT (test signal) to the corresponding component leg P through the corresponding first switch K1 and the corresponding I/O terminal Pio.

A plurality of comparators CP are provided at each of the plurality of component leg ends P. Each of the plurality of comparators CP receives the output data Dout (test signal) output from the corresponding component pin terminal P via the corresponding I/O terminal Pio and the corresponding first switch K1. Each comparator CP compares the level of the input output data Dout with a predetermined threshold voltage to determine its level. More specifically, the comparator CP latches the output data Dout at the timing corresponding to the flash control signal output from the timing generator 2. Therefore, the comparator CP is also called a timing comparator.

A plurality of second switches K2 are provided at each of the plurality of component leg ends P. One end of each of the plurality of second switches K2 is connected to the other end of the corresponding first switch K1. The short wiring W1 is connected between the other ends of the plurality of second switches K2. Preferably, the short wiring W1 is connected between the other ends of the adjacent second switches K2 by equal lengths.

The above is the structure of the PE board 10. According to the PE board 10 described above, the timing of the driver DR and the comparator CP can be adjusted without using the calibration board as described below.

3(a) and 3(b) are circuit diagrams showing the calibration procedure of the PE board 10. At the calibration step, all of the first switches K1 are turned off (OFF). In the first step, any two of the plurality of second switches K2 are turned "ON", and the rest are (OFF). In the first step shown in FIG. 3(a), the second switches K2 ₁ and K2 ₂ of the first channel and the second channel are turned "ON", and the second switch K2 _{3 of the} third channel is turned off ( OFF).

In the first step, the timing of the driver DR and the comparator CP connected to the turned-on second switch K2 can be adjusted. Specifically, the following two processes can be performed.

(1). The test pattern (calibration pattern) PAT is output from the driver DR1 of the first channel, and the value is evaluated by the comparator CP2 of the second channel.

(2). Outputting the test pattern PAT from the driver DR2 of the second channel evaluates its value at the comparator CP1 of the first channel.

Through the above steps, the timings of the drivers DR1, DR2 and the comparators CP1, CP2 can be adjusted.

Moving on to the second step, in the second step, among the plurality of second switches K2, any one that is turned on in the first step (in this example, the second switch K2 ₂ of the second channel), and The one that is turned off in the first step (in this case, the second switch K2 ₃ of the third channel) is turned on.

In the second step, the timing of the driver DR and the comparator CP connected to the turned-on second switch K2 can also be adjusted in accordance with the same procedure as in the first step.

After the first and second steps, may be utilized during step two, the turned on second switch K2 ₂ and DR2 drive connector of the comparator CP2 as a reference, so that all the drives and DR2 consistent timing comparator CP2 .

As described above, with the PE board 10 of the present embodiment, it is not necessary to mount the calibration board on the mother board 12 as before, and the timing of each channel can be calibrated. Moreover, the previous system shown in Figure 1 needs to pass the mother because of the calibration data during calibration. The cable on the board, in the case of a long cable, there is a problem that cannot be ignored. In this regard, in the test apparatus 100 of FIG. 2, since the calibration can be performed without passing the cable on the mother board, the accuracy of the calibration can be improved.

Fig. 4 is a circuit diagram showing a modification of the PE panel 10 of the first embodiment. In the PE board 10a of the present modification, the first terminating resistor RT1 and the second terminating resistor RT2 are added to the configuration of FIG. The first terminating resistor RT1 and the second terminating resistor RT2 are respectively connected to the two ends E1 and E2 of the short wiring W1.

In the case of using the PE board 10 of Fig. 2, in the first step of Fig. 3(a), one portion of the connection of the short wiring W1 to the OFF (OFF) second switch K2 ₃ forms an open path (OPEN). Therefore, the test patterns output by the drivers DR1, DR2 reflect reflections that affect the accuracy of the calibration. Therefore, by providing the second terminating resistor RT2 on the side E2 side, reflection at the end of the short wiring W1 can be suppressed, and the accuracy of calibration can be improved. By the same token, by providing the first terminating resistor RT1, the reflection in the second step of Fig. 3(b) can be suppressed.

(Second embodiment)

FIG. 5 is a circuit diagram showing the configuration of the test apparatus 100b of the second embodiment. The test apparatus 100b includes a plurality of PE boards 10b ₁ to 10b ₃ , and the plurality of PE boards 10 b are disposed on each of the plurality of element leg ends P of the DUT 110 (not shown), and have the same configuration. Each of the PE boards 10b ₁ to 10b ₃ includes an I/O terminal Pio, a driver DR, a comparator CP, a first switch K1, a second switch K2, and a correction terminal Pcal.

The I/O pin Pio is connected to the corresponding component foot end via a cable on the motherboard (not shown). The first switch K1 has one end connected to the I/O terminal. The driver DR outputs the test pattern PAT to the corresponding component leg via the first switch K1 and the I/O terminal Pio. The comparator CP receives the output data Dout outputted from the corresponding component pin terminal through the I/O terminal Pio and the first switch K1, and determines its level. The second switch K2 has one end connected to the other end of the first switch K1, and the other end connected to the correction terminal Pcal.

10b ₁ ~ 10b ₃ PE plurality of plates arranged adjacent to each other within the test head 16. The plurality of PE sheets 10b ₁ to 10b ₃ are configured to be connectable to the back sheet 18. The short wiring W2 is formed in the back plate 18, and the correction terminals Pcal ₁ to Pcal ₃ provided in each of the plurality of PE boards 10b ₁ to 10b ₃ are connected to each other with equal length.

The back plate 18 is disposed in the test head 16 in the same manner as the plurality of PE plates 10b ₁ to 10b ₃ . The backing plate 18 is only connected to the PE board 10b in the test head 16 at the time of calibration, and can be removed from the test head 16 after the calibration is completed. Alternatively, it may be connected to the PE board 10b not only during calibration but also during normal testing. In this case, all of the second switch K2 must be disconnected during the test.

Further, similarly to FIG. 4, at least one of the terminal electric groups RT1 and RT2 can be provided at both ends of the short wiring W2 on the back plate 18, so that reflection can be suppressed.

The calibration of the test apparatus 100b of Fig. 5 can be performed by the same procedure as that of Figs. 3(a) and 3(b).

Compared with the test apparatus 100 of FIG. 2, the test apparatus 100b has the following advantages in addition to the disadvantage of preparing the backboard 18. That is, the back plate 18 is not affected by the mother board side. Therefore, when the mother board needs to be changed in design, the back board 18 can still be used as it is.

The invention has been described above by way of examples, but the examples are merely illustrative of the principles and applications of the invention. In the embodiments, various modifications or configurations may be made without departing from the spirit and scope of the invention as defined by the appended claims.

100. . . Test device

110. . . Tested component (DUT)

10. . . Foot interface board (PE board)

12. . . motherboard

14. . . Socket board

16. . . Test head

18. . . Backplane

Pio. . . I/O terminal

P. . . Component end

PAT. . . Test pattern

EXP. . . Expected value

Pcal. . . Correct foot

DR. . . driver

CP. . . Comparators

K1‧‧‧ first switch

K2‧‧‧second switch

W1, W2‧‧‧ short wiring

RT1‧‧‧ first terminating resistor

RT2‧‧‧Second terminating resistor

1‧‧‧ pattern generator

2‧‧‧Timer Generator

5‧‧‧Decision Department

1 is a block diagram showing the construction of a test apparatus that is corrected using a previous calibration plate.

2 is a block diagram of a portion of a test apparatus of a first embodiment of the present invention.

3(a) and 3(b) are circuit diagrams showing the calibration procedure of the PE board.

Fig. 4 is a circuit diagram showing a modification of the PE plate of the first embodiment.

Fig. 5 is a circuit diagram showing the configuration of the test apparatus of the second embodiment.

100‧‧‧Testing device

110‧‧‧Tested component (DUT)

1‧‧‧ pattern generator (PG)

2‧‧‧Timer Generator (TG)

5‧‧‧Decision Department

10‧‧‧PE board

12‧‧‧ Motherboard

14‧‧‧Socket board (SB)

16‧‧‧Test head

PAT‧‧‧ test pattern

EXP‧‧‧ Expected value

DR‧‧‧ drive

CP‧‧‧ comparator

K1‧‧‧ first switch

K2‧‧‧second switch

Pio‧‧I/O terminal

CBL‧‧‧ cable

Claims (4)

A test device for testing a device under test having a plurality of leg ends, the test device having a foot interface circuit board opposite to a plurality of leg ends of the device under test, the foot interface circuit board including a plurality of input and output terminals Corresponding to each of the plurality of foot ends, each of the input and output terminals is connected to the corresponding foot end through a cable on the motherboard; and the plurality of first switches correspond to respective settings of the plurality of foot ends, and one end of each of the first switches Connected to the corresponding input and output terminals; a plurality of drivers corresponding to the respective settings of the plurality of legs, each driver outputs a test signal to the corresponding leg through the corresponding first switch and the corresponding input and output terminals; Corresponding to each of the plurality of foot ends, each comparator receives the test signal outputted by the corresponding foot end through the corresponding input and output terminal and the corresponding first switch, and determines the level thereof; a switch corresponding to each of the plurality of foot ends, one end of each of the second switches and the corresponding first switch He terminal; and a wiring connected to the other edge of the second plurality of switches. The test apparatus according to claim 1, wherein the foot interface circuit board further includes a terminating resistor connected to one end of the wiring. A test device for testing a component to be tested having a plurality of leg ends, the test device having a plurality of leg interface boards disposed on a plurality of legs of the device under test, Each of the foot interface circuit boards includes an input/output terminal connected to the corresponding foot end via a cable on the motherboard; a first switch having one end connected to the input and output terminals; and a driver passing through the first switch and the input and output terminals And outputting a test signal to the corresponding foot end; the comparator receives the test signal outputted from the corresponding foot end through the input and output terminals and the first switch; the correction terminal; and the second switch, the first switch and the first end The other end of the switch is connected, and the other end is connected to the correction terminal, and the plurality of foot interface boards are configured to be connectable to the backplane, so that the correction terminals provided on the respective foot interface boards are of equal length Connected. The test device of claim 3, wherein the backplane is disposed in a test head on which the plurality of foot interface boards are mounted.