JP3069330U - Semiconductor test equipment - Google Patents

Abstract

(57) [Summary] (With correction) [Problem] The present invention can prevent damage to a comparator due to high-voltage static electricity generated when attaching or detaching a performance board or a diagnostic board without using a costly surge arrester. Provide a semiconductor test device. SOLUTION: When a performance board is attached / detached, a relay for connecting a signal line and a terminating resistor can be controlled to be turned on.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a semiconductor test apparatus for preventing high-voltage static electricity generated in a signal line when a performance board or the like of a test head is attached or detached.

[0002]

[Prior art]

 An example of the related art will be described with reference to FIGS. First, an outline of the semiconductor test apparatus will be described. As shown in FIG. 4, the configuration of the semiconductor test apparatus includes a workstation 10, a semiconductor test apparatus main body 20, and a test head 30.

The workstation 10 serves as an interface between a semiconductor test apparatus and an operator, and performs calibration and execution of a test program.

The semiconductor test apparatus main body 20 includes a unit for generating a test signal, a unit for receiving a signal from a DUT 31 which is a device under test (DUT: Device Under Test) to make a pass / fail judgment, a control processor, and a power supply. And so on.

The test head 30 exchanges a test signal with a DUT 31 mounted on an IC socket 32 via a performance board 33. However, there is a case where the test head includes the performance board 33 on which the IC socket 32 is mounted, but in this specification, it is separated for convenience of explanation. Further, the mechanical elements of the test head 30 are omitted because they are not directly related to the invention. Although not shown in FIG. 4, when performing the calibration, the performance board 33 is replaced with a diagnostic board.

Next, details of the test head 30 will be described with reference to FIG. As shown in FIG. 5, the test head 30 includes a connecting means 34 and pin electronics 35.

The pin electronics 35 is a measurement circuit corresponding to each pin of the DUT 31. For example, in the case of a semiconductor test apparatus that measures 64 DUTs 31 simultaneously, the pin electronics 35 corresponding to 10000 pins is required. However, for the sake of simplicity, FIG. 5 shows only one set of pin electronics 35.

[0008] The connection means 34 is means for making the performance board 33 detachable from the test head 30. For example, the connection and reception of signals is performed using each pad of the performance board 33 and pogo pins P1 and P2 pressed by spring pressure. I do.

The performance board 33 is a multilayer board having a side of about 50 cm, and has an IC socket 32 corresponding to the DUT 31 mounted thereon.

The IC socket 32 is a socket that matches the number of pins and the shape of the DUT 31 to be tested.

The DUT 31 is a device to be tested by a semiconductor test device, and is mounted on an IC socket 32 and tested.

Next, a configuration example and operation of the main part of the pin electronics 35 will be described. As shown in FIG. 5, an example of a main part of the pin electronics 35 includes relays S11, S12, S21, S22, S31, S32, S41, S42, a driver 51, comparators 61 and 62, and surge arresters 71 and 72. , Resistors R1 and R2.

As shown in FIG. 7, the relays S11, S21, S31, and S41 are controlled by driving the coils of the respective relays with transistors Q1, Q2, Q3, and Q4. The control of the relays S12, S22, S32, and S42 is performed in the same manner as in FIG. 7, and the circuit diagram is omitted.

Here, the relays S11, S12, S21, S22, S31, S32, S41, and S42 are all OFF (break) in a default state, and are independent by a command signal for controlling each relay. And turn on (make). For example, the command signals for turning on the relays S11, S21, S31, and S41 are DR OUT, DR DC, DR CAL, and DR TERM, respectively.

The relays S 11 and S 12 are turned on by a command signal when a logic signal is applied to an I / O pin of the DUT 31 or a logic signal is received from an output pin of the DUT 31.

The relays S 21 and S 22 are turned on by a command signal when applying or measuring a direct current (DC) test signal of an I / O pin or an output pin of the DUT 31.

The relays S 31 and S 32 are turned on by a command signal when performing calibration for matching the test timing of each pin electronics 35.

When applying a logic signal to the I / O pin of the DUT 31 or receiving a logic signal from the output pin of the DUT 31, the relay S41 is turned on by a command signal and terminates the signal by the resistor R1. When receiving the logic signal from the output pin of the DUT 31, the relay S42 is turned on by the command signal, and terminates the signal on the signal line by the resistor R2.

The driver 51 amplifies a test signal applied to the DUT 31 to a predetermined voltage and outputs the amplified signal.

The comparators 61 and 62 compare the voltage of the output signal of the DUT 31 with a high-level comparison voltage or a low-level comparison voltage.

The surge arresters 71 and 72 are elements that absorb high-voltage static electricity on signal lines.

The resistors R1 and R2 are terminating resistors and adjust the resistance value to the characteristic impedance of the signal line.

Next, an outline of an example of a test procedure of the semiconductor test apparatus will be described in the following paragraphs. (1) A diagnostic board is mounted on the test head 30 of the semiconductor test apparatus and calibration is performed. After the calibration is completed, the diagnostic board is detached from the test head 30 and removed.

(2) A performance board 33 corresponding to the DUT 31 to be tested is mounted on the test head 30.

(3) The DUT 31 to be tested is mounted on the IC socket 32 of the performance board 33.

(4) The test program is executed to test the DUT 31 and make a pass / fail decision.

(5) The DUT 31 that has been determined to be acceptable is removed from the IC socket 32 of the performance board 33.

(6) Further, when testing the same type of DUT 31 continuously, the operation is repeated by returning to the step (3).

(7) Next, when testing another type of DUT 31, as shown in FIG. 6, the currently mounted performance board 33 is detached, and the DUT 31 corresponding to the DUT 31 to be tested next is removed. The mounted performance board 33 is mounted on the test head 30.

(8) Then, the operations of (3) to (5) are repeated.

As can be seen from the above test procedure, when testing the DUT 31, it is necessary to attach and detach a diagnostic board and a performance board 33. For example, a problem in the past when the performance board 33 is attached and detached will be described.

When the performance board 33 is attached or detached, high-voltage static electricity of several kV is generated in the performance board 33, and the static electricity is applied to the comparators 61 and 62 of the pin electronics 35 via the gaps of the relays S 11 and S 12 which are turned off. It could be damaged by high voltage static electricity.

Therefore, as a conventional countermeasure against static electricity, in the pin electronics 35, the surge arresters 71 and 72 are inserted into the signal lines on the connection means 34 side of the relays S11 and S12 to attach and detach the performance board 33. The static electricity of the voltage is absorbed to prevent the comparators 61 and 62 from being damaged. However, the conventional pin electronics 35 increases the number of surge arresters 71 and 72 required in response to the increase in the number of pins of the DUT 31 to be tested, and the unit price is high. A similar problem may occur when a diagnostic board is attached or detached.

[0034]

[Problems to be solved by the invention]

 As described above, conventional pin electronics add surge arresters as a countermeasure against static electricity that occurs when a performance board or diagnostic board is attached or detached. There was a problem. Therefore, the present invention has been made in view of these problems, and its purpose is to use a high-cost surge arrester to prevent damage to the comparator due to high-voltage static electricity generated when attaching or detaching a performance board or a diagnostic board. It is an object of the present invention to provide a semiconductor test apparatus which can be performed without performing the above.

[0035]

[Means for Solving the Problems]

 That is, the present invention has been made to achieve the above object. According to the present invention, when a performance board is attached or detached, it is possible to control a relay for connecting a signal line and a terminating resistor to an ON state. .

[0036]

[Embodiment of the invention]

 Embodiments of the present invention will be described in the following examples.

[0037]

【Example】

 An embodiment of the present invention will be described with reference to FIGS. The outline of the semiconductor test apparatus has been described in the prior art and will not be described.

Next, the test head 30 will be described with reference to FIG. The test head 30 includes connection means 34 and pin electronics 36. Also, the connection means 34 has been described in the prior art, and will not be described.

Next, an example of a configuration of a main part of the pin electronics 36 will be described. As shown in FIG. 1, an example of a main part of the pin electronics 36 includes relays S11, S12, S21, S22, S31, S32, S41, S42, a driver 51, comparators 61 and 62, and resistors R1 and R2. Make up. That is, the configuration of the pin electronics 36 is such that the surge arresters 71 and 72 are deleted from the conventional pin electronics 35.

Next, a relay control circuit will be described. Then, as shown in FIG. 3, the control of the relays S11, S21, S31 is performed by driving the coils of the respective relays with transistors Q1, Q2, Q3. The relays S11, S12, S21, S22, S31, and S32 are OFF (break) in the default state, and are turned ON (make) independently by a command for controlling each relay. For example, command signals for turning on the relays S11, S21, and S31 are DR OUT, DR DC, and DR CAL, respectively.

On the other hand, the control of the relay S 41 is such that the control signals of the relays S 31, S 21 and S 31 are received by the NOR gate 80, and the output of the NOR gate 80 and the signal of the command signal DR TER RM are received by the OR gate 90. Therefore, the transistor Q4 is driven. Therefore, the relay S41 is ON in the default state and in the state in which the program is not executed, and is turned OFF by executing the program and giving any of the command signals DR OUT, DR DC, and DR CAL. Become. Alternatively, the program can be executed and turned on independently by the command signal DR TERM.

The control of the relays S12, S22, S32, and S42 can be performed in the same manner as in FIG. 3, so that the circuit diagram and the operation description of the relay S42 are omitted.

Here, when the performance board or the diagnostic board is replaced, the default state or the state where the program is not executed, and the relay 41 and the relay 42 are always on.

Next, an operation for attaching and detaching a diagnostic board will be described. For example, when the diagnostic board is mounted for calibration, the relay S41 and the relay S42 are in the ON state, so that the high-voltage static electricity generated on the diagnostic board is turned off by the pogo pins P1 and P2. Since the relays 41 and 42 are ON through the gaps between the relays S11 and S12, they are absorbed by the terminating resistors R1 and R2, respectively. When the calibration is started, when the relay S31 connecting the calibration loop is turned on, the relay S41 is turned off, and when the relay S32 is turned on, the relay S42 is turned off.

When the calibration is completed, when the relay S32 connecting the calibration loop is turned off, the relay S41 is turned on, and when the relay S32 is turned off, the relay S42 is turned on.

Next, an operation for attaching and detaching the performance board 33 will be described. As shown in FIG. 1, when the performance board 33 is worn to test the DUT 31, the relay S41 and the relay S42 are in the ON state, so that the high-voltage static electricity generated on the performance board 33 is low. The pogo pins P1 and P2 of the connection means 34 and the gaps between the relays S11 and S41 are absorbed by the terminating resistors R1 and R2, respectively. Then, when the DUT 31 is tested by executing the program, the relays S41 and S42 can be turned off by any of the command signals DROUT, DRDC, and DRCAL, and turned on by the command signal DRTERM.

As shown in FIG. 2, when the test of the DUT 31 is completed and the performance board 33 is detached and attached, the relays S41 and S42 are in the ON state as in the case of wearing. The high-voltage static electricity generated on the performance board 33 is absorbed by the terminating resistors R1 and R2 via the pogo pins P1 and P2 of the connecting means 34 and the gap between the relays S11 and S41.

Therefore, the high-voltage static electricity generated when the performance board or the diagnostic board is replaced is transferred to the relays 41 and 42 via the pogo pins P1 and P2 of the connecting means 34 and the gaps of the relays S11 and S12. Since it is ON, it is absorbed by the terminating resistors R1 and R2 and does not damage the comparators 61 and 62.

[0049]

[Effect of the invention]

 The present invention is embodied in the form described above and has the following effects. That is, the high-voltage static electricity generated when the performance board or the diagnostic board is attached or detached can be absorbed by the terminating resistors R1 and R2, and the cost can be reduced since a costly surge arrestor does not need to be used. There is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram in which a performance board is mounted on a test head of a semiconductor test apparatus of the present invention.

FIG. 2 is a circuit diagram of the semiconductor test apparatus of the present invention in which a performance board is detached from a test head.

FIG. 3 is a control circuit diagram of the relay of the semiconductor test device of the present invention.

FIG. 4 is a configuration diagram of a semiconductor test apparatus.

FIG. 5 is a circuit diagram in which a performance board is mounted on a test head of a conventional semiconductor test apparatus.

FIG. 6 is a circuit diagram in which a performance board is detached from a test head of a conventional semiconductor test apparatus.

FIG. 7 is a control circuit diagram of a relay of a conventional semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Workstation 20 Semiconductor test apparatus main body 30 Test head 31 DUT 32 IC socket 33 Performance board 34 Connection means 35, 36 pin electronics 51 Driver 61, 62 Comparator 71, 72 Surge arrester

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[Procedure amendment]

[Submission date] January 21, 2000 (2000.1.2
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims for utility model registration

[Correction method] Change

[Correction contents]

[Utility model registration claims]

Claims (1)

[Contents of amendment] [Rules for registering utility models] 1. A semiconductor test apparatus capable of controlling a relay for connecting a signal line and a terminating resistor to an ON state when a performance board is attached or detached.