JP2007171019A - Electronic circuit and connection diagnostic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit and a connection diagnostic circuit capable of easily specifying the site of failure cause, without having to provide additional wirings. <P>SOLUTION: An electronic circuit comprises a first integrated circuit 12 and second integrated circuits 13 to 17, which are connected by wiring 18 to each other. The first integrated circuit 12 includes a diagnosis signal transmitting section 123 for outputting a predetermined connection diagnostic signal to the wiring 18. The second integrated circuits 13 to 17, respectively includes a signal receiving section 124 corresponding to the connection diagnostic signal supplied via the wiring 18, a signal determining section 125 for determining connection status, denoting whether the connection diagnostic signal received by the signal receiving section 124 has been correctly transmitted, and a determination result holding section 126 for holding the determination result determined by the signal determining section 125. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic circuit including an integrated circuit and a connection diagnosis circuit mounted on the integrated circuit.

  As a method of confirming whether or not the function of a circuit board having a plurality of integrated circuits is normal, diagnostic software is executed before starting the original function of the circuit board, and the function of the electronic circuit as hardware is diagnosed. It is widely done. Such a diagnostic software facilitates repair of an electronic circuit by showing detailed information of the failure when a minor failure that does not become an obstacle to software execution occurs. However, if the failure is serious due to, for example, disconnection of the system bus on the circuit board or malfunction of the bus interface circuit, the diagnostic software does not operate normally. In this case, although the occurrence of a failure is detected because the diagnostic software does not operate normally, the site causing the failure is not specified, and information necessary for repair or replacement of parts cannot be obtained.

Conventionally, as means for avoiding this problem, Patent Documents 1 and 2 are provided with another signal line different from the signal line necessary for the original operation, and a signal for inspection via this other signal line. A technique for inspecting the operation of each component by transmitting and receiving the information is disclosed. Patent Document 3 discloses a technology in which a plurality of modules confirm the soundness of a device by notifying the initialization state on a communication line. Patent Document 4 discloses a technique for re-initializing the entire apparatus by turning on the power again as a recovery process when a failure occurs.
Japanese Patent Application Laid-Open No. 07-087161 Japanese Patent Laid-Open No. 09-274067 Japanese Patent Laid-Open No. 07-236182 JP 2003-256240 A

  However, as in the technique shown in Patent Document 1 or 2, when a signal line different from the signal line necessary for the original operation is laid for fault diagnosis, the pin of the package that houses the integrated circuit The number of wires and the number of wires on the circuit board increase, and the manufacturing cost increases. The increase in the number of wirings causes an increase in the wiring layer of the circuit board. In addition, since the technique of Patent Document 3 determines that all of a plurality of modules have started normally, it cannot specify which module does not start normally. Further, the technique of Patent Document 4 is to turn off the power supply of the entire apparatus in the case of malfunction, and does not correspond to individual integrated circuits.

  In view of the above circumstances, an object of the present invention is to provide an electronic circuit and a connection diagnosis circuit that can easily specify a site causing a failure without adding wiring.

An electronic circuit of the present invention that achieves the above object is an electronic circuit including a first integrated circuit and a second integrated circuit connected to each other by wiring,
The first integrated circuit includes a diagnostic signal transmission unit that outputs a predetermined connection diagnostic signal to the wiring.
The second integrated circuit is
A signal receiving unit for receiving a signal corresponding to the connection diagnosis signal, which has been supplied via the wiring;
A signal determination unit for performing a connection pass / fail determination indicating whether or not the signal received by the signal reception unit is a signal in which the connection diagnosis signal has been accurately transmitted;
And a determination result holding unit for holding a determination result by the signal determination unit.

  According to the electronic circuit of the present invention, the first integrated circuit outputs a connection diagnosis signal to the wiring, and the second integrated circuit accurately transmits the signal received via the wiring. Therefore, a special signal line for diagnosis is not required. Further, by reading the held determination result, it is possible to easily determine whether or not the wiring is connected between the first integrated circuit and the second integrated circuit. Therefore, when a failure occurs, it is possible to easily specify whether the part causing the failure is a wiring or the integrated circuit itself.

Here, in the electronic circuit of the present invention, the first integrated circuit and the second integrated circuit receive a reset signal input from the outside and perform an initialization operation.
The first integrated circuit preferably transmits the connection diagnosis signal following the initialization operation.

  In the electronic circuit of the present invention, it is preferable that the second integrated circuit performs the connection quality determination based on a signal received within a predetermined time following the initialization operation.

  The first integrated circuit transmits a connection diagnosis signal following the initialization operation performed in response to the reset signal, and the second integrated circuit is based on a signal received within a predetermined time following the initialization operation. By determining whether or not the connection is good, it is possible to make a diagnosis by transmitting and receiving a connection diagnosis signal without hindering transmission and reception of signals for the original function of each integrated circuit.

The connection diagnosis circuit of the present invention that achieves the above object is a connection diagnosis circuit mounted on each of at least two integrated circuits among a plurality of integrated circuits connected to each other by wiring,
A diagnostic signal transmitter for outputting a predetermined connection diagnostic signal to the wiring;
A signal receiving unit for receiving a signal corresponding to the connection diagnosis signal, which has been supplied via the wiring;
A signal determination unit for performing a connection pass / fail determination indicating whether or not the signal received by the signal reception unit is a signal in which the connection diagnosis signal has been accurately transmitted;
A determination result holding unit for holding a determination result by the signal determination unit;
In accordance with a setting signal supplied from the outside, the diagnostic signal transmitting unit and the signal receiving unit are switched to operate.

  Since the connection diagnosis circuit of the present invention includes all of the diagnosis signal transmission unit, the signal reception unit, the signal determination unit, and the determination result holding unit, when the connection diagnosis circuit is mounted on each of the plurality of integrated circuits, In the electric circuit having the integrated circuit, one of the integrated circuits is operated as the first integrated circuit according to the above-described electronic circuit invention by the setting signal, and the other integrated circuit is operated as the second integrated circuit. Is possible. Therefore, it is possible to easily specify the site of the cause of failure without increasing the wiring for diagnosis in the electronic circuit. Furthermore, at the design stage of the electronic circuit, an integrated circuit corresponding to the required function is selected from a plurality of integrated circuits equipped with the connection diagnosis circuit, and the settings are made for connection diagnosis at the final stage of the design. It is possible to design an electronic circuit that can easily identify the cause site. Therefore, the degree of freedom of combination of integrated circuits at the design stage is high.

  It should be noted that the connection diagnosis circuit according to the present invention is only shown in its basic form here, but this is only for avoiding duplication, and the connection diagnosis circuit according to the present invention has the above basic form. In addition, various forms corresponding to each form of the electronic circuit described above are included.

  As described above, according to the present invention, it is possible to realize an electronic circuit and a connection diagnosis circuit that can easily determine whether or not a connection is good without increasing the number of wires.

  Embodiments of an electronic circuit according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an electronic circuit according to an embodiment of the present invention.

  The electronic circuit 10 of this embodiment is formed on a circuit board 11 installed in an electronic device, and includes a plurality of LSIs 12, 13, 14, 15, 16, and 17. These LSIs 12 to 17 are connected to each other by a communication bus 18 formed of printed wiring, connectors, wires, and sockets formed on the circuit board 11. The communication bus 18 includes a plurality of address buses, data buses, and control signal lines (not shown). In the electronic circuit 10, the LSI 12 normally operates as a microcontroller that is an original function, and transmits an address signal to the other LSIs 12 to 17 via the address bus. A unique address is assigned to each of the LSIs 13 to 17, and the LSI corresponding to the address signal sent via the address bus among the LSIs 12 to 17 is sent from the LSI 12 via the control signal line. Depending on the signal, the data signal sent via the data bus is taken in, or the data signal is output to the LSI 12 via the data bus. As a result, the LSI 12 writes and reads information necessary for operating the electronic device to the LSIs 13 to 17 via the communication bus 18. Each of the LSIs 12 to 17 corresponds to an example of an integrated circuit according to the present invention. The LSI 12 corresponds to an example of a first integrated circuit referred to in the electronic circuit of the present invention, and each of the LSIs 13 to 17 corresponds to an example of a second integrated circuit referred to in the electronic circuit of the present invention.

  The electronic circuit 10 is also provided with a reset circuit 19. The reset circuit 19 supplies a reset signal to the LSIs 12 to 17 immediately after the power is supplied to the electronic circuit 10 or according to a user operation, thereby setting the LSIs 12 to 17 in an initial state. When the reset circuit 19 stops supplying the reset signal, each of the LSIs 12 to 17 performs internal initialization.

  FIG. 2 is a block diagram showing the configuration of the LSI 12.

  The LSI 12 includes a main function circuit 120, an input / output buffer 121, and a startup diagnostic circuit 122.

  The main function circuit 120 is a circuit that executes an original function of the LSI 12. For example, the main function circuit 120 in the LSI 12 executes a function of a microcontroller, and although not shown, a central processing unit (CPU) that controls the operation of the entire electronic circuit 10 based on a program, a program, It includes a ROM that stores a table, a RAM that provides a temporary storage area for the CPU, and an interface circuit that relays signals. The operation of the LSI 12 as a microcontroller is controlled based on a program executed by the CPU, and the program includes a program corresponding to a defect detection process and a fault location specifying process described later.

  The input / output buffer 121 outputs the signal output from the main function circuit 120 toward the communication bus 18 or outputs the signal transmitted via the communication bus 18 to the main function circuit 120. During a predetermined time after the supply of the signal is stopped, a signal from the start-up diagnosis circuit 122 is output to the communication bus 18 or a signal sent via the communication bus 18 is supplied to the start-up diagnosis circuit 122. .

  One startup diagnosis circuit 122 is provided for each of the wirings constituting the communication bus 18, but FIG. 2 shows one of the plurality of startup diagnosis circuits 122 corresponding to one wiring. Only the startup diagnostic circuit 122a is shown.

  The startup diagnosis circuit 122a includes a transmission circuit 123, a reception circuit 124, a comparison circuit 125, a holding circuit 126, and a selection circuit 127. These circuits are constituted by a sequencer.

  After the reset signal supply is stopped and the internal initialization time Ti of the LSI 12 has elapsed, the transmission circuit 123 generates a startup diagnosis pulse having a predetermined pulse waveform, and the communication bus 18 via the input / output buffer 121. Output to. The activation diagnosis pulse is an example of the connection diagnosis signal referred to in the present invention.

  The receiving circuit 124 receives a signal transmitted via the input / output buffer 121 of the communication bus 18 after the reset signal supply is stopped and the internal initialization time Ti of the LSI 12 has elapsed.

  The comparison circuit 125 compares the signal received by the reception circuit 124 with a predetermined pulse waveform to determine whether or not the received signal is a signal that has been accurately transmitted from the communication bus 18. The connection pass / fail judgment is determined.

  The holding circuit 126 has a diagnostic register for holding the diagnostic result, and holds the determination result by the comparison circuit 125 in the diagnostic register. The holding circuit 126 is configured such that the determination result held in the diagnostic register can be read later via the communication bus 18.

  The selection circuit 127 switches between the transmission circuit 123 and the reception circuit 124 in accordance with a setting signal supplied from an external setting pin. Thus, in the master mode in which the startup diagnostic circuit 122 of the LSI 12 outputs the startup diagnostic pulse by the setting signal supplied to the external setting pin, or in the slave mode in which the startup diagnostic pulse is received and the connection quality is determined. Set to either. Specifically, when the setting pin is set to the H level, the selection circuit 127 outputs a transmission mode signal to the transmission circuit 123, and the startup diagnostic circuit 122 of the LSI 12 outputs a startup diagnostic pulse. Become. On the other hand, when the setting pin is set to L level, the selection circuit 127 outputs a reception mode signal to the reception circuit 124, and the startup diagnostic circuit 122 of the LSI 12 enters a slave mode in which the startup diagnostic pulse is received. Regardless of the input / output direction of the signal to / from the communication bus 18 of the input / output buffer 121, the predetermined time after the stop of the supply of the reset signal is a mode corresponding to the level of the set signal regardless of the input / output direction as the original function of the LSI 12. Determined by.

  The transmission circuit 123, the reception circuit 124, the comparison circuit 125, the holding circuit 126, and the selection circuit 127 are examples of a diagnostic signal transmission unit, a signal reception unit, a signal determination unit, a determination result holding unit, and a switching unit according to the present invention, respectively. It corresponds to. Although the configuration of the LSI 12 is shown in FIG. 2, the configurations of the other LSIs 13 to 17 are the same except for the function and configuration of the main functional circuit, and thus the same reference numerals are given, and illustration and description are omitted.

  Returning to FIG. 1, the description will be continued.

  In the electronic circuit 10 of this embodiment, the LSI 12 is set to the master mode, and the LSIs 13 to 17 are set to the slave mode. That is, the startup diagnostic circuit 122 included in the LSI 12 outputs a startup diagnostic pulse following the initialization operation performed in response to the reset signal, while the startup diagnostic circuit 122 included in the LSIs 13 to 17 performs the initialization operation. It is set to perform the above-mentioned connection pass / fail judgment based on a signal received within a predetermined time after that.

  Here, in each of the LSIs 12 to 17, only one of the transmission circuit 123 and the reception circuit 124 operates, but the startup diagnosis circuit 122 includes the transmission circuit 123, the reception circuit 124, and the comparison circuit 125. And holding circuit 126 are all provided. Thereby, in the design stage of the electronic circuit, a plurality of LSIs including the startup diagnosis circuit 122 are selected and combined based on functions required for the electronic circuit, and the plurality of LSIs combined in the final design stage By setting any one of them to the master mode by the setting signal, it is possible to configure the wiring connection failure to be diagnosed. Therefore, there is a high degree of freedom in combining LSIs in designing electronic circuits.

  Next, operations of the LSI 12 set to the master mode and the LSIs 13 to 17 set to the slave mode will be described.

  FIG. 3 is a flowchart showing the operation of the startup diagnostic circuit provided in the LSI set in the master mode, and FIG. 4 shows the operation of the startup diagnostic circuit provided in the LSI set in the slave mode. It is a flowchart. FIG. 5 is a timing chart showing the bus signal and the reset signal.

  As shown in FIG. 3, the LSI 12 starts the activation diagnosis when the reset signal is canceled. As shown in the timing chart of FIG. 5, the reset signal is at the H level (positive logic). When the supply of the reset signal is stopped and the reset is released (step S11: Yes), the startup diagnostic circuit 122 and the main function circuit 120 perform internal initialization (step S12). Next, when the internal initialization time Ti for internal initialization elapses from the reset release timing Tres (see FIG. 5) (step S13: Yes), the transmission circuit 123 indicates the start diagnosis time Td in FIG. A waveform activation diagnosis pulse is transmitted to the communication bus 18 (step S14). As a result, the LSI 12 transmits a connection diagnosis signal following the initialization operation performed in response to the reset signal.

  The activation diagnosis pulse output from the transmission circuit 123 toward the communication bus 18 is transmitted toward the LSIs 13 to 17 connected via the communication bus 18. However, if the wiring pattern or wire constituting the communication bus 18 is disconnected, or if the contact between the LSIs 12 to 17 and the socket is poor or the soldering is defective, the activation diagnosis pulse does not reach the LSIs 12 to 17. .

  Next, the transmission circuit 123 inactivates a bus signal to be transmitted to the communication bus 18 (step S15). As a result, the communication bus 18 is in a high impedance state as shown in FIG. 5 until initialization by software is performed (step S16). Thereafter, when the main function circuit 120 starts to operate as a microcomputer that is an original function of the LSI 12 and initialization by software is executed, the communication bus 18 becomes active as shown in FIG.

  Here, with reference to FIG. 4, the operation of the LSIs 13 to 17 set to the slave mode will be described.

  The LSIs 13 to 17 start the activation diagnosis when the reset signal is released. When the supply of the reset signal is stopped and the reset is released (step S21: Yes), the LSIs 13 to 17 have passed the internal initialization time Ti of the internal initialization from the reset release timing Tres (see FIG. 5). (Step S22). Here, since the internal initialization time Ti is set in common in all the LSIs 12 to 17, the transmission timing and the reception timing of the activation diagnosis pulse in each of the LSIs 12 to 17 that receive the same reset signal are mutually different. Synchronize. After the internal initialization time Ti elapses, the receiving circuit 124 starts receiving signals transmitted via the communication bus 18. Next, when the activation diagnosis time Td elapses (step S23: Yes) or when the reception circuit 124 receives a signal (step S24: Yes), the comparison circuit 125 activates the waveform of the signal received by the reception circuit 124. By comparing the waveforms of the diagnostic pulses, it is determined whether or not the received signal is a signal that has been accurately transmitted from the transmission circuit 123 of the LSI 12 (steps S25 and S26). As a result of the comparison by the comparison circuit 125, when it is determined that the activation diagnosis pulse has been transmitted correctly, the holding circuit 126 holds a value indicating good connection in the diagnosis register (step S28). On the other hand, when the received signal is different from the activation diagnostic pulse, including the case where no signal is received, the holding circuit 126 holds a value indicating a connection failure in the diagnostic register (step S27). Then, the startup diagnosis operation ends.

  In this way, the LSI 12 functioning as a master outputs a connection diagnosis signal to the communication bus 18, and signals received by the LSIs 13 to 17 functioning as slaves via the communication bus 18 are accurately transmitted. Since the determination result is retained and the determination result is retained, whether or not the communication bus 18 is connected between the LSI 12 and the LSIs 13 to 17 is easily determined when the retained determination result is read. . For example, after the above-described startup diagnosis, the LSI 12 operates as a microcontroller that is an original function, and the data held in the diagnosis register of the holding circuit 126 provided in each of the LSIs 13 to 17 can be read via the communication bus 18. For example, it is possible to determine whether or not any of the wirings of the LSI 12 and the LSIs 13 to 17 is defective. Therefore, when a failure occurs in the electronic circuit 10, it is easily specified whether the failure cause is the communication bus 18 or the LSIs 12 to 17 themselves. Moreover, it is not necessary to add wiring for diagnosis.

  Further, according to the electronic circuit 10 of the present embodiment, the LSI 12 transmits a connection diagnosis signal subsequent to the initialization operation performed in response to the reset signal, and the LSIs 13 to 17 start-up diagnosis time subsequent to the initialization operation. By making a connection pass / fail judgment based on the signal received at Td, before starting transmission / reception, diagnosis is performed without interrupting transmission / reception of signals of the original functions of the LSIs 12-17. be able to.

  FIG. 6 is a flowchart showing a defect detection process executed by the LSI, and FIG. 7 is a flowchart showing a fault location specifying process executed by the LSI.

  The defect detection process and the fault site identification process shown in FIGS. 6 and 7 are a part of the processes executed by the LSI 12 as a microcontroller that is the original function. When the startup diagnosis is completed and the operation of the LSI 12 is started as a microcontroller, the LSI 12 executes a failure location specifying process following the defect detection process.

  In the defect detection process, first, the LSI 12 performs initialization (step S31). Here, the LSI 12 initializes the LSI 12 such as a RAM and writes data to the LSIs 13 to 17 via the communication bus 18 to initialize the LSIs 13 to 17.

  Next, the LSI 12 sequentially reads the registers for each of the m LSIs in the slave mode. In the electronic circuit 10 of the present embodiment, the number of LSIs in the slave mode is five. The LSIs 13 to 17 are referred to as LSI-1 to LSI-5, respectively. First, the LSI 12 initializes the value of the count n representing the number of LSIs in the slave mode to 0 (step S32), then adds 1 to the count n (step S33), and the nth LSI-n The value of the diagnostic register included in the holding circuit 126 (FIG. 2) is read (step S34). Here, when the read cycle in the reading process is not normally completed (step S35: No), the LSI 12 determines that the connection from the LSI 12 to the LSI-n or the operation failure of the LSI-n itself (step S35). S36), the value Error1, which means a connection failure or an operation failure of the LSI-n itself, is recorded in an area corresponding to the LSI-n in the activation diagnosis result log arranged in the RAM (step S37). On the other hand, when the read cycle in the reading process is normally completed (step S35: Yes), the LSI 12 determines whether or not the read value of the diagnostic register is a value meaning good connection (step S38). If the value of the diagnosis register means a connection failure (step S38: No), it is determined that the connection from the LSI 12 to the LSI-n is a failure (step S39), and the value Error2 indicating the connection failure is determined as a start diagnosis. It records in the area | region applicable to LSI-n of a result log (step S40).

  After the processes of steps S37, S40, and S38 described above, the LSI 12 determines whether or not the LSI-n that has read from the diagnostic register is the last LSI-m among the LSIs 13 to 17 to be read. If it is determined that the LSI is not the last LSI-m, the processing from step S33 is repeated (step S41: No), and reading from all the diagnostic registers of the LSIs 13 to 17 and determination are sequentially performed to detect defects. Exit.

  Thus, according to the electronic circuit 10 of the present embodiment, the value of the determination result held in the diagnostic register can be read between the LSI 12 and the LSIs 13 to 17 without adding wiring for diagnosis. It is possible to determine whether or not the wiring connection is defective. Furthermore, according to the electronic circuit 10, there are a plurality of LSIs 13 to 17 in the slave mode, and it is possible to easily determine which of these LSIs has a poor connection. That is, when a failure occurs, it is possible to easily identify whether the failure cause is the connector or cable connecting the LSIs 13 to 17 or the LSIs 13 to 17 themselves. If the part causing the failure is easily identified, it is possible to replace only the part at the failure part in a short time in repairing the failure. For example, even in the case of a failure of an electronic circuit in a device such as a copier or a printer that does not allow a long time to be repaired with its original function stopped, repair is performed by avoiding the situation of replacing the entire circuit board. Cost can be reduced.

  Subsequently, a failure part specifying process executed for specifying a failure part based on the value recorded in the activation diagnosis result log in the defect detection process will be described.

  First, the LSI 12 initializes the value of the count n indicating the number of LSIs in the slave mode to 0 (step S51). Subsequently, the LSI 12 adds 1 to the count n (step S52), and reads a value from the area corresponding to the LSI-n in the activation diagnosis result log arranged in the RAM (step S53). When the value read in step S53 is the value Error1 meaning a connection failure or an operation failure of the LSI-n itself (step S54: Yes), the LSI 12 has a connection failure from the LSI 12 to the LSI-n or the LSI-n itself. It is determined that this is a malfunction (step S55). On the other hand, if the value read in step S53 is the value Error2 meaning a connection failure from the LSI 12 to the LSI-n (step S56: Yes), the LSI 12 determines that there is a connection failure from the LSI 12 to the LSI-n. (Step S57).

  The LSI 12 determines that the LSI-n corresponding to the area read from the activation diagnosis result log is the last LSI-m among the LSIs 13 to 17 to be read (step S58: Yes) until step S52. To S57 are repeated.

  Next, the LSI 12 discards the determination results in step S55 and step S57 when the value read from the activation diagnosis result log is the value Error2, which means a connection failure, for all the slave mode LSIs 13 to 17. Thus, it is determined that the master mode LSI, that is, the LSI 12 itself is in failure (step S60), and the process of specifying the failed part is terminated. On the other hand, if the values of all the slave mode LSIs 13 to 17 do not mean connection failure (step S59: No), the determination results in step S55 and step S57 are valid.

  In this way, when there are a plurality of slave mode LSIs, it is possible to determine which LSI, including the master mode LSI, is defective in connection.

  In the present embodiment, all the LSIs 12 to 17 included in the electronic circuit 10 have been described as including the startup diagnostic circuit 122, but the electronic circuit and startup diagnostic circuit of the present invention are not limited thereto. The electronic circuit of the present invention may include an integrated circuit that does not include any of a transmission circuit, a reception circuit, a comparison circuit, and a holding circuit. In addition, the startup diagnostic circuit of the present invention only needs to be mounted on at least two integrated circuits. However, when all the integrated circuits are provided with the startup diagnostic circuit, it is possible to easily determine whether or not all the integrated circuits are connected.

  In this embodiment, the slave mode LSIs 13 to 17 are described as being plural, but the present invention is not limited to this. The electronic circuit of the present invention only needs to include one integrated circuit that operates in the master mode and at least one integrated circuit that operates in the slave mode.

  In this embodiment, the original function of the LSI 12 set to the master mode is described as a microcomputer. However, in the present invention, the original function of the first integrated circuit is the master of the communication bus. It is not limited to. For example, the electronic circuit may have a configuration in which a microcomputer connected to a communication bus is provided separately from an LSI operating in the master mode and an LSI operating in the slave mode.

  In the present embodiment, the communication bus 18 is described as being composed of an address bus, a data bus, and the like, but the present invention is not limited to this. The wiring of the present invention may be a wiring for transmitting and receiving a serial communication signal and a video / audio data signal, for example. Further, although the electronic circuit 10 has been described as being formed on the circuit board 11, the present invention is not limited to this, and the electronic circuit of the present invention is formed on a plurality of circuit boards, for example, May be configured to be extended via a connector or a cable.

It is a block diagram which shows the structure of the electronic circuit of one Embodiment of this invention. 2 is a block diagram showing a configuration of an LSI 12. FIG. It is a flowchart which shows operation | movement of the starting time diagnostic circuit with which LSI set to the master mode was equipped. It is a flowchart which shows operation | movement of the starting time diagnostic circuit with which LSI set to the slave mode was equipped. It is a timing chart which shows a bus signal and a reset signal. It is a flowchart which shows the defect detection process which LSI performs. It is a flowchart which shows the failure part specific process which LSI performs.

Explanation of symbols

10 electronic circuit 11 circuit board 12 LSI (first integrated circuit)
13-17 LSI (second integrated circuit)
120 Main function circuit 121 I / O buffer 122 (122a) Start-up diagnostic circuit (connection diagnostic circuit)
123 Transmitter circuit (diagnostic signal transmitter)
124 Receiver circuit (signal receiver)
125 comparison circuit (signal determination unit)
126 holding circuit (determination result holding unit)
127 selection circuit (switching unit)
18 Communication bus (wiring)
19 Reset circuit

Claims (4)

An electronic circuit comprising a first integrated circuit and a second integrated circuit connected to each other by wiring,
The first integrated circuit includes a diagnostic signal transmission unit that outputs a predetermined connection diagnostic signal to the wiring,
The second integrated circuit comprises:
A signal receiving unit for receiving a signal corresponding to the connection diagnosis signal, which has been supplied via the wiring;
A signal determination unit for performing a connection pass / fail determination indicating whether or not the signal received by the signal reception unit is a signal in which the connection diagnosis signal has been accurately transmitted;
An electronic circuit comprising: a determination result holding unit that holds a determination result by the signal determination unit. The first integrated circuit and the second integrated circuit receive a reset signal input from the outside and perform an initialization operation.
2. The electronic circuit according to claim 1, wherein the first integrated circuit transmits the connection diagnosis signal subsequent to the initialization operation.   2. The electronic circuit according to claim 1, wherein the second integrated circuit performs the connection quality determination based on a signal received within a predetermined time following the initialization operation. A connection diagnostic circuit mounted on each of at least two integrated circuits among a plurality of integrated circuits connected by wiring,
A diagnostic signal transmitter for outputting a predetermined connection diagnostic signal to the wiring;
A signal receiving unit for receiving a signal corresponding to the connection diagnosis signal, which has been supplied via the wiring;
A signal determination unit that performs a connection pass / fail determination that indicates whether the signal received by the signal reception unit is a signal that the connection diagnosis signal has been accurately transmitted;
A determination result holding unit for holding a determination result by the signal determination unit;
A connection diagnostic circuit comprising: a switching unit that switches between the diagnostic signal transmission unit and the signal reception unit to operate in accordance with a setting signal supplied from outside.

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