TWI396854B - Test device and socket board - Google Patents

Description

Test device and adapter board

The present invention relates to a test device for a semiconductor component, and more particularly to a timing calibration technique for a pin electronic component.

A test device for testing a semiconductor element (hereinafter also referred to as a DUT) is provided with a plurality of pin electronic components in order to impart a test pattern to the pins of the DUT or read data from the DUT. Each pin electronic component includes a driver for outputting a signal to a pin corresponding to the DUT, and a comparator for determining a level of a signal output from the corresponding pin.

Typically, a single pin of the DUT is assigned to each pin electronic component, i.e., to the driver. Between the corresponding driver and the pin of the DUT, it is connected by wiring having a predetermined characteristic impedance Zo (for example, 50 Ω) laid on the mother board and the mating board. In recent years, in order to reduce the test cost and effectively utilize the hardware resources, a method of shunting a signal from a single driver and supplying it to a plurality of DUTs to increase the number of simultaneous measurements is generally employed.

With the increase in the speed of the DUT represented by the memory element, the test apparatus is required to perform measurement with higher precision. On the other hand, when the number of simultaneous measurements is increased, the impedance mismatch between the driver and the DUT becomes remarkable, and the speed is increased. The obstacle to high precision.

An object of the present invention is to provide a test apparatus formed in view of the above situation, which can measure a plurality of DUTs with high precision.

An aspect of the present invention provides a test apparatus which is a test apparatus for testing N (N is an integer of 2 or more) test elements having at least one input/output terminal. The testing device includes: a driver that is commonly disposed for the input and output terminals of the N tested components; a terminal circuit that is commonly set for the input and output terminals of the N tested components; and a first wiring that outputs the output terminal of the driver and the 1 is connected between the nodes; the second wiring is connected between the terminal circuit and the second node; and the N third wirings are connected to the terminal of the first node and the N elements to be tested. Connected; N fourth wirings that connect the second node and each of the N test elements to the terminal. The first and second wirings have a characteristic impedance of a predetermined value, and each of the N third wirings and the N fourth wirings has a characteristic impedance N times a predetermined value.

According to this aspect, the impedance of the plurality of elements to be tested is observed from the driver, and the impedance of the plurality of elements to be tested is observed from the terminal circuit, and the impedance is matched with the characteristic impedance of the predetermined value. Therefore, impedance matching can be realized with high precision. High precision testing is possible.

The first and second wirings may be laid on the mother board, and the mother board is connected between the semiconductor wafer in which the driver is integrated and the mating board in which the N test elements are directly or indirectly connected. The third and fourth wirings can also be laid on the mating plate.

The terminal circuit can also be placed on the motherboard. In this case, the number of channels (channels) that can be formed on one semiconductor wafer can be increased, and the number of terminals of the semiconductor wafer can be reduced.

The termination circuit can also be mounted on the semiconductor wafer with the driver.

It is also possible to make N=2 and the characteristic impedance is specified to be 50 Ω.

The Nth third wirings may be of equal length. In this case, there is an advantage that it is not necessary to optimize the timing of the test pattern supplied from the driver on each of the plurality of DUTs.

Another aspect of the present invention provides a patching board which is a mating board mounted with N (N is an integer of 2 or more) tested components, wherein the N tested components respectively have at least one input/output terminal . The adapter board includes: a first terminal connected to an output terminal of a driver provided for the input and output terminals of the N tested components in a state where the adapter board is mounted on the motherboard; the second terminal In a state in which the mating board is mounted on the motherboard, the terminal circuit is provided in common with the input and output terminals of the N devices to be tested; N third wirings each of which is the first terminal and the N tested components The input/output terminals are connected; and the N fourth wirings are branched from the second terminal as the starting point to the input/output terminals of the N test elements. Each of the N third wirings and the N fourth wirings has the same characteristic impedance.

According to this aspect, the influence of reflection can be suppressed, and a plurality of components to be tested can be simultaneously measured.

The Nth third wirings may be of equal length.

Further, any combination of the above constituent elements or the constituent elements or expressions of the present invention are mutually replaced by a method, an apparatus, a system, etc., and are also effective as an aspect of the present invention.

According to a certain aspect of the present invention, a plurality of components to be tested can be measured with high precision.

Hereinafter, the present invention will be described with reference to the drawings in accordance with preferred embodiments. The same or equivalent constituent elements, members, and processes shown in the respective drawings are denoted by the same reference numerals, and the overlapping description will be omitted as appropriate. Further, the embodiments are not intended to limit the invention, and all the features described in the embodiments or combinations thereof are not necessarily essential features of the invention or a combination thereof.

In the present specification, the phrase "the state in which the member A is connected to the member B" includes the case where the member A and the member B are physically directly connected, and also includes the member A and the member B via other members that do not affect the electrical connection state. In the case of indirect connections.

Similarly, the phrase "the member C is disposed between the member A and the member B" includes, in addition to the case where the member A and the member C or the member B and the member C are directly connected, including other effects that do not affect the electrical connection state. The case of indirect connections.

FIG. 1 is a block diagram showing a portion of the configuration of the test apparatus 100. The test apparatus 100 includes a pin electronic component 30, a mother board 32, a mating board 34, and other timing generators or pattern generators (not shown). Since the function and configuration of the test apparatus 100 are general functions and configurations, only the parts related to the present invention will be described in detail.

The test apparatus 100 has the function of simultaneously measuring a plurality of N DUTs 110. In the following description, in order to facilitate the understanding and simplification of the description, the case of N=2 will be described, but the present invention is not limited thereto. Multiple DUTs 110 are generally assumed to be the same component (same variety), but may be different. The DUTs 110 each have at least one input/output terminal. Hereinafter, in order to distinguish the members of the respective DUTs, the wording is attached as needed. Further, in order to simplify the description, attention will be paid only to the first input/output terminal P1.

The driver 20 is provided in common for each of the input and output terminals P1 ₁ and P1 _{2 of the} two DUTs 110 ₁ and 110 ₂ . The driver 20 outputs the test pattern in a time-division manner for each of the input/output terminals P1 ₁ and P1 ₂ . When the test pattern is 1, the driver 20 outputs a voltage VIH corresponding to a high level, and when the test pattern is 0, a voltage VIL corresponding to a low level is output. The driver 20 is designed such that its output impedance is consistent with a prescribed characteristic impedance ZO. For example, ZO = 50 Ω. On the output side of the driver 20, a first switch SW1 is provided. The first switch SW1 may be a mechanical switch such as a relay or an electrical switch such as a transfer gate.

The terminal circuit 22 can also be provided in common for the respective input/output terminals P1 ₁ and P1 _{2 of the} two DUTs 110 ₁ and 110 ₂ . The output impedance of the termination circuit 22 is designed to coincide with a prescribed value of ZO = 50 Ω. For example, the termination circuit 22 includes a termination resistor RT and a buffer BUF. The buffer BUF fixes the potential of one end of the terminating resistor RT to a predetermined value VT (for example, the midpoints of VIH and VIL). The other end of the terminating resistor RT is provided with a second switch SW2.

The first wiring L1 connects the output terminal of the driver 20 and the first node N1. The second wiring L2 connects the terminal circuit 22 and the second node N2. The mating plate 34 is detachably formed to the mother board 32, and is connected via the connection pins PC1, PC2. In FIG. 1, the first node N1 corresponds to the connection pin PC1. However, a part of the first wiring L1 may be laid on the adapter plate 34, and the first node N1 may be placed on the adapter plate 34.

The plurality of Nth third lines L3 ₁ and L3 ₂ respectively connect the first node N1 and the two DUTs 110 ₁ and 110 ₂ to the terminals P1 ₁ and P1 ₂ . In other words, the plurality of third lines L3 ₁ and L3 ₂ are formed by branching from the first node N ₁ to the plurality of input/output terminals P1 ₁ and P1 ₂ . The plurality of Nth fourth wirings L4 ₁ and L4 ₂ respectively connect the second node N2 and the two DUTs 110 ₁ and 110 ₂ to the terminals P1 ₁ and P1 ₂ . In other words, the plurality of fourth wirings L4 ₁ and L4 ₂ are formed by branching the plurality of input/output terminals P1 ₁ and P1 ₂ with the connection pin PC2 as a starting point. Further, the second node N2 can coincide with the connection pin PC2.

The above is the connection form of the plurality of DUTs 110, the driver 20, and the terminal circuit 22. In addition, the test apparatus 100 of FIG. 1 has the following features.

Each of the first wiring L1 and the second wiring L2 has a characteristic impedance ZO of a predetermined value of 50 Ω. On the other hand, each of the N third wirings L3 ₁ and L3 ₂ and the N fourth wirings L4 ₁ and L4 ₂ has a characteristic impedance ZO of 100 Ω which is N times (double) of a predetermined value of 50 Ω. The term "N times" as used herein does not mean a strict N times, and may be deviated by N times as long as it does not affect the impedance mismatch in the measurement.

By using the test apparatus 100 of Fig. 1, the impedance matching on the side of the plurality of DUTs 110 can be observed from the terminal circuit 22 to be 50 Ω. Further, both ends of the transmitting end (driver 20) side and the receiving end (110) side are used as terminals, so that the influence of reflection can be suppressed. Therefore, high-precision testing can be achieved.

In a preferred embodiment, the N third wirings L3 ₁ and L3 ₂ are of equal length. As a result, the transmission time of the test pattern outputted from the driver 20 to the input/output terminal P1 ₁ of one 110 ₁ can be made the same as the transmission time of the input/output terminal P1 ₂ of the other 110 ₂ . As a result, in the case of data of the same channel, the DuT 110 can be made to operate at a common timing for the plurality of DUTs 110, so that the timing adjustment function of each DUT is not required on either the DUT 110 side or the test apparatus 100 side.

In addition, the test apparatus 100 has the following features. The test apparatus 100 is divided into a pin electronic component 30, a mother board 32, and a mating board 34. On the mating plate 34, a plurality of DUTs are directly or indirectly mounted. The pin electronic component 30 is a semiconductor wafer in which a driver 20 having a plurality of channels and a termination circuit 22 are integrated. The motherboard 32 connects the pin electronic component 30 and the mating panel 34.

The first wiring L1 and the second wiring L2 are laid on the mother board 32. On the other hand, a part of the third wiring L3, the fourth wiring L4, and the second wiring L2 are laid on the mating plate 34. In other words, the first node N1 and the second node N2 are disposed on the boundary between the mother board 32 and the mating plate 34, or are disposed on the side of the mating plate 34 from the boundary. According to this configuration, even when the pin arrangement of the DUT 110 is changed, only the adapter plate 34 can be designed, and the pin electronic component 30 and the motherboard 32 need not be changed.

The above is the configuration of the test apparatus 10 of the embodiment. The effect of the test apparatus 100 is more apparent by comparison with the comparison technique shown in Figs. 2(a) and (b). The test apparatus 100c of Fig. 2(a) does not have the termination circuit 22. In this configuration, since the third wirings L3 ₁ and L3 ₂ are designed to be 100 Ω, impedance matching can be theoretically obtained, and therefore, it is not affected by reflection. However, since the DUT side is open in reality, if the characteristic impedances of the _two third wirings L3 ₁ and L3 ₂ are slightly different, the data transmission is easily affected by the reflected waves. In particular, when the input capacities of the DUTs 110 ₁ and 110 _{2 are} different, or when the balance is broken in a state where a certain DUT is removed, the influence of the reflected waves is increased.

The test apparatus 100d of Fig. 2(b) has a wiring L5 that connects the outputs of the DUTs 100 ₁ and 100 ₂ to the terminals P1 ₁ and P1 ₂ . In the configuration of Fig. 2(b), both the end side and the receiving end side form a terminal, and there is no branch path, so that it is difficult to be affected by reflection. However, since the time from when the test pattern outputted from the driver 20 reaches the output of the DUTs 110 ₁ and 110 ₂ to the terminals P1 ₁ and P1 ₂ is different, it is necessary to make the timing different at each DUT on the transmitting side of the test apparatus 100d, or A timing comparator (not shown) side that receives data from the DUT 110 ₁ and the DUT 110 ₂ sets a different timing for each DUT.

As with the test apparatus 100 of Fig. 1, the above problems caused by the test apparatuses 100c, 100d using the comparative technique can be appropriately solved.

FIG. 3 is a block diagram showing a modification of the test apparatus 100 of FIG. 1. The test apparatus 100a of the modification differs from the test apparatus 100 of FIG. 1 in the position of the terminal circuit 22. The terminal circuit 22 is disposed on the motherboard 32.

Normally, the power supply voltage Vdd to the mating plate 34 is supplied from the power source 36 via the mother board 32. Therefore, the mother board 32 can always receive the supply of the power source voltage Vdd from the power source 36. When the buffer BUF of the terminal circuit 22 is disposed on the mother board 32, the generation of the reference voltage VT and the power supply of the buffer BUF can utilize the power supply voltage Vdd via the mother board 32. Since the terminal circuit 22 does not require as high precision as the driver 20, the configuration can be simplified, and can be easily disposed on the mother board 32 together with the second switch SW2. Further, if the terminal circuit 22 is provided on the mother board 32, a terminal for connecting the pin electronic component 30 and the mother board 32 is not required as compared with the case of FIG. 1, and the area of the pin electronic component 30 can be reduced. Since the area occupied by the terminal circuit 22 in Fig. 1 can be allocated to the driver 20, the number of channels can be increased.

In the embodiment, the case of N=2 has been described, but the present invention can be extended to any number such as N=4.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

[Industrial availability]

According to a certain aspect of the present invention, a plurality of components to be tested can be measured with high precision.

20. . . driver

twenty two. . . Terminal circuit

30. . . Pin electronic component

32. . . motherboard

34. . . Adapter plate

36‧‧‧Power supply

100‧‧‧Testing device

110‧‧‧Tested component (DUT)

BUF‧‧‧ buffer

L1‧‧‧1st wiring

L2‧‧‧2nd wiring

L3‧‧‧3rd wiring

L4‧‧‧4th wiring

P1‧‧‧ input and output terminal

RT‧‧‧ terminating resistor

SW1‧‧‧1st switch

SW2‧‧‧2nd switch

Figure 1 is a block diagram showing a portion of the construction of the test apparatus.

2(a) and 2(b) are block diagrams showing the configuration of a test apparatus of a comparative technique.

Fig. 3 is a block diagram showing a modification of the test apparatus of Fig. 1.

20. . . driver

twenty two. . . Terminal circuit

30. . . Pin electronic component

32. . . motherboard

34. . . Adapter plate

100. . . Test device

110. . . Tested component (DUT)

BUF. . . buffer

L1. . . First wiring

L2. . . Second wiring

L3. . . Third wiring

L4. . . 4th wiring

P1. . . Input and output terminal

RT. . . Terminating resistor

SW1. . . First switch

SW2. . . Second switch

Claims (6)

A test device is a test device for testing a time-divided test of N (N is an integer greater than or equal to 2) identical test elements respectively corresponding to an input/output terminal, comprising: a driver for the N tested components The corresponding input/output terminals are provided in common; the terminal circuit is provided in common with the corresponding input/output terminals of the N test elements; the first wiring connects the output terminal of the driver and the first node; and the second wiring And connecting the terminal circuit and the second node; and the N third wirings connect the first node and the N corresponding test elements to the terminal; and the N fourth wirings The second node and the corresponding input/output terminals of each of the N test elements are connected; and the first and second wires have a characteristic impedance of a predetermined value, and the N third wiring and the N fourth wiring are respectively It has a characteristic impedance of N times the aforementioned predetermined value. The test apparatus according to claim 1, wherein the first and second wirings are laid on a mother board that integrates the semiconductor wafer in which the driver is integrated and directly or indirectly mounts the N The mating plates of the tested components are connected to each other; the third and fourth wirings are laid on the mating plate. The test device of claim 2, wherein the former The terminal circuit is disposed on the aforementioned motherboard. The test apparatus according to claim 2, wherein the terminal circuit is integrated with the driver on the semiconductor wafer. The test apparatus according to claim 1 or 2, wherein N=2, the predetermined characteristic impedance is 50 Ω. The test apparatus according to any one of claims 1 to 4, wherein the N third wirings are of equal length.