JPH04240581A - Ic tester - Google Patents

Abstract

PURPOSE:To realize an IC tester in which an exact timing correction is performed by measuring a delay time in a transmission route between a rate generation device and a pin electronics and making timing standards of a plurality of the pin electronics agree to each other. CONSTITUTION:The output of a rate generation device 1 is branched into a plurality of outputs by the use of a distribution circuit 61 and transmitted for input to pin electronics 121-12n through a plurality of transmission routes 71-7n. Trailing end resistance R1 is connected to each trailing end C1-Cn of the transmission routes 71-7n through a switch SW and delay times in the transmission routes 71-7n are measured by the start signal o the transmission route and the reflection signals from the trailing ends C1-Cn at which the switch is turned off in a time measurement circuit 63 to compensate for the differences.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to LSI testers, etc.
This invention relates to improving timing accuracy in test equipment, particularly to reference timing distribution using high-precision timing measurement techniques such as TDR.

0002

[Prior Art] FIG. 7 is a block diagram showing a timing generation/correction system in a conventional LSI tester (NT
TR&D Vol. 38 No. 5 1989,
p537/546). The signal from the rate generator (TG) 1 includes timing errors due to delay differences in intermediate cables, etc., and is transmitted to each pin electronics (PE) 21.
~2n. Each of the PEs 21 to 2n exchanges signals with the corresponding pins of the device under test 3, and the device under test 3 is tested. Generally LSI
The tester cannot perform a correct test unless measurement timing standards for each pin of the device under test (DUT) 3 are aligned. Therefore, in order to align the timings from PE21 to PE2n, the channel selector 4 switches the channels to be corrected, and the timing correction unit (TC) 5 measures the delay time to be corrected for each channel. That is, TDR
(Time Domain Reflectome
DUT3 using try: time domain reflectometry)
When the end points of are in an open state, a step-like rising and falling waveform with a step width corresponding to the time of reciprocating the line length L is generated at the measurement terminal of TC5 due to the influence of total reflection, and sequentially PE21 to 2n-DUT3. Measure the line length between the two. There are also cases where the timing of PE21 to PE2n is directly measured by TC5.

0003

[Problem to be Solved by the Invention] However, in the case of the above-mentioned configuration, the delay time in PE changes frequently due to temperature fluctuations, so if correction is made including PE21 to 2n as described above, the correction frequency becomes high. Then, DUT3 again
Since the timing correction is performed while the is pulled out, there is a problem in that it takes a lot of man-hours and time. In addition, since it is necessary to switch the signal line directly connected to the DUT, it is difficult to implement the channel selector 4 with a semiconductor switch, and a mechanical switch is required, which is expensive, has low reliability, and
There are problems such as low speed. The present invention provides an IC test device with accurate timing correction by measuring the delay time in the transmission path between the rate generator and the pin electronics and matching the reference timing that is the reference for the operation of the pin electronics. The purpose is to realize this.

0004

[Means for Solving the Problems] The present invention provides an IC test device that applies test signals from a plurality of pin electronics to each pin of a device under test using the output of a rate generator transmitted via a transmission line as a timing reference. It is characterized by a distribution circuit that branches the output of the rate generator into multiple parts, multiple transmission lines that transmit each output of this distribution circuit to the input of the corresponding pin electronics, and A terminating resistor connected to each end of a plurality of transmission lines via a switch, a selection means for selecting one of the start ends of the plurality of transmission lines, a start end signal of the transmission line selected by the selection means, and the switch. and a time measurement circuit that measures the delay time in the transmission line from the reflected signal from the terminal end which is turned off, and is configured to compensate for the difference in delay time based on the output of the time measurement circuit. Another feature is that it includes a plurality of transmission paths for transmitting each output of the distribution circuit to the corresponding input of another distribution circuit.

[0005]

[Operation] The delay time in the transmission line between the output of the rate generator and the pin electronics is measured and corrected by the TDR method after being branched by the distribution circuit, so the transmission line can be switched using an electronic switch. The frequency of correction can be reduced, and accurate timing correction is possible. Furthermore, by configuring the distribution circuit in a hierarchical structure, it is possible to cope with the case of a large number of pins.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to the drawings. FIG. 1 is a block diagram showing a timing generation/correction system of an IC testing apparatus according to the present invention. The same parts as in FIG. 7 are given the same symbols.

1 is a rate generator (TG), 6 is a timing distributor (TD) that branches the rate signal output from the rate generator 1 into a plurality of transmission paths, and 71 to 7n are TDs.
Transmission line through which multiple outputs of 6 are transmitted, 121 to 12n
is a PE that sends and receives signals to and from each pin of the device under test 3 made of an LSI or the like, using each output of the transmission lines 71 to 7n as a timing reference. In TD6, the rate signal from rate generator 1 is sent to distribution circuit (DB) 61.
The signal is branched into a plurality of parts and applied to one end of the transmission lines 71 to 7n via a matching resistor Ro on the starting end side. The signal at this one end is further selected by a changeover switch 62 comprising a selection means, such as a semiconductor switch, and becomes an input to a time measurement circuit (TM) 63. PE121 ~12n
, the terminals C1 to Cn of the transmission lines 71 to 7n
is connected to the input stage of PE121 to PE12n, and also connected to the switch SW and the terminating resistor RI for matching.
Connect to common via.

[0008] The operation of the apparatus having the above configuration will now be described. FIG. 2 is a time chart showing a normal operating state when the SW is turned on. In this state, the transmission lines 71 to 7n are matched by the starting end resistance Ro and the ending end RI, so that no signal reflection occurs. The rate signal generated by TG1 is sent to PE121 ~ 12n by TD6.
One bottle each will be distributed. Each PE drives or measures the DUT 3 based on the distributed timing. Regarding the timing T2 of transmission to the termination points C1 to Cn via the transmission lines 71 to 7n, the delay time t2 varies for each PE due to manufacturing variations, deformation during mounting, etc.
In addition, variations in the delay time t1 of the DB 61 are also added.

FIG. 3 is a time chart showing an operating state in which any SW of PEs 121 to 12n is turned off and timing errors are measured. For example, when the SW of PE121 is turned off, reflection occurs at point C1, so B
If you measure the time from time T1 when driving at one point to time T3 when the reflected wave returns with TM63, this is equal to twice the propagation time t2 of the transmission line when SW is on, so measure the propagation time t2. can. Below PE122 ~
Similarly, the propagation time of each channel can be measured by sequentially turning off the 12n SWs. At the same time, by measuring with TM63 from drive time T0 at point A to time T1 when reaching point B1, the propagation time from the entrance of TD6 to the entrance of PE can be measured.

FIG. 4 shows a case where the delay time of the DB 61 is controlled based on the propagation time of each channel measured by the TM 63. As shown in the time chart of Figure 5, T
In M63, if integration is performed between times T0 and T1 with a slope of 2a, and between times T1 and T3 with a slope of a, the integral value Vi corresponds to the propagation time from point A to point C1. Measured on all distribution channels and all Vi
If the delay time of each delay element DL in the DB 61 is set so that the values are equal, the timing standards of the C1 to Cn points will match within several tens of ps. Moreover, the deviation in reference timing that occurs between PEs can be easily adjusted simultaneously for all PEs. Therefore, the reference timings of all pins of the DUT 3 can be accurately matched.

According to the IC test device having such a configuration,
Since the propagation delay time of timing distribution can be measured in the actual wiring state in which the DUT 3 is loaded, it is possible to accurately measure timing deviations due to wiring length and mounting. Furthermore, by measuring the delay time of the distributor itself, complete timing correction becomes possible. Further, since the channel switching switches SW and 62 handle standard signal levels, electronic switches such as semiconductor switches can be used for both, which are inexpensive, highly reliable, and fast. In addition, the frequency of correction for variations in delay time up to the entrance of pin electronics is not very high, and the correction in pin electronics that is frequent is performed internally by the pin electronics itself (for example, 51
(2 pins) can be aligned at the same time, so the time required for timing correction can be significantly shortened. In the above embodiment, instead of using the delay element DL in the timing distributor, the timing standards may be matched by setting data for each PE 121 to 12n according to the measured value of the time measurement circuit 63. good.

FIG. 6 is a configuration block diagram showing a timing generation/correction system of an embodiment of the IC test device according to the present application, in which the timing distributor is configured in a hierarchical structure to cope with the case of a large number of pins. It is a diagram. The rate signal output from the rate generator 1 is branched into n pieces at TD60, and each is sent to the TD via transmission lines 701 to 70n.
61 to 6n. Each TD61 to 6n has m transmission lines 711 to 71m,..., 7n1 to 7n.
branched into m, each corresponding pin electronics 1
211 to 121m, ..., 12n1 to 12nm. Each TD60, 61 to 6n has the same configuration as 6 in FIG. 1, and an electronic switch SW and a termination resistor RI are connected to the inputs of TD61 to 6n in the same way as the input of PE. The delay time of the transmission lines 701 to 70n is measured at TM of TD60, and the delay time of the transmission lines 711 to 7nm is measured at T.
Measured at TM from D1 to TDn. The delay time at each TD is also measured in the same manner as in FIG. As a result of configuring the timing distributor in two stages in this way, n×
The distribution of the reference timing to a large number of m PEs is achieved with high accuracy. Note that the structure is not limited to two stages, but can be configured in any number of stages.

[0013]

[Effects of the Invention] As described above, according to the present invention, the laser
By measuring the delay time in the transmission path between the pulse generator and the pin electronics and matching the timing standards of multiple pin electronics, it is possible to realize an IC test equipment with accurate timing correction with a simple configuration. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a main part of an embodiment of an IC testing device according to the present invention.

FIG. 2 is a time chart showing the normal operation of the device in FIG. 1;

FIG. 3 is a time chart showing the operation of the device in FIG. 1 during correction.

FIG. 4 is a partial configuration block diagram showing the detailed configuration of the device in FIG. 1;

FIG. 5 is a time chart showing the operation of the device shown in FIG. 4;

FIG. 6 is a block diagram showing the main parts of another embodiment of the IC testing device according to the present invention.

FIG. 7 is a block diagram showing a main part configuration of a conventional example of an IC test device.

[Explanation of symbols]

1 Rate generator 3 Device under test 71 to 7n, 701 to 70n, 711 to 7nm
Transmission lines 121 to 12n, 1211 to 121m,...,
12n1 to 12nm Pin electronics 61 Distribution circuit 62 Selection means 63 Time measurement circuit SW Switch RI Terminating resistor t2 Delay time

Claims (2)

[Claims] [Claim 1] A test signal that applies a test signal from a plurality of pin electronics to each pin of a device under test using the output of a rate generator transmitted via a transmission line as a timing reference.
C test equipment includes a distribution circuit that branches the output of the rate generator into multiple units, multiple transmission lines that transmit each output of this distribution circuit to the input of the corresponding pin electronics, and each of these multiple transmission lines. a terminating resistor connected to a terminal end via a switch; selection means for selecting one of the starting ends of the plurality of transmission lines; a starting end signal of the transmission line selected by the selection means; and a terminal end at which the switch is turned off. and a time measurement circuit that measures the delay time in the transmission path from a reflected signal from the IC, and is configured to compensate for a difference in delay time based on the output of the time measurement circuit.
Test equipment. 2. The IC testing apparatus according to claim 1, further comprising a plurality of transmission lines for transmitting each output of said distribution circuit to a corresponding input of another distribution circuit.