TW528875B - Method and device for adjusting timing of a semiconductor tester - Google Patents

Abstract

A method and a device for adjusting timing of a semiconductor tester are provided. According to the method, a plurality of signals are transmitted from a semiconductor tester to an adjusting device by simulating practical testing conditions. One of the signals is selected and measured a signal jitter including the effect of cross talk for adjusting the clock driver of the semiconductor tester.

Description

528875

[Field of the invention] The present invention is related to ^ and correction devices, especially j $ conductor test equipment, clock correction is a secondary talk] factor = there is a kind of method including cross-line interference [cross method to correct the semi-conductor true [Slgnal j.itter] Actual measurement side [Prior art] Clock of conductor testing equipment. In semiconductor testing, the operation of electrical modules such as memory modules, conductor wafers, semiconductor packaging structures, and conductor products. Φ test. Semiconductor testing equipment should provide

High-speed frequency, half twilight, # grasp # 耆 operation of various σ conductors to produce σσ • physical test 纟 ready clock driver [c 1 〇ck 1 r 1 = er ^ The frequency of the clock signal generated needs to be accelerated, Therefore, within each finite% pulse signal, the signal distortion deviation that the semiconductor test equipment can tolerate must be effectively regulated. However, the delay effect of the components and lines of the semiconductor test equipment itself will cause the distortion of the test signal, which will seriously affect the test signal of semiconductor products. Test system stability. In the invention patent of the Republic of China Patent Gazette No. 38 8795 "Auxiliary device and method for signal testing", a signal testing method for measuring the maximum and minimum jitter deviation is disclosed. The step is to first obtain the time difference between adjacent pulses of a signal. , And calculate the average value, and calculate the difference between each time difference and the average value ', so that the jitter deviation can be obtained according to the difference between each time difference and the average value, and a signal selection device is used to change the first signal and the first Action ^ Select one of the signal outputs, but during the inter-semiconductor test process, you must not output and accept a single test signal one by one. When multiple ^ trials are output and accepted, it is transmitted to the test. The line of the device itself

528875 V. Description of the invention (2) Between the roads, the signal ta 1 k, or the signal during the string test [the purpose of the invention and the pulse correction method of the present invention, the device and the selective signal distortion path, accurately correct the present invention Pulse correction device, circuit test of conductor testing equipment] Summary of factor distortion levels] The main purpose is to use multiple measurements, the degree of which has been included in the operation of the semiconductor should be considered together, in order to provide a signal transmitted in a The signal of the signal contains the line interference of cross-line dry good test equipment (cross quantity and calculation, in order to grasp the actual effect and consistent correction. The next is to provide the number, and has included the conductor measurement as the pulse correction test equipment, choose to install the oscilloscope element. The method is based on the method of transmitting the test equipment with a separate line to reach the device or signal [osc i distortion. The present invention has a product that uses a wave output device to measure the impact of disturbance. The above purpose simulates an actual correction device. The degree of electrical 11oscop e is selected, and the body circuit analog input terminal is used to output one of the signal factors for the purpose of the test conditions of the present invention. The body circuit simulator of the semiconducting semiconductor testing equipment and at least one kind of semiconductor factor affecting the degree of distortion of the semiconductor test number clock. This type of semiconductor tester has multiple devices that receive calibration test signals that are not valid and actually test the device. The device and the calibration are therefore tested. Therefore, for the test of valid devices, each test corresponds to multiple levels of reliability. When the semi-1! '≪ Λ semiconductor test equipment is calibrated, a plurality of signals are transmitted from a semiconductor test simulator to a calibration device via a signal signal, and the measurement includes a clock of the line interference test equipment. Driving clock correction device, which is a main oscilloscope, the integrated circuit

528875

Simulators, such as wafer simulators and crystal simulators, have a plurality of input and output terminals corresponding to the semiconductor test connected to the oscilloscope. Preferably, the selection circuit or the integrated signal selection device is used to Selective quantity [Detailed description of the invention] The chip simulator or the semiconductor package structure's input terminal and at least one output terminal, the output terminal of these devices, the output terminal is connected to the integrated circuit simulator, which includes a signal simulator and an oscilloscope Connect a measurement signal distortion. As shown in Figures 1 and 2, the clock correction device 20 and at least one oscilloscope 30 of the test equipment, pulse 0 According to a specific embodiment of the present invention, the semiconductor system mainly includes an integrated circuit simulator to calibrate the semiconductor test equipment. At 10, as shown in Figures 1 and 2, the integrated circuit simulator 20 is provided with an output terminal 22, such as a wafer simulator, a wafer simulator I, a conductor assembly, and a structured board simulator. The plurality of input terminals 21 of the body circuit simulator 20 are corresponding to the output terminals of the semiconductor testing equipment 10 (such as the probes 13). In this embodiment, the semiconductor testing equipment is a test for testing a semiconductor wafer. The device has a test head, and a probe card 12 ipr0be card is installed at the test head 11, and the probe card 12 is formed with a plurality of probes 13 in a conventional semiconductor test process. The probe 13 is an electrode [eletrode] that presses on a semiconductor wafer such as a pad or a bump, and serves as an output terminal of the semiconductor test equipment 10. The integrated circuit simulator 20 is a wafer simulator. , A plurality of rows of round ends 2 j Simulation-based distribution of the test electrodes of the semiconductor wafer, moreover, the integrated circuit-based simulator 20 having a signal receiving circuit 23, and a signal selection circuit

Page 6 528875 V. Description of the invention (4) '-24' The signal receiving circuit 23 is connected to the plurality of input terminals 21, and the outside% ^ δίΐ said that the selection circuit 24 has a plurality of relay switches 25 [relay] , Which is connected to the input terminal 21 corresponding to the signal receiving circuit 23 for selective switching, and the other end of the signal selection circuit 24 is at least one round out terminal 2 2 for the transmission line 26 to be connected to an oscilloscope 30 [ osci i 1〇sc〇pe]. ’The oscilloscope 30 is a synchronous oscilloscope [SynChroscope] or a mechanical wave filter, which is electrically connected to the output terminal 22 of the integrated circuit simulator 2 0 to measure the signal distortion level of the test signal. The clock correction method of the semiconductor test equipment according to the present invention uses the above-mentioned calibration device to correct the clock of the semiconductor test equipment. First, after the calibration device is placed and positioned, the semiconductor test equipment is started and the probe card is activated.

1 2 of the plurality of probes 1 3 (that is, the plurality of output terminals of the semiconductor test equipment) are in contact with the integrated circuit simulator 2 0 of the plurality of corresponding input terminals 2 1 to complete electrical conduction, and according to the actual test one The output frequency of the semiconductor wafer [100 ~ 50 0MHz, or even higher frequency] and test conditions. Multiple signals are output from the plurality of probes on the semiconductor test equipment 10 and the output terminal to the integrated circuit. The input terminal 21 of the simulator 20 uses the circuit selection circuit 24 to turn on one of the relay switches 25, so that one of a plurality of signals can be selectively transmitted to the oscilloscope 30 to measure the signal distortion level of the signal. sgna ijit ter], such as the eye diagram, because the multiple signals are transmitted to the semiconductor test equipment 10 to simulate actual test conditions, the selected signals can reflect a single line offset in the semiconductor test equipment 10 'Effects such as transmission delay' can also reflect the influence factors of cross talk caused by the magnetic field of adjacent lines. In this way, the measured signal distortion process

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5. The description of the invention will be extremely accurate, so the measured §fl 5 tiger distortion level can be provided as a clock driver for the day when the semiconductor test equipment is violated, to reduce the instrument error of the semiconductor test equipment. It is especially suitable for clock correction of "high-frequency" semiconductor test equipment, and even test the distortion spear of the signal one by one. After the measurement, the standard error, the maximum error, or the minimum error calculated by it can be used as the quality judgment and acceptance reference of the conductor testing equipment. Calibration method Simulator 20: The electrical output signal of the device 20 is measured by another device. When a signal is selected, the semiconductor output is selected. The connected output is selected. The measured result is corrected. The protection is familiar with this and the other integrated circuit body circuit simulation 2 5 makes multi-device 10, in contrast to the semiconductor test simulator 40 of the present invention, to faster calibration 4 0 is a probe with simulator 40 3 [ The transmission switches 51 and 61, 62 use the number of distortion levels, whichever is more accurate, whichever is the originator. Any number of probes 33 and 33 which are in contact with the corresponding wheel-in terminal 2 After 1, turn off all the relay switches by using the product selection circuit 2 4 and the signal is transmitted to the probe 1 3 and reflected back to the distortion level of the semiconductor test number. In the embodiment, as shown in FIG. 3, a pulse correction device is provided. The pulse correction device includes an integrated circuit selection device 50 and a plurality of oscilloscopes 61 and 62. The clock of the test device 10 is used to simulate the integrated circuit. Terminal 41 and output terminal 42, where the integrated circuit input terminal 41 is corresponding to the semiconductor test equipment, and the signal selection device 50 is provided with the output terminals 42 of the relay circuit simulator 40 and the oscilloscope. Signals for faster measurement. Signal distortion levels include line interference factors, clock drivers for body testing equipment. 1 Those skilled in the art, as defined in the scope of patent application, do not depart from the spirit and scope of the present invention.

528875 V. Description of the Invention Any changes and modifications made within the scope are within the protection scope of the present invention.

U ΙΙϋΙ Page 9 528875 Brief Description of Drawings [Illustration of Drawings] Figure 1: Schematic diagram of a semiconductor test equipment and a calibration device according to a specific embodiment of the present invention; Figure 2 ·· Specifically according to one of the present invention In the embodiment, a schematic diagram of the circuit connection between the calibration device and the semiconductor test equipment; and FIG. 3 is a schematic diagram of the circuit connection of a calibration device and the semiconductor test equipment according to another specific embodiment of the present invention. [Illustration of the drawing number] 10 Semiconductor test equipment 11 Test head 12 Probe card 13 Probe 20 Integrated circuit simulator 21 Input 22 Output 23 Signal receiving circuit 24 Signal selection circuit 25 Relay switch 26 Transmission line 30 Oscilloscope 40 Integrated circuit simulator 41 input terminal 42 output terminal 50 signal selection device 51. relay switch 61 oscilloscope 62 oscilloscope

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Claims (1)

528875 VI. Scope of patent application-'— " —- [Scope of patent application] 1. A method for clock calibration of semiconductor test equipment, which includes the steps as follows: Provide an oscilloscope to multiply the semiconducting simulator wheel. The signal loss of integrated electrical selectivity, such as applying a pulse correction cube test device, such as applying a pulse correction cube semiconductor, such as applying a pulse correction cube test, a semi-integral output, the semiconductor test correction device, which includes Yes-the integrated circuit simulator and at least a plurality of corresponding input terminals of the body test equipment; the signals are sent by the semiconductor road test simulator; and at least one of the signals is transmitted. The first method of the patent scope, the first method of the patent scope of the probe card on the transmission equipment, which also includes the first method of the patent scope when testing equipment, where the output frequency of the output wheel is a phase conductor test equipment circuit simulator, The steps in the output item of the integrated circuit § device are output to all of the items: the steps in the pulse-driven item are the same. At the time, it has a simulator terminal; and the output terminal of the wheel is in contact with the output terminals of the integrated circuit test equipment to the oscilloscope to measure the actual-multiple signals of the semiconductor test equipment described in dc Via the semiconductor the integrated circuit simulator. The measured signal distortion corrector at the time of the semiconductor test equipment described above. At the time of the semiconductor test equipment described above, the output frequency of the signal and the actual correction device include: a plurality of input terminals and at least one round of the plurality of input terminals correspond to 528875 6. Scope of patent application At least one oscilloscope is electrically connected to the output terminal of the integrated circuit simulator. 6. The clock correction device for semiconductor test equipment as described in item 5 of the scope of patent application, wherein the integrated circuit simulator is a wafer simulator. 7. The clock correction device for semiconductor test equipment as described in item 5 of the scope of patent application, where the integrated circuit is simulated? § is a 'Chip Simulator'. 8. The clock correction device for semiconductor testing equipment as described in item 5 of the scope of patent application, wherein the integrated circuit simulator is a simulator of a semiconductor package structure. 9. The clock correction device for semiconductor test equipment as described in item 5 of the scope of patent application, wherein the integrated circuit simulator includes a signal connection? Receive circuit and a signal selection circuit. \ 1 0. The clock correction device of the semiconductor test equipment as described in item 5 of the scope of patent application, which also includes a signal selection device, which is connected to the integrated circuit simulator and the oscilloscope. Page 12