WO2010001440A1 - Test device and socket board - Google Patents

Test device and socket board Download PDF

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Publication number
WO2010001440A1
WO2010001440A1 PCT/JP2008/001772 JP2008001772W WO2010001440A1 WO 2010001440 A1 WO2010001440 A1 WO 2010001440A1 JP 2008001772 W JP2008001772 W JP 2008001772W WO 2010001440 A1 WO2010001440 A1 WO 2010001440A1
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WO
WIPO (PCT)
Prior art keywords
wirings
input
output terminals
driver
socket board
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PCT/JP2008/001772
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French (fr)
Japanese (ja)
Inventor
関信介
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株式会社アドバンテスト
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Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to JP2010518828A priority Critical patent/JPWO2010001440A1/en
Priority to PCT/JP2008/001772 priority patent/WO2010001440A1/en
Priority to KR1020117001931A priority patent/KR20110033846A/en
Priority to TW098122428A priority patent/TWI396854B/en
Publication of WO2010001440A1 publication Critical patent/WO2010001440A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Definitions

  • the present invention relates to a semiconductor device test apparatus, and more particularly to pin electronics timing calibration technology.
  • a test apparatus that tests a semiconductor device includes a plurality of pin electronics in order to give a test pattern to a DUT pin and read data from the DUT.
  • Each pin electronics includes a driver that outputs a signal to a corresponding pin of the DUT and a comparator that determines the level of the signal output from the corresponding pin.
  • each pin electronics ie driver
  • a single pin of the DUT is assigned a single pin of the DUT.
  • the corresponding driver and the DUT pin are connected by wiring having a predetermined characteristic impedance Zo (for example, 50 ⁇ ) laid on the mother board and the socket board.
  • Zo for example, 50 ⁇
  • a method of branching a signal from a single driver and supplying it to a plurality of DUTs to increase the number of simultaneous measurements has become common. .
  • the present invention has been made in view of such a situation, and an object thereof is to provide a test apparatus capable of measuring a plurality of DUTs with high accuracy.
  • a certain aspect of the present invention relates to a test apparatus for testing N devices (N is an integer of 2 or more) each having at least one input / output terminal.
  • the test apparatus includes a driver provided in common for input / output terminals of N devices under test, a termination circuit provided in common for input / output terminals of N devices under test, The first wiring connecting the output terminal and the first node, the second wiring connecting the termination circuit and the second node, and the input / output terminals of the first node and each of the N devices under test are connected.
  • the first and second wirings have a predetermined characteristic impedance
  • the N third wirings and the N fourth wirings each have a characteristic impedance N times the predetermined value.
  • the impedance when looking into the plurality of devices under test from the driver and the impedance when looking into the multiple devices under test from the termination circuit are all equal to the predetermined characteristic impedance, the impedance is highly accurate. Matching can be realized and high-accuracy testing can be realized.
  • the first and second wirings may be laid on a mother board that connects between a semiconductor chip on which drivers are integrated and a socket board on which N devices under test are directly or indirectly mounted.
  • the third and fourth wirings may be laid on the socket board.
  • the termination circuit may be provided on the motherboard. In this case, the number of drivers (number of channels) that can be formed in one semiconductor chip can be increased, and the number of terminals of the semiconductor chip can be reduced.
  • the termination circuit may be mounted on the semiconductor chip together with the driver.
  • the predetermined value of the characteristic impedance may be 50 ⁇ .
  • the N third wirings may be of equal length. In this case, there is an advantage that it is not necessary to optimize the timing of the test pattern supplied from the driver for each of the plurality of DUTs.
  • the socket board includes a first terminal to be connected to an output terminal of a driver provided in common to input / output terminals of N devices under test in a state where the socket board is mounted on the motherboard, and the socket board. Is mounted on the motherboard, the second terminal to be connected to the termination circuit provided in common to the input / output terminals of the N devices under test, the first terminal, and the N devices under test, respectively.
  • the N third wirings and the N fourth wirings have the same characteristic impedance. According to this aspect, it is possible to simultaneously measure a plurality of devices under test while suppressing the influence of reflection.
  • the N third wirings may be of equal length.
  • a plurality of devices under test can be measured with high accuracy.
  • FIG. 2A and 2B are block diagrams illustrating the configuration of a test apparatus according to a comparative technique. It is a block diagram which shows the modification of the test apparatus of FIG.
  • DESCRIPTION OF SYMBOLS 100 ... Test apparatus, 110 ... DUT, 20 ... Driver, 22 ... Termination circuit, RT ... Termination resistance, BUF ... Buffer, SW1 ... First switch, SW2 ... Second switch, L1 ... First wiring, L2 ... Second wiring , L3 ... third wiring, L4 ... fourth wiring, 30 ... pin electronics, 32 ... motherboard, 34 ... socket board, 36 ... power supply, P1 ... input / output terminal.
  • the state in which the member A is connected to the member B means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. It includes the case of being indirectly connected through another member that does not affect the above.
  • the state in which the member C is provided between the member A and the member B refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.
  • FIG. 1 is a block diagram showing a part of the configuration of the test apparatus 100.
  • the test apparatus 100 includes a pin electronics 30, a motherboard 32, a socket board 34, and other timing generators and pattern generators (not shown). Since the function and configuration of the test apparatus 100 itself are general, only the portions related to the present invention will be described in detail.
  • the test apparatus 100 has a function of measuring a plurality of N DUTs 110 simultaneously.
  • the plurality of DUTs 110 are usually assumed to be the same device (same type), but may be different.
  • Each DUT 110 includes at least one input / output terminal.
  • subscripts are attached as necessary. For the sake of brevity, only the first input / output terminal P1 will be described.
  • the driver 20 is provided in common to the input / output terminals P1 1 and P1 2 of the two DUTs 110 1 and 110 2 .
  • the driver 20 outputs a test pattern to each of the input / output terminals P1 1 and P1 2 in a time division manner.
  • the driver 20 outputs a voltage VIH corresponding to a high level when the test pattern is 1, and a voltage VIL corresponding to a low level when the test pattern is 0.
  • a first switch SW1 is provided on the output side of the driver 20.
  • the first switch SW1 may be a mechanical switch such as a relay or an electrical switch such as a transfer gate.
  • the termination circuit 22 is also provided in common to the input / output terminals P1 1 and P1 2 of the two DUTs 110 1 and 110 2 respectively.
  • termination circuit 22 includes a termination resistor RT and a buffer BUF.
  • the buffer BUF fixes the potential at one end of the termination resistor RT to a predetermined value VT (for example, the midpoint between VIH and VIL).
  • a second switch SW2 is provided at the other end of the termination resistor RT.
  • the first wiring L1 connects between the output terminal of the driver 20 and the first node N1.
  • the second wiring L2 connects between the termination circuit 22 and the second node N2.
  • the socket board 34 is configured to be detachable from the mother board 32, and is connected via connector pins PC1 and PC2.
  • the first node N1 corresponds to the connector pin PC1, but a part of the first wiring L1 may be laid on the socket board 34 and the first node N1 may be provided on the socket board 34. .
  • a plurality of N third wirings L3 1 and L3 2 respectively connect the first node N1 and the input / output terminals P1 1 and P12 of the two DUTs 110 1 and 110 2 respectively. That is, the plurality of third wirings L3 1 and L3 2 are formed to branch from the first node N1 to the plurality of input / output terminals P1 1 and P1 2 .
  • the plurality of N fourth wirings L4 1 and L4 2 respectively connect the second node N2 and the two input / output terminals P1 1 and P1 2 of 110 1 and 110 2 . That plurality of fourth wirings L4 1, L4 2, as a starting point the connector pin PC2, are formed by branching into a plurality of input-output terminals P1 1, P1 2.
  • the second node N2 may coincide with the connector pin PC2.
  • the above is the connection mode of the plurality of DUTs 110, the driver 20, and the termination circuit 22. Furthermore, the test apparatus 100 of FIG. 1 has the following features.
  • the first wiring L1 and the second wiring L2 each have a characteristic impedance ZO of a predetermined value 50 ⁇ .
  • the N third wirings L3 1 and L3 2 and the N fourth wirings L4 1 and L4 2 each have a characteristic impedance ZO of 100 ⁇ that is N times (two times) the predetermined value 50 ⁇ .
  • N times does not mean exact N times, and may be deviated from N times as long as impedance mismatch does not affect the measurement.
  • the impedance viewed from the termination circuit 22 to the plurality of DUTs 110 can be matched with 50 ⁇ . Furthermore, since both ends on the sending end (driver 20) side and receiving end (110) side are terminated, the influence of reflection can be suppressed. By these, a highly accurate test can be realized.
  • the N third wirings L3 1 and L3 2 are of equal length. Consequently, to align the propagation time until the test pattern output from the driver 20 reaches the output terminal P1 1 of one 110 1, the propagation time to reach the output terminal P1 2 of the other 110 2 Can do.
  • the DUT 110 can be operated at the same timing for a plurality of DUTs 110 for data of the same channel, so that a timing adjustment function for each DUT is not required on both the DUT 110 side and the test apparatus 100 side. It becomes.
  • the test apparatus 100 has the following features.
  • the test apparatus 100 is divided into a pin electronics 30, a mother board 32, and a socket board 34.
  • a plurality of DUTs are directly or indirectly attached to the socket board 34.
  • the pin electronics 30 is a semiconductor chip on which a multi-channel driver 20 and a termination circuit 22 are integrated.
  • the mother board 32 connects between the pin electronics 30 and the socket board 34.
  • the first wiring L1 and the second wiring L2 are laid on the mother board 32.
  • a part of the third wiring L3, the fourth wiring L4, and the second wiring L2 is laid on the socket board 34. That is, the first node N1 and the second node N2 are arranged on the boundary between the mother board 32 and the socket board 34 or closer to the socket board 34 than the boundary. According to this configuration, even if the pin arrangement of the DUT 110 is changed, only the socket board 34 needs to be designed, and the pin electronics 30 and the mother board 32 need not be changed.
  • the above is the configuration of the test apparatus 100 according to the embodiment.
  • the effect of the test apparatus 100 is further clarified by comparison with the comparative technique shown in FIGS. 2 (a) and 2 (b).
  • the test apparatus 100c in FIG. 2A does not include the termination circuit 22.
  • the impedance matching is theoretically achieved, and therefore, there is no influence of reflection.
  • the receiving end (DUT) side is actually open, if there is a slight difference between the characteristic impedances of the two third wirings L3 1 and L3 2 , data transmission is easily affected by reflected waves. .
  • the input capacities of the DUTs 110 1 and 110 2 are different or the balance is lost when one of the DUTs is removed, the influence of the reflected wave becomes large.
  • the test apparatus 100d in FIG. 2B includes a wiring L5 that connects between the input / output terminals P1 1 and P1 2 of the DUTs 110 1 and 110 2 .
  • both the transmission end side and the reception end side are terminated, and there is no branch path, so that the configuration is not easily affected by reflection.
  • the timing is different for each DUT on the transmission side of the test apparatus 100d.
  • FIG. 3 is a block diagram showing a modification of the test apparatus 100 of FIG.
  • the test apparatus 100a according to the modification is different from the test apparatus 100 of FIG.
  • the termination circuit 22 is provided on the mother board 32.
  • the power supply voltage Vdd for the socket board 34 is supplied from the power supply 36 via the mother board 32. Therefore, the mother board 32 is always supplied with the power supply voltage Vdd from the power supply 36.
  • the buffer BUF of the termination circuit 22 is arranged on the mother board 32, the power supply voltage Vdd passing through the mother board 32 can be used for generation of the reference voltage VT and power supply of the buffer BUF. Since the termination circuit 22 does not require as high accuracy as the driver 20, the configuration can be simplified, and therefore it can be easily arranged on the mother board 32 together with the second switch SW2.
  • the termination circuit 22 is provided on the mother board 32, a terminal for connecting the pin electronics 30 and the mother board 32 is not required, and the area of the pin electronics 30 can be reduced as compared with the case of FIG. Since the area occupied by the termination circuit 22 in FIG. 1 can be allocated to the driver 20, the number of channels can be increased.
  • a plurality of devices under test can be measured with high accuracy.

Abstract

A test device (100) tests N (N is an integer of 2 or more) DUTs (110), each of which is provided with one or more input/output terminals (P1). A driver (20) is provided in common to the input/output terminals (P1) of the N DUTs (110). A terminating circuit (22) is provided in common to the input/output terminals (P1) of the N DUTs (110). A first wiring (L1) connects the output terminal of the driver (20) with a first node (N1). A second wiring (L2) connects the terminating circuit (22) with a second node (N2). N third wirings (L3) connect the first node with the input/output terminals (P1) of the respective N DUTs (110). N fourth wirings (L4) connect the second node (N2) with the input/output terminals (P1) of the respective N DUTs (110). The first wiring (L1) and the second wiring (L2) have a characteristic impedance (ZO) of a predetermined value, and the N third wirings (L3) and the N fourth wirings (L4) have a characteristic impedance of N-times the predetermined value.

Description

試験装置およびソケットボードTest equipment and socket board
　本発明は、半導体デバイスの試験装置に関し、特にピンエレクトロニクスのタイミングキャリブレーション技術に関する。 The present invention relates to a semiconductor device test apparatus, and more particularly to pin electronics timing calibration technology.
　半導体デバイス（以下、ＤＵＴともいう）を試験する試験装置は、ＤＵＴのピンに対してテストパターンを与え、またＤＵＴからデータを読み出すために、複数のピンエレクトロニクスを備える。各ピンエレクトロニクスは、ＤＵＴの対応するピンに対して信号を出力するドライバと、対応するピンから出力される信号のレベルを判定するコンパレータを含む。 2. Description of the Related Art A test apparatus that tests a semiconductor device (hereinafter also referred to as a DUT) includes a plurality of pin electronics in order to give a test pattern to a DUT pin and read data from the DUT. Each pin electronics includes a driver that outputs a signal to a corresponding pin of the DUT and a comparator that determines the level of the signal output from the corresponding pin.
　通常、各ピンエレクトロニクス、すなわちドライバにはＤＵＴの単一のピンが割り当てられる。対応するドライバとＤＵＴのピンとの間は、マザーボードおよびソケットボード上に敷設された所定の特性インピーダンスＺｏ（たとえば５０Ω）を有する配線で結線される。近年では、テストコストの削減、ハードウェア資源の有効利用を目的として、単一のドライバからの信号を分岐して複数のＤＵＴへと供給し、同時測定数を上げる手法が一般的となっている。 Typically, each pin electronics, ie driver, is assigned a single pin of the DUT. The corresponding driver and the DUT pin are connected by wiring having a predetermined characteristic impedance Zo (for example, 50Ω) laid on the mother board and the socket board. In recent years, for the purpose of reducing test costs and effectively using hardware resources, a method of branching a signal from a single driver and supplying it to a plurality of DUTs to increase the number of simultaneous measurements has become common. .
　メモリデバイスをはじめとするＤＵＴの高速化にともない、試験装置にはより高精度な測定が求められる一方、同時測定数を上げると、ドライバとＤＵＴ間のインピーダンスの不整合が顕著となり、高速化、高精度化の妨げとなっている。 As the speed of DUTs including memory devices increases, more accurate measurement is required for test equipment. On the other hand, when the number of simultaneous measurements is increased, impedance mismatch between the driver and DUT becomes noticeable. This hinders high accuracy.
　本発明はかかる状況に鑑みてなされたものであり、その目的は、複数のＤＵＴを高精度で測定可能な試験装置の提供にある。 The present invention has been made in view of such a situation, and an object thereof is to provide a test apparatus capable of measuring a plurality of DUTs with high accuracy.
　本発明のある態様は、それぞれが少なくともひとつの入出力端子を備えるＮ個（Ｎは２以上の整数）の被試験デバイスを試験する試験装置に関する。この試験装置は、Ｎ個の被試験デバイスの入出力端子に対して共通に設けられたドライバと、Ｎ個の被試験デバイスの入出力端子に対して共通に設けられた終端回路と、ドライバの出力端子と第１ノードの間を接続する第１配線と、終端回路と第２ノードの間を接続する第２配線と、第１ノードとＮ個の被試験デバイスそれぞれの入出力端子を結線するＮ本の第３配線と、第２ノードとＮ個の被試験デバイスそれぞれの入出力端子を結線するＮ本の第４配線と、を備える。第１、第２配線は所定値の特性インピーダンスを有し、Ｎ本の第３配線とＮ本の第４配線はそれぞれ、所定値のＮ倍の特性インピーダンスを有する。 A certain aspect of the present invention relates to a test apparatus for testing N devices (N is an integer of 2 or more) each having at least one input / output terminal. The test apparatus includes a driver provided in common for input / output terminals of N devices under test, a termination circuit provided in common for input / output terminals of N devices under test, The first wiring connecting the output terminal and the first node, the second wiring connecting the termination circuit and the second node, and the input / output terminals of the first node and each of the N devices under test are connected. N third wirings, and N fourth wirings connecting the second node and the input / output terminals of each of the N devices under test. The first and second wirings have a predetermined characteristic impedance, and the N third wirings and the N fourth wirings each have a characteristic impedance N times the predetermined value.
　この態様によると、ドライバから複数の被試験デバイス側を覗いたインピーダンス、ならびに終端回路から複数の被試験デバイス側を覗いたインピーダンスが、いずれも所定値の特性インピーダンスと一致するため、高い精度でインピーダンス整合が実現でき、高精度な試験が実現できる。 According to this aspect, since the impedance when looking into the plurality of devices under test from the driver and the impedance when looking into the multiple devices under test from the termination circuit are all equal to the predetermined characteristic impedance, the impedance is highly accurate. Matching can be realized and high-accuracy testing can be realized.
　第１、第２配線は、ドライバが集積化される半導体チップとＮ個の被試験デバイスが直接または間接的に装着されるソケットボードとの間を接続するマザーボード上に敷設されてもよい。第３、第４配線は、ソケットボード上に敷設されてもよい。 The first and second wirings may be laid on a mother board that connects between a semiconductor chip on which drivers are integrated and a socket board on which N devices under test are directly or indirectly mounted. The third and fourth wirings may be laid on the socket board.
　終端回路は、マザーボード上に設けられてもよい。この場合、ひとつの半導体チップに形成可能なドライバの個数（チャンネル数）を増加させることができ、また半導体チップの端子数を低減できる。 The termination circuit may be provided on the motherboard. In this case, the number of drivers (number of channels) that can be formed in one semiconductor chip can be increased, and the number of terminals of the semiconductor chip can be reduced.
　終端回路は、半導体チップにドライバとともに実装されてもよい。 The termination circuit may be mounted on the semiconductor chip together with the driver.
　Ｎ＝２であり、特性インピーダンスの所定値は５０Ωであってもよい。 N = 2, and the predetermined value of the characteristic impedance may be 50Ω.
　Ｎ本の第３配線は等長であってもよい。この場合、ドライバから供給するテストパターンのタイミングを、複数のＤＵＴごとに最適化する必要がないという利点がある。 The N third wirings may be of equal length. In this case, there is an advantage that it is not necessary to optimize the timing of the test pattern supplied from the driver for each of the plurality of DUTs.
　本発明の別の態様は、それぞれが少なくともひとつの入出力端子を備えるＮ個（Ｎは２以上の整数）の被試験デバイスが装着されるソケットボードに関する。このソケットボードは、ソケットボードがマザーボードに装着された状態において、Ｎ個の被試験デバイスの入出力端子に対して共通に設けられたドライバの出力端子と接続されるべき第１端子と、ソケットボードがマザーボードに装着された状態において、Ｎ個の被試験デバイスの入出力端子に対して共通に設けられた終端回路と接続されるべき第２端子と、第１端子とＮ個の被試験デバイスそれぞれの入出力端子を結線するＮ本の第３配線と、第２端子を始点としてＮ個の被試験デバイスそれぞれの入出力端子に分岐して到るＮ本の第４配線と、を備える。Ｎ本の第３配線とＮ本の第４配線はそれぞれ、同一の特性インピーダンスを有する。
　この態様によれば、反射の影響を抑制しつつ、複数の被試験デバイスの同時測定が可能となる。 Another aspect of the present invention relates to a socket board on which N devices (N is an integer of 2 or more) each having at least one input / output terminal are mounted. The socket board includes a first terminal to be connected to an output terminal of a driver provided in common to input / output terminals of N devices under test in a state where the socket board is mounted on the motherboard, and the socket board. Is mounted on the motherboard, the second terminal to be connected to the termination circuit provided in common to the input / output terminals of the N devices under test, the first terminal, and the N devices under test, respectively. N third wirings for connecting the input / output terminals to the input / output terminals, and N fourth wirings that branch from the second terminal to the input / output terminals of each of the N devices under test. The N third wirings and the N fourth wirings have the same characteristic impedance.
According to this aspect, it is possible to simultaneously measure a plurality of devices under test while suppressing the influence of reflection.
　Ｎ本の第３配線は等長であってもよい。 The N third wirings may be of equal length.
　なお、以上の構成要素の任意の組み合わせや、本発明の構成要素や表現を、方法、装置、システムなどの間で相互に置換したものもまた、本発明の態様として有効である。 It should be noted that any combination of the above-described constituent elements, or those obtained by mutually replacing constituent elements and expressions of the present invention among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.
　本発明のある態様によれば、複数の被試験デバイスを高精度で測定できる。 According to an aspect of the present invention, a plurality of devices under test can be measured with high accuracy.
試験装置の構成の一部を示すブロック図である。It is a block diagram which shows a part of structure of a test apparatus. 図２（ａ）、（ｂ）は、比較技術に係る試験装置の構成を示すブロック図である。2A and 2B are block diagrams illustrating the configuration of a test apparatus according to a comparative technique. 図１の試験装置の変形例を示すブロック図である。It is a block diagram which shows the modification of the test apparatus of FIG.
符号の説明Explanation of symbols
１００…試験装置、１１０…ＤＵＴ、２０…ドライバ、２２…終端回路、ＲＴ…終端抵抗、ＢＵＦ…バッファ、ＳＷ１…第１スイッチ、ＳＷ２…第２スイッチ、Ｌ１…第１配線、Ｌ２…第２配線、Ｌ３…第３配線、Ｌ４…第４配線、３０…ピンエレクトロニクス、３２…マザーボード、３４…ソケットボード、３６…電源、Ｐ１…入出力端子。 DESCRIPTION OF SYMBOLS 100 ... Test apparatus, 110 ... DUT, 20 ... Driver, 22 ... Termination circuit, RT ... Termination resistance, BUF ... Buffer, SW1 ... First switch, SW2 ... Second switch, L1 ... First wiring, L2 ... Second wiring , L3 ... third wiring, L4 ... fourth wiring, 30 ... pin electronics, 32 ... motherboard, 34 ... socket board, 36 ... power supply, P1 ... input / output terminal.
　以下、本発明を好適な実施の形態をもとに図面を参照しながら説明する。各図面に示される同一または同等の構成要素、部材、処理には、同一の符号を付するものとし、適宜重複した説明は省略する。また、実施の形態は、発明を限定するものではなく例示であって、実施の形態に記述されるすべての特徴やその組み合わせは、必ずしも発明の本質的なものであるとは限らない。 Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.
　本明細書において、「部材Ａが部材Ｂに接続された状態」とは、部材Ａと部材Ｂが物理的に直接的に接続される場合や、部材Ａと部材Ｂが、電気的な接続状態に影響を及ぼさない他の部材を介して間接的に接続される場合も含む。
　同様に、「部材Ｃが、部材Ａと部材Ｂの間に設けられた状態」とは、部材Ａと部材Ｃ、あるいは部材Ｂと部材Ｃが直接的に接続される場合のほか、電気的な接続状態に影響を及ぼさない他の部材を介して間接的に接続される場合も含む。 In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. It includes the case of being indirectly connected through another member that does not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.
　図１は、試験装置１００の構成の一部を示すブロック図である。試験装置１００は、ピンエレクトロニクス３０、マザーボード３２、ソケットボード３４およびその他の図示しないタイミング発生器やパターン発生器などを備える。試験装置１００そのものの機能、構成は一般的なものであるため、本発明に関係のある部分についてのみ詳細に説明する。 FIG. 1 is a block diagram showing a part of the configuration of the test apparatus 100. The test apparatus 100 includes a pin electronics 30, a motherboard 32, a socket board 34, and other timing generators and pattern generators (not shown). Since the function and configuration of the test apparatus 100 itself are general, only the portions related to the present invention will be described in detail.
　試験装置１００は、複数Ｎ個のＤＵＴ１１０を同時に測定する機能を有している。以下では理解の容易化、説明の簡潔化を目的としてＮ＝２の場合を説明するが、本発明はこれに限定されない。複数のＤＵＴ１１０は通常同じデバイス（同一品種）であることが想定されるが、異なっていても構わない。ＤＵＴ１１０はそれぞれ、少なくともひとつの入出力端子を備える。以下、各ＤＵＴの部材を区別するために必要に応じて添え字を付す。また説明を簡潔とするため、１番目の入出力端子Ｐ１にのみ注目して説明をする。 The test apparatus 100 has a function of measuring a plurality of N DUTs 110 simultaneously. Hereinafter, a case where N = 2 is described for the purpose of facilitating understanding and simplifying the description, but the present invention is not limited to this. The plurality of DUTs 110 are usually assumed to be the same device (same type), but may be different. Each DUT 110 includes at least one input / output terminal. Hereinafter, in order to distinguish the members of each DUT, subscripts are attached as necessary. For the sake of brevity, only the first input / output terminal P1 will be described.
　ドライバ２０は、２つのＤＵＴ１１０１、１１０２それぞれの入出力端子Ｐ１１、Ｐ１２に対して共通に設けられる。ドライバ２０は、各入出力端子Ｐ１１、Ｐ１２に対して時分割的にテストパターンを出力する。ドライバ２０は、テストパターンが１のとき、ハイレベルに相当する電圧ＶＩＨを、０のときローレベルに相当する電圧ＶＩＬを出力する。ドライバ２０は、その出力インピーダンスが所定の特性インピーダンスＺＯと一致するよう設計される。たとえばＺＯ＝５０Ωである。ドライバ２０の出力側には、第１スイッチＳＷ１が設けられる。第１スイッチＳＷ１はリレーなどの機械的なスイッチであってもよいし、トランスファゲートなどの電気的なスイッチであってもよい。 The driver 20 is provided in common to the input / output terminals P1 1 and P1 2 of the two DUTs 110 1 and 110 2 . The driver 20 outputs a test pattern to each of the input / output terminals P1 1 and P1 2 in a time division manner. The driver 20 outputs a voltage VIH corresponding to a high level when the test pattern is 1, and a voltage VIL corresponding to a low level when the test pattern is 0. The driver 20 is designed so that its output impedance matches a predetermined characteristic impedance ZO. For example, ZO = 50Ω. A first switch SW1 is provided on the output side of the driver 20. The first switch SW1 may be a mechanical switch such as a relay or an electrical switch such as a transfer gate.
　終端回路２２もまた、２つのＤＵＴ１１０１、１１０２それぞれの入出力端子Ｐ１１、Ｐ１２に対して共通に設けられる。終端回路２２の出力インピーダンスは所定値ＺＯ＝５０Ωと一致するように設計される。たとえば終端回路２２は、終端抵抗ＲＴと、バッファＢＵＦを含む。バッファＢＵＦは、終端抵抗ＲＴの一端の電位を所定値ＶＴ（たとえばＶＩＨとＶＩＬの中点）に固定する。終端抵抗ＲＴの他端には、第２スイッチＳＷ２が設けられる。 The termination circuit 22 is also provided in common to the input / output terminals P1 1 and P1 2 of the two DUTs 110 1 and 110 2 respectively. The output impedance of the termination circuit 22 is designed to coincide with a predetermined value ZO = 50Ω. For example, termination circuit 22 includes a termination resistor RT and a buffer BUF. The buffer BUF fixes the potential at one end of the termination resistor RT to a predetermined value VT (for example, the midpoint between VIH and VIL). A second switch SW2 is provided at the other end of the termination resistor RT.
　第１配線Ｌ１は、ドライバ２０の出力端子と第１ノードＮ１の間を接続する。第２配線Ｌ２は、終端回路２２と第２ノードＮ２の間を接続する。ソケットボード３４は、マザーボード３２に対して着脱可能に構成され、コネクタピンＰＣ１、ＰＣ２を介して接続される。図１において、第１ノードＮ１はコネクタピンＰＣ１に対応しているが、第１配線Ｌ１の一部がソケットボード３４上に敷設され、第１ノードＮ１がソケットボード３４上に設けられてもよい。 The first wiring L1 connects between the output terminal of the driver 20 and the first node N1. The second wiring L2 connects between the termination circuit 22 and the second node N2. The socket board 34 is configured to be detachable from the mother board 32, and is connected via connector pins PC1 and PC2. In FIG. 1, the first node N1 corresponds to the connector pin PC1, but a part of the first wiring L1 may be laid on the socket board 34 and the first node N1 may be provided on the socket board 34. .
　複数Ｎ本の第３配線Ｌ３１、Ｌ３２はそれぞれ、第１ノードＮ１と２つのＤＵＴ１１０１、１１０２それぞれの入出力端子Ｐ１１、Ｐ１２を結線する。つまり複数の第３配線Ｌ３１、Ｌ３２は、第１ノードＮ１から、複数の入出力端子Ｐ１１、Ｐ１２へと分岐して形成される。複数Ｎ本の第４配線Ｌ４１、Ｌ４２はそれぞれ、第２ノードＮ２と２つの１１０１、１１０２それぞれの入出力端子Ｐ１１、Ｐ１２を結線する。つまり複数の第４配線Ｌ４１、Ｌ４２は、コネクタピンＰＣ２を始点として、複数の入出力端子Ｐ１１、Ｐ１２へと分岐して形成される。なお、第２ノードＮ２はコネクタピンＰＣ２と一致しても構わない。 A plurality of N third wirings L3 1 and L3 2 respectively connect the first node N1 and the input / output terminals P1 1 and P12 of the two DUTs 110 1 and 110 2 respectively. That is, the plurality of third wirings L3 1 and L3 2 are formed to branch from the first node N1 to the plurality of input / output terminals P1 1 and P1 2 . The plurality of N fourth wirings L4 1 and L4 2 respectively connect the second node N2 and the two input / output terminals P1 1 and P1 2 of 110 1 and 110 2 . That plurality of fourth wirings L4 1, L4 2, as a starting point the connector pin PC2, are formed by branching into a plurality of input-output terminals P1 1, P1 2. The second node N2 may coincide with the connector pin PC2.
　以上が複数のＤＵＴ１１０およびドライバ２０、終端回路２２の結線態様である。さらに図１の試験装置１００は以下の特徴を有する。
　第１配線Ｌ１、第２配線Ｌ２は、それぞれ所定値５０Ωの特性インピーダンスＺＯを有する。一方、Ｎ本の第３配線Ｌ３１、Ｌ３２およびＮ本の第４配線Ｌ４１、Ｌ４２はそれぞれ、所定値５０ΩのＮ倍（２倍）の１００Ωの特性インピーダンスＺＯを有する。ここでの「Ｎ倍」とは厳密なＮ倍を意味するものではなく、インピーダンスの不整合が測定に影響しない範囲であれば、Ｎ倍からずれていても構わない。 The above is the connection mode of the plurality of DUTs 110, the driver 20, and the termination circuit 22. Furthermore, the test apparatus 100 of FIG. 1 has the following features.
The first wiring L1 and the second wiring L2 each have a characteristic impedance ZO of a predetermined value 50Ω. On the other hand, the N third wirings L3 1 and L3 2 and the N fourth wirings L4 1 and L4 2 each have a characteristic impedance ZO of 100Ω that is N times (two times) the predetermined value 50Ω. Here, “N times” does not mean exact N times, and may be deviated from N times as long as impedance mismatch does not affect the measurement.
　図１の試験装置１００によれば、終端回路２２から複数のＤＵＴ１１０側を覗いたインピーダンスを５０Ωに整合させることができる。さらに送端（ドライバ２０）側、受端（１１０）側の両端が終端されるため反射の影響を抑制できる。これらによって、高精度な試験が実現できる。 According to the test apparatus 100 of FIG. 1, the impedance viewed from the termination circuit 22 to the plurality of DUTs 110 can be matched with 50Ω. Furthermore, since both ends on the sending end (driver 20) side and receiving end (110) side are terminated, the influence of reflection can be suppressed. By these, a highly accurate test can be realized.
　好ましい形態において、Ｎ本の第３配線Ｌ３１、Ｌ３２は等長である。その結果、ドライバ２０から出力したテストパターンが一方の１１０１の入出力端子Ｐ１１に到達するまでの伝搬時間と、他方の１１０２の入出力端子Ｐ１２に到達するまでの伝搬時間を揃えることができる。その結果、ＤＵＴ１１０を、同じチャンネルのデータについては、複数のＤＵＴ１１０に対して共通のタイミングで動作させることができるため、ＤＵＴごとのタイミングの調整機能が、ＤＵＴ１１０側にも試験装置１００側にも不要となる。 In a preferred embodiment, the N third wirings L3 1 and L3 2 are of equal length. Consequently, to align the propagation time until the test pattern output from the driver 20 reaches the output terminal P1 1 of one 110 1, the propagation time to reach the output terminal P1 2 of the other 110 2 Can do. As a result, the DUT 110 can be operated at the same timing for a plurality of DUTs 110 for data of the same channel, so that a timing adjustment function for each DUT is not required on both the DUT 110 side and the test apparatus 100 side. It becomes.
　さらに試験装置１００は以下の特徴を有している。試験装置１００は、ピンエレクトロニクス３０、マザーボード３２、ソケットボード３４に分割されて構成される。ソケットボード３４には、複数のＤＵＴが直接または間接的に装着される。ピンエレクトロニクス３０は、複数チャンネルのドライバ２０および終端回路２２が集積化された半導体チップである。マザーボード３２は、ピンエレクトロニクス３０とソケットボード３４の間を接続する。 Furthermore, the test apparatus 100 has the following features. The test apparatus 100 is divided into a pin electronics 30, a mother board 32, and a socket board 34. A plurality of DUTs are directly or indirectly attached to the socket board 34. The pin electronics 30 is a semiconductor chip on which a multi-channel driver 20 and a termination circuit 22 are integrated. The mother board 32 connects between the pin electronics 30 and the socket board 34.
　第１配線Ｌ１、第２配線Ｌ２は、マザーボード３２上に敷設される。一方、第３配線Ｌ３、第４配線Ｌ４および第２配線Ｌ２の一部はソケットボード３４上に敷設される。つまり第１ノードＮ１、第２ノードＮ２は、マザーボード３２とソケットボード３４の境界上、もしくは、その境界よりもソケットボード３４側に配置される。この構成によれば、ＤＵＴ１１０のピン配置が変更となった場合であっても、ソケットボード３４のみを設計すればよく、ピンエレクトロニクス３０およびマザーボード３２に変更は不要となる。 The first wiring L1 and the second wiring L2 are laid on the mother board 32. On the other hand, a part of the third wiring L3, the fourth wiring L4, and the second wiring L2 is laid on the socket board 34. That is, the first node N1 and the second node N2 are arranged on the boundary between the mother board 32 and the socket board 34 or closer to the socket board 34 than the boundary. According to this configuration, even if the pin arrangement of the DUT 110 is changed, only the socket board 34 needs to be designed, and the pin electronics 30 and the mother board 32 need not be changed.
　以上が実施の形態に係る試験装置１００の構成である。試験装置１００の効果は、図２（ａ）、（ｂ）に示す比較技術との対比によってさらに明確となる。図２（ａ）の試験装置１００ｃは、終端回路２２を備えない。この構成では、第３配線Ｌ３１、Ｌ３２がともに１００Ωで設計される場合、理論上はインピーダンス整合がとれるため反射の影響は受けない。しかしながら、現実的には受端（ＤＵＴ）側がオープンであるため、２本の第３配線Ｌ３１、Ｌ３２の特性インピーダンスにわずかな差が存在すると、データ伝送が反射波の影響を受けやすくなる。特にＤＵＴ１１０１、１１０２で入力容量が相違したり、どちらかのＤＵＴが取り外された状態でバランスが崩れると、反射波の影響が大きくなってしまう。 The above is the configuration of the test apparatus 100 according to the embodiment. The effect of the test apparatus 100 is further clarified by comparison with the comparative technique shown in FIGS. 2 (a) and 2 (b). The test apparatus 100c in FIG. 2A does not include the termination circuit 22. In this configuration, when both the third wirings L3 1 and L3 2 are designed with 100Ω, the impedance matching is theoretically achieved, and therefore, there is no influence of reflection. However, since the receiving end (DUT) side is actually open, if there is a slight difference between the characteristic impedances of the two third wirings L3 1 and L3 2 , data transmission is easily affected by reflected waves. . In particular, if the input capacities of the DUTs 110 1 and 110 2 are different or the balance is lost when one of the DUTs is removed, the influence of the reflected wave becomes large.
　図２（ｂ）の試験装置１００ｄは、ＤＵＴ１１０１、１１０２の入出力端子Ｐ１１、Ｐ１２の間を接続する配線Ｌ５を備える。図２（ｂ）の構成では、送端側、受端側の両方が終端されており、分岐経路が存在しないため、反射の影響は受けにくい構成となっている。しかしながら、ドライバ２０から出力されたテストパターンがＤＵＴ１１０１、１１０２の入出力端子Ｐ１１、Ｐ１２に到達するまでの時間が異なるため、試験装置１００ｄの送信側で、ＤＵＴごとにタイミングを異ならせるか、あるいはＤＵＴ１１０１、１１０２からのデータを受けるタイミングコンパレータ（不図示）側で、ＤＵＴごとに異なるタイミングを設定する必要がある。 The test apparatus 100d in FIG. 2B includes a wiring L5 that connects between the input / output terminals P1 1 and P1 2 of the DUTs 110 1 and 110 2 . In the configuration of FIG. 2B, both the transmission end side and the reception end side are terminated, and there is no branch path, so that the configuration is not easily affected by reflection. However, since the time until the test pattern output from the driver 20 reaches the input / output terminals P1 1 and P1 2 of the DUTs 110 1 and 110 2 is different, the timing is different for each DUT on the transmission side of the test apparatus 100d. Alternatively, it is necessary to set a different timing for each DUT on the side of the timing comparator (not shown) that receives data from the DUTs 110 1 and 110 2 .
　図１の試験装置１００によれば、比較技術に係る試験装置１００ｃ、１００ｄに生ずる上述の問題を好適に解決できる。 1 can suitably solve the above-described problems occurring in the test apparatuses 100c and 100d according to the comparison technique.
　図３は、図１の試験装置１００の変形例を示すブロック図である。変形例に係る試験装置１００ａは、図１の試験装置１００と終端回路２２の位置が異なっている。終端回路２２は、マザーボード３２上に設けられている。 FIG. 3 is a block diagram showing a modification of the test apparatus 100 of FIG. The test apparatus 100a according to the modification is different from the test apparatus 100 of FIG. The termination circuit 22 is provided on the mother board 32.
　通常、ソケットボード３４に対する電源電圧Ｖｄｄは、電源３６からマザーボード３２を介して供給される。したがって、マザーボード３２は常に電源３６から電源電圧Ｖｄｄの供給を受けていることになる。終端回路２２のバッファＢＵＦをマザーボード３２に配置すると、基準電圧ＶＴの生成およびバッファＢＵＦの電源に、マザーボード３２を経由する電源電圧Ｖｄｄを利用できる。終端回路２２にはドライバ２０ほど高い精度が必要とされないため、構成が簡素化でき、したがって第２スイッチＳＷ２とともにマザーボード３２上に容易に配置できる。また、終端回路２２をマザーボード３２上に設ければ、図１の場合とくらべて、ピンエレクトロニクス３０とマザーボード３２を接続するための端子が不要となり、ピンエレクトロニクス３０の面積を削減できる。図１において終端回路２２に占有される領域を、ドライバ２０に割り当てることができるため、チャンネル数を増やすことが可能となる。 Normally, the power supply voltage Vdd for the socket board 34 is supplied from the power supply 36 via the mother board 32. Therefore, the mother board 32 is always supplied with the power supply voltage Vdd from the power supply 36. When the buffer BUF of the termination circuit 22 is arranged on the mother board 32, the power supply voltage Vdd passing through the mother board 32 can be used for generation of the reference voltage VT and power supply of the buffer BUF. Since the termination circuit 22 does not require as high accuracy as the driver 20, the configuration can be simplified, and therefore it can be easily arranged on the mother board 32 together with the second switch SW2. Further, if the termination circuit 22 is provided on the mother board 32, a terminal for connecting the pin electronics 30 and the mother board 32 is not required, and the area of the pin electronics 30 can be reduced as compared with the case of FIG. Since the area occupied by the termination circuit 22 in FIG. 1 can be allocated to the driver 20, the number of channels can be increased.
　実施の形態ではＮ＝２の場合を説明したが、本発明はＮ＝４など任意の数に拡張することができる。 Although the case where N = 2 has been described in the embodiment, the present invention can be extended to any number such as N = 4.
　実施の形態にもとづき本発明を説明したが、実施の形態は、本発明の原理、応用を示しているにすぎず、実施の形態には、請求の範囲に規定された本発明の思想を逸脱しない範囲において、多くの変形例や配置の変更が可能である。 Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.
　本発明のある態様によれば、複数の被試験デバイスを高精度で測定できる。 According to an aspect of the present invention, a plurality of devices under test can be measured with high accuracy.

Claims (8)

  1. 　それぞれが少なくともひとつの入出力端子を備えるＮ個（Ｎは２以上の整数）の被試験デバイスを試験する試験装置であって、
    　前記Ｎ個の被試験デバイスの前記入出力端子に対して共通に設けられたドライバと、
    　前記Ｎ個の被試験デバイスの前記入出力端子に対して共通に設けられた終端回路と、
    　前記ドライバの出力端子と第１ノードの間を接続する第１配線と、
    　前記終端回路と第２ノードの間を接続する第２配線と、
    　前記第１ノードと前記Ｎ個の被試験デバイスそれぞれの前記入出力端子を結線するＮ本の第３配線と、
    　前記第２ノードと前記Ｎ個の被試験デバイスそれぞれの前記入出力端子を結線するＮ本の第４配線と、
    　を備え、
    　前記第１、第２配線は所定値の特性インピーダンスを有し、前記Ｎ本の第３配線と前記Ｎ本の第４配線はそれぞれ、前記所定値のＮ倍の特性インピーダンスを有することを特徴とする試験装置。     A test apparatus for testing N devices (N is an integer of 2 or more) each having at least one input / output terminal,
    A common driver for the input / output terminals of the N devices under test;
    A termination circuit provided in common to the input / output terminals of the N devices under test;
    A first wiring connecting the output terminal of the driver and a first node;
    A second wiring connecting the termination circuit and the second node;
    N third wirings that connect the input / output terminals of the first node and the N devices under test,
    N fourth wirings for connecting the input / output terminals of the second node and the N devices under test,
    With
    The first and second wirings have a characteristic impedance of a predetermined value, and the N third wirings and the N fourth wirings each have a characteristic impedance N times the predetermined value. To test equipment.
  2. 　前記第１、第２配線は、前記ドライバが集積化される半導体チップと前記Ｎ個の被試験デバイスが直接または間接的に装着されるソケットボードとの間を接続するマザーボード上に敷設され、
    　前記第３、第４配線は、前記ソケットボード上に敷設されることを特徴とする請求項１に記載の試験装置。     The first and second wirings are laid on a motherboard connecting between a semiconductor chip on which the driver is integrated and a socket board on which the N devices under test are directly or indirectly mounted,
    The test apparatus according to claim 1, wherein the third and fourth wirings are laid on the socket board.
  3. 　前記終端回路は、前記マザーボード上に設けられることを特徴とする請求項２に記載の試験装置。 3. The test apparatus according to claim 2, wherein the termination circuit is provided on the motherboard.
  4. 　前記終端回路は、前記半導体チップに前記ドライバとともに集積化されることを特徴とする請求項２に記載の試験装置。 3. The test apparatus according to claim 2, wherein the termination circuit is integrated with the driver in the semiconductor chip.
  5. 　Ｎ＝２であり、前記特性インピーダンスの所定値は５０Ωであることを特徴とする請求項１または２に記載の試験装置。 3. The test apparatus according to claim 1, wherein N = 2 and the predetermined value of the characteristic impedance is 50Ω.
  6. 　前記Ｎ本の第３配線は等長であることを特徴とする請求項１から５のいずれかに記載の試験装置。 6. The test apparatus according to claim 1, wherein the N third wirings are of equal length.
  7. 　それぞれが少なくともひとつの入出力端子を備えるＮ個（Ｎは２以上の整数）の被試験デバイスが装着されるソケットボードであって、
    　前記ソケットボードがマザーボードに装着された状態において、前記Ｎ個の被試験デバイスの前記入出力端子に対して共通に設けられたドライバの出力端子と接続されるべき第１端子と、
    　前記ソケットボードがマザーボードに装着された状態において、前記Ｎ個の被試験デバイスの前記入出力端子に対して共通に設けられた終端回路と接続されるべき第２端子と、
    　前記第１端子と前記Ｎ個の被試験デバイスそれぞれの前記入出力端子を結線するＮ本の第３配線と、
    　前記第２端子を始点として前記Ｎ個の被試験デバイスそれぞれの前記入出力端子に分岐して到るＮ本の第４配線と、
    　を備え、
    　前記Ｎ本の第３配線と前記Ｎ本の第４配線はそれぞれ、同一の特性インピーダンスを有することを特徴とするソケットボード。     A socket board to which N devices (N is an integer of 2 or more) each having at least one input / output terminal are mounted,
    A first terminal to be connected to an output terminal of a driver provided in common to the input / output terminals of the N devices under test in a state where the socket board is mounted on a motherboard;
    A second terminal to be connected to a termination circuit provided in common to the input / output terminals of the N devices under test when the socket board is mounted on a motherboard;
    N third wirings for connecting the first terminal and the input / output terminals of each of the N devices under test;
    N fourth wirings that branch from the second terminal to the input / output terminals of each of the N devices under test,
    With
    The socket board, wherein the N third wirings and the N fourth wirings have the same characteristic impedance.
  8. 　前記Ｎ本の第３配線は等長であることを特徴とする請求項７に記載のソケットボード。 The socket board according to claim 7, wherein the N third wirings are of equal length.
PCT/JP2008/001772 2008-07-03 2008-07-03 Test device and socket board WO2010001440A1 (en)

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KR1020117001931A KR20110033846A (en) 2008-07-03 2008-07-03 Test device and socket board
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