KR101329594B1 - Calibration device - Google Patents

Abstract

A calibration device is provided for use with the Automatic Test Equipment (ATE). Such a calibration device includes a circuit having a fanout circuit. The companion-side fanout circuit has an input connected to the first channel of the ATE and an output connected to the N (N> 1) channels of the ATE, which N channels do not include the first channel. The ATE delivers the edge to the first channel, and the fanout circuit sends this edge to the N channels. Optionally, the calibration device for use with automated test equipment includes a drive-side circuit. This drive-side circuit includes a circuit having a number of inputs connected to the N (N> 1) channels of the ATE and an output connected to the second channel of the ATE rather than one of the N channels. The ATE delivers an edge to each of the N channels and this circuit delivers each edge to the second channel of the ATE.

Calibration Device, Automated Test Equipment, Fanout Circuit, Companion-Side, Drive-Side Circuit, Channel, Edge

Description

Calibration device {CALIBRATION DEVICE}

The present application generally relates to calibration devices for use with automated test equipment (ATE).

Automatic test equipment (ATE) relates to automated, typically computer-driven systems for testing devices such as semiconductors, electronic circuits and printed circuit board assemblies. The device tested by the ATE is called the device under test (DUT).

An ATE usually includes a computer system and a testing device or a single device with corresponding functionality. Pin electronics are usually part of a testing device. Pin electronics may include active load functionality for testing drivers, comparators, and / or DUTs. The driver provides a test signal on the pin of the testing device.

ATE can usually provide different types of signals in the DUT. An example of such a signal is the test signal described above, which test signal is used during testing of the DUT (eg, to test the DUT). Next-generation high-speed memory devices operate at data transfer rates of at least 6.4 gigabits per second (Gbps). Certain types of such devices, namely New Memory Technology (NMT) devices, require three to six device input or output lanes (channels) to share one delay adjustment circuit to conserve die area. As a result, testers for NMT devices often need to provide signals with precise inter-lane skew of less than +/- 25 ps (picoseconds) in the DUT. Currently useful calibration techniques use robots to probe in the DUT sockets, which are expensive due to robotic costs, maintenance costs and calibration time costs.

According to an embodiment, a calibration device is provided for use with the automatic test equipment (ATE). Such a calibration device includes a circuit having a fanout circuit. The fanout circuit has an input connected to the first channel of the ATE and an output connected to the N (N> 1) channels of the ATE, which N channels do not include the first channel. The ATE delivers the edge to the first channel, and the fanout circuit sends this edge to the N channels.

In yet another embodiment, the calibration device for use with automated test equipment includes a drive-side circuit. This drive-side circuit includes a circuit having a number of inputs connected to the N (N> 1) channels of the ATE and an output connected to the second channel of the ATE rather than one of the N channels. The ATE delivers an edge to each of the N channels and this circuit delivers each edge to the second channel of the ATE.

In yet another embodiment, the calibration device for use with automated test equipment includes a circuit having a fanout circuit. The fanout circuit has an input connected to the first channel of the ATE and an output connected to the M (M> 1) channels of the ATE, which M channels do not include the first channel, and the ATE is the first channel. Forward the edges, and the fanout circuit sends the edges to the M channels. The drive-side circuit includes a circuit having a number of inputs connected to N (N> 1) channels of the ATE and an output connected to a second channel of the ATE rather than one of the N channels, wherein the ATE comprises N channels Passing an edge to each of the circuits and passing each edge to a second channel of the ATE.

In another embodiment, the calibration method includes delivering an edge to the first channel of the signal source. Through the fanout circuit, this edge is transmitted to N channels, which fanout circuit has an input connected to the first channel and an output connected to N (N> 1) channels of the signal source, and N channels Does not include the first channel. Measurements corresponding to each edge of the N channels are obtained, wherein the difference in the measurement values between each edge of the N channels corresponds to inter-comparator skew.

In yet another embodiment, the calibration method includes delivering an edge to each of the N channels of the signal source. In addition, the step of passing each edge of the N channels is performed through a drive-side circuit having a plurality of inputs connected to the N (N > 1) channels of the signal source, thereby eliminating the signal source of one of the N channels. Runs on two channels. In addition, a measurement is obtained that corresponds to the time at which each edge of the N channels is received, with the difference in the measurement corresponding to driver-side skew.

In yet another embodiment, the calibration method provides for delivering a first edge to a first channel of a signal source. Through the fanout circuit, the first edge is transmitted on M channels. The fanout circuit has an input connected to the first channel and an output connected to M (M> 1) channels of the signal source, where the M channels do not include the first channel. A measurement value is obtained that corresponds to each first edge of the M channels, where the difference in the measurement value between each first edge of the M channels corresponds to inter-comparator skew. The second edge is delivered to each of the N channels of the signal source. In addition, the second edge may be connected to the first edge of the signal source other than one of the N channels, through a drive-side circuit having a plurality of inputs connected to the N (N> 1) channels of the signal source, in each of the N channels. 2 channels are delivered. A measurement is obtained that corresponds to the time at which each second edge of the N channels is received, with the difference in the measurement corresponding to drive-side skew.

In another embodiment, a computer program product has instructions executable using a data processing device. Such instructions include delivering an edge to a first channel of the signal source and transmitting this edge to the N channels through a fanout circuit. The fanout circuit has an input connected to the first channel and an output connected to N (N> 1) channels of the signal source, where the N channels do not include the first channel. Measurements corresponding to each edge of the N channels are obtained, wherein the difference in the measurement values between each edge of the N channels corresponds to inter-comparator skew.

In another embodiment, a computer program product has instructions executable using a data processing device. These instructions include forwarding an edge to each of the N channels of the signal source and drive-side each edge of the N channels with a plurality of inputs connected to the N (N> 1) channels of the signal source. Passing through the circuit to a second channel of a signal source that is not one of the N channels. A measurement is obtained that corresponds to the time at which each edge of the N channels is received, with the difference of the measurements corresponding to driver-side skew.

In another embodiment, a computer program has instructions executable using a data processing device. Such instructions include delivering a first edge to a first channel of the signal source. Through the fanout circuit, the first edge is transmitted on M channels. This fanout circuit has an input connected to the first channel and an output connected to M (M> 1) channels of the signal source, and the M channels do not include the first channel. A measurement value is obtained that corresponds to each first edge of the M channels, where the difference in the measurement value between each first edge of the M channels corresponds to inter-comparator skew. The second edge is delivered to each of the N channels of the signal source. In addition, the second edge may be connected to the first edge of the signal source other than one of the N channels, through a drive-side circuit having a plurality of inputs connected to the N (N> 1) channels of the signal source, in each of the N channels. 2 channels are delivered. A measurement is obtained that corresponds to the time at which each second edge of the N channels is received, with the difference in the measurement corresponding to drive-side skew.

1 is a block diagram of an ATE for testing a device;

2 is a block diagram of a tester used in ATE,

3 is a block diagram of a skew calibration device for use with an ATE;

4 is a block diagram of a signal routing chip in a skew calibration device for comparator interlane skew measurement, and

5 is a block diagram of an example signal routing chip for driver inter-lane skew measurements.

Like part numbers in different drawings represent like elements.

Various embodiments of the present invention aim to provide a more efficient and continuous calibration method, as well as greater inter-lane skew accuracy. In FIG. 1, a system for testing a device under test (DUT) 18, such as a semiconductor device, includes a tester, such as automated test equipment (ATE) or similar testing device. To control the tester 12, the system 10 includes a computer system 14 that interfaces with the tester 12 via a hardwired connection 16. Computer system 14 typically sends commands to tester 12 to initiate the execution of routines and functions for testing DUT 18. This execution test routine may initiate the generation of a test signal and transmission to the DUT 18 and collect a response from the DUT 18. Various types of DUTs can be tested by the system 10. For example, the DUT may be a semiconductor device such as an integrated circuit (IC) chip (eg, memory chip, microprocessor, analog-to-digital converter, digital-to-analog converter, etc.).

To provide a test signal and collect a response from the DUT, the tester 12 is connected to one or more connector pins that provide an interface for the internal circuitry of the DUT 18. To test some DUTs, for example, 64 or 128 connector pins, or more, may be interfaced to the tester. For illustrative purposes, in this example, the semiconductor device tester 12 is connected to one connector pin of the DUT 18 via a hardwire connection. Conductor 20 (eg, cable) is connected to pin 22 and used to deliver test signals (eg, PMU test signals, PE test signals, etc.) to the internal circuitry of DUT 18. Conductor 20 also detects a signal at pin 22 in response to a test signal provided by semiconductor device tester 12. For example, a voltage signal or current signal is detected at pin 22 in response to the test signal and sent to tester 12 for analysis via conductor 20.

This single port test can be executed on other pins included in the DUT 18. For example, tester 12 may provide a test signal to another pin and collect the reflected signal reflected back through the conductor, such as delivering the provided signal. By collecting the reflected signal, the input impedance of the pin can be characterized according to other single port testing amounts. In another test scenario, the digital signal may be sent to pin 22 through conductor 20 to store the digital signal in DUT 18. Once the digital values are stored, the DUT 18 can be accessed via conductor 20 or another conductor to retrieve and transmit the stored digital values. The retrieved digital value can then be identified to determine if a suitable value has been stored in the DUT 18.

In addition to the one-port measurement, the two-port test can also be executed by the semiconductor device tester 12. For example, a test signal can be injected into pin 22 through conductor 20 and a response signal can be collected from one, two or more other pins of DUT 18. This response signal may be provided to the semiconductor device tester 12 to determine quantities such as, for example, gain response, phase response, and other processing measurements.

In FIG. 2, the semiconductor device tester 12 includes an interface card 24 that can communicate with multiple pins to transmit and collect test signals from multiple connector pins of one DUT (or multiple DUTs). do. For example, interface card 24 may send a test signal, for example, to 32, 64, or 128 pins and collect a corresponding response. Each communication link to the pin is commonly referred to as a channel, and by providing a test signal over a vast number of channels, test time can be reduced because multiple tests can be run simultaneously. The output channel usually includes a driver (not shown) to provide a signal to the DUT, and the input channel usually includes a comparator (also for receiving input signals, comparing them with a reference value, and providing an output, for example). Not shown). As having many channels in the interface card by the same step as including a plurality of interface cards in the tester 12, the total number of channels increases, and thus the testing time is further reduced. In this example, two additional interface cards 26 and 28 are shown to demonstrate that a number of interface cards are populating the tester 12.

In some embodiments, each interface card may include a dedicated integrated circuit (IC) chip (eg, an application specific integrated circuit (ASIC)) to perform a particular test function. For example, the interface card 24 includes an IC chip 30 for executing a parameter measurement unit (PMU) test and a pin electronics (PE) test. IC chip 30 has a PE stage 34 that includes a circuit for executing a PMU test and a circuit for executing a PE test. The interface cards 26 and 28 also include IC chips 36 and 38, which each include PMU and PE circuits. Usually, PMU testing includes providing a DC voltage or current signal to the DUT to determine quantities such as input and output impedances, current leakage values, and other types of DC performance characteristics. PE testing includes sending an AC test signal or waveform to a DUT (eg, DUT 18) and collecting a response to further characterize the performance of the DUT. For example, IC chip 30 may send an AC test signal (to the DUT) indicating a vector of binary values for storage in the DUT. Once this binary value has been stored, the DUT may be accessed by tester 12 to determine if the correct binary value has been stored. Since digital signals usually include steep voltage transitions, the circuitry in the PE stage 34 of the IC chip 30 can operate at a relatively high speed compared to the circuitry in the PMU 32.

In order to pass both DC and AC test signals from the interface card 24 to the DUT 18, the conductive trace 40 passes through the IC chip 30, with the signals on and off relative to the interface board 24. To the interface board connector 42, which allows it to be connected. The interface board connector 42 is also connected to a conductor 44 connected to the interface connector 46 that allows signals to pass into and out of the tester 12. In this example, conductor 20 is connected to interface connector 46 for a bidirectional signal path between DUT 18 pin 22 and tester 12. In some arrangements, the interface device may be used to connect one or more conductors from tester 12 to the DUT. For example, a DUT (eg, DUT 18) may be mounted to the device interface board (DIB) to provide access to each DUT pin. In this arrangement, conductor 20 may be connected to the DIB to place a test signal on a suitable pin (eg, pin 22) of the DUT.

In this example, only conductive trace 40 and conductor 44 are connected to IC chip 30 and interface board 24, respectively, for the transmission and collection of signals. However, IC chip 30 (along with IC chips 36 and 38) typically has a plurality of pins connected to a plurality of conductive traces and corresponding conductors, respectively, for providing and collecting signals from the DUT (via the DIB). (For example, 8, 16, etc.). Further, in some arrangements, tester 12 may be connected to two or more DIBs for interfacing the channels provided by interface cards 24, 26, 28 to one or multiple devices under test.

In order to initiate and control the testing performed by the interface cards 24, 26 and 28, the tester 12 generates test signals and test parameters (e.g., test signal voltage levels, tests for analyzing the DUT response). Signal current level, digital value, etc.) and a PMU control circuit 48 and a PE control circuit 50. The PMU control circuit and the PE control circuit can be implemented using one or more processing devices. Examples of processing devices include, but are not limited to, microprocessors, microcontrollers, programmable logic (eg, field-programmable gate arrays), and / or combinations thereof. The tester 12 also allows the computer system 14 to control the operations performed by the tester 12 and data (eg, test parameters, DUT response, etc.) may be present between the tester 12 and the computer system 14. And a computer interface 52 for passing through.

For example, a calibration device that can interface with an ATE tester by being injected into a DUT socket on a DIB is described below. Once in the socket, the calibration device can communicate with the tester to enable cross lane skew measurements and continuous calibration by the tester by the tester, thereby allowing eg, +/- 25 ps or better calibration in the group of lanes. You can get skewed lanes. In such an embodiment, the lane may be, for example, a tester communication path used for communication to the DUT, for example. The number of lanes in the group of lanes to be calibrated can be customized to the DUT needs. A group of six lanes is used for the example below.

One embodiment of a calibration device is shown in FIG. 3. The calibration device of FIG. 3 is a printed circuit board (PCB) comprising one or more high precision signal routing devices (chips in this embodiment), which may be custom or commercially available, and traces to route the input and output signals of the calibration device to a suitable routing chip. It includes. The PCB substrate can have the same form factor as the device (DUT), so that it can contact the DUT socket (eg, on a tester) in the same way as the DUT.

In this embodiment, there are two types of signal routing techniques in each calibration device, namely, compar- side skew measurements and drive-side skew measurements. An embodiment for the companion-side skew is shown in FIG. 4. In this embodiment, the input Q6 of the high precision clock fanout chip is connected to a tester channel (e.g., ch 6) that is not part of the channel group (e.g., ch 0 -ch 5) being calibrated. The output of clock fanout chips Q0-Q5 is connected to channel groups ch0-ch5 through traces on the PCB substrate. These trace lengths can be well matched to be within 5 mils (0.5% of one inch). Calibration is performed by creating an edge in input lane ch6 that is fanned out to a group of channels through a calibration device and measured by a comparator for each tester channel. The difference in measured values represents skew between the comparator lanes and can be compensated by the tester by adjusting the appropriate calibration delay in each comparator.

In FIG. 5, a precision logic OR gate or multiplexer is used to connect a group of channels (e.g., Q8-Q13) to one input (e.g., Q14) in an embodiment for dry-side skew measurements. . According to an embodiment, all channels in a group of channels, one by one, are programmed identically (or at least substantially identically) via a calibration device to an output Q14 connected to the tester channel ch14 outside of this group of channels. Transfer the edge. This channel comparator measures the edge time of all channels in the input group, and the difference in the measured value (eg, the difference in the received edge time) reveals the skew of the driver output. This skew can be compensated by the tester by adjusting the appropriate delay (eg driver timing) of each drive channel.

Such a calibration device enables parallel calibration processes for multiple device test sites that only take less than a few minutes to achieve inter-lane accuracy of, for example, + / 25 ps (or less), resulting in at least some conventional Will be superior to the robot.

ATE and calibration devices are not limited to the hardware and software described above. The ATE and / or calibration device, or any portion thereof, is for execution by one or more data processing devices, such as, for example, programmable processors, computers, multiple computers, and / or programmable logic elements, or of such data processing devices. It may be implemented at least in part via a computer program product, ie a computer program, of a type embodied in an information carrier, such as a signal or one or more machine-readable media transmitted to control operation.

A computer program may be written in any programming language, including compiled or interpreted language, and in any form including a stand-alone program or module, component, subroutine, or other unit suitable for use in a computing environment. Can be configured. The computer program may be interconnected by a network and distributed across multiple sites or configured to run on multiple computers or on one computer at one site.

Actions associated with implementing calibration and / or testing may be executed by one or more programmable processors executing one or more computer programs to execute functions of the calibration process. All or part of the ATE and / or calibration device may be implemented as dedicated logic circuitry. Examples may include, but are not limited to, field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs).

Processors suitable for the execution of computer programs include, for example, general and special purpose microprocessors and one or more processors of any kind of digital computer. In general, a processor will receive instructions and data from a ROM or RAM or both. Elements of a computer include a processor for executing instructions and one or more memory devices for storing instructions and data.

Elements of the different embodiments described herein may be combined to constitute other embodiments that are not specifically described above. It is included within the scope of the following claims or other embodiments not specifically described herein.

Claims (23)

Calibration device for use with automated test equipment (ATE), A circuit including a fanout circuit having an input connected to the first channel of the ATE and an output connected to the N (N> 1) channels of the ATE, The N channels do not include the first channel, The ATE delivers an edge to the first channel, and the fanout circuit transmits the edge to the N channels. The calibration device of claim 1; And A comparator corresponding to each of the N channels; Wherein each of the comparators obtains a measurement value corresponding to each edge, and the difference in the measurement value of each edge corresponds to skew between the comparator lanes. 3. The method of claim 2, And circuitry for making adjustments to compensate for the interlane skew, wherein the adjustments affect timing associated with the comparator. 3. The automated test equipment (ATE) of claim 2, wherein the fanout circuit output is connected to a channel of the ATE via a trace on a printed circuit board whose lengths match each other. Calibration device for use with automated test equipment (ATE), A drive-side circuit comprising a circuit having a plurality of inputs connected to N (N> 1) channels of the ATE and an output connected to a second channel of the ATE that is not one of the N channels, The ATE delivers an edge to each of the N channels and the circuit delivers each edge to a second channel of the ATE. 6. The calibration device of claim 5, wherein said circuit comprises an OR gate. 6. The calibration device of claim 5, wherein said circuit comprises a multiplexer. As an automatic test equipment (ATE), The calibration device of claim 5; And A comparator corresponding to the second channel; The comparator obtains a measurement value corresponding to the time at which the edges of the N channels were received, and the difference in the measurement value corresponds to driver-side skew. 9. The automatic test rig of claim 8, further comprising circuitry that performs adjustments to compensate for the driver-side skew, wherein the adjustments affect timing associated with drivers corresponding to the N channels. (ATE). Calibration device for use with automated test equipment (ATE), A circuit comprising a fanout circuit having an input connected to a first channel of the ATE and an output connected to M (M> 1) channels of the ATE, wherein the M channels do not include the first channel, The ATE transfers an edge to the first channel, and the fanout circuit transfers the edge to the M channels; And Circuitry having a plurality of inputs connected to N (N> 1) channels of the ATE and an output connected to a second channel of the ATE rather than one of the N channels, wherein the ATE is connected to each of the N channels. And drive-side circuitry for delivering edges and for delivering each edge to a second channel of the ATE. Delivering an edge to a first channel of a signal source; An input connected to the first channel and an output connected to the N (N> 1) channels of the signal source, wherein the N channels are connected to the N channels through a fanout circuit that does not include the first channel. Transmitting; Obtaining a measurement value corresponding to each edge of the N channels; And the difference in measurement between each edge of the N channels corresponds to inter-lane comparators skew. 12. The method of claim 11, After obtaining a measurement corresponding to each edge of the N channels, An adjustment step of compensating for the inter-lane skew, wherein the adjustment affects timing associated with a plurality of comparators associated with each of the N channels. 12. The method of claim 11, wherein in transmitting said edge, said signal source is an automatic test equipment. Delivering an edge to each of the N channels of the signal source; A second channel of a signal source other than one of the N channels, through a drive-side circuit having a plurality of inputs connected at each edge of the N channels to N (N> 1) channels of the signal source Delivering to; And Obtaining a measurement value corresponding to the time at which each edge of the N channels is received; And the difference in the measured values corresponds to driver-side skew. The method of claim 14, After obtaining a measurement value corresponding to the time at which each edge of the N channels is received, And adjusting to compensate for the driver-side skew by adjusting each delay of the N channels. 15. The method of claim 14, wherein in transmitting an edge to each of the N channels of the signal source, the signal source is an automatic test equipment. 15. The method of claim 14, wherein in delivering said each edge of said N channels, said drive-side circuit comprises an OR gate. 15. The method of claim 14, wherein in delivering said each edge of said N channels, said drive-side circuit comprises a multiplexer. Delivering a first edge to a first channel of the signal source; Transmitting the first edge to M channels through a fanout circuit having an input connected to a first channel and an output connected to M (M> 1) channels of a signal source; Obtaining a measurement value corresponding to each first edge of the M channels; Passing a second edge to each of the N channels of the signal source; The second edge of each of the N channels through a drive-side circuit having a plurality of inputs connected to N (N > 1) channels of the signal source; Delivering to two channels; And Obtaining a measurement value corresponding to the time at which each second edge of the N channels is received; The M channels do not include a first channel, and the difference in the measured value between each first edge of the M channels corresponds to inter-comparator skew, where each second edge of the N channels is received. And wherein the difference in measurement corresponding to time corresponds to driver-side skew. 20. The method of claim 19, wherein said signal source is an automatic test equipment. A storage medium having stored thereon a computer program having instructions executable using a data processing device, the instructions comprising: Delivering an edge to a first channel of a signal source; The N channel has an input connected to the first channel and an output connected to N (N> 1) channels of a signal source, and the N channels pass the edge through the fanout circuit not including the first channel. Transmitting to a channel; And Obtaining a measurement value corresponding to each edge of the N channels; And wherein the difference in measurement between each edge of said N channels corresponds to inter-lane comparators skew. A storage medium having stored thereon a computer program having instructions executable using a data processing device, the instructions comprising: Delivering an edge to each of the N channels of the signal source; Each of the N channels through a drive-side circuit having a plurality of inputs connected to a second channel of the signal source other than one of the N channels, connected to the N (N> 1) channels of the signal source Passing an edge of the; And Obtaining a measurement value corresponding to the time at which each edge of the N channels is received; And the difference in the measured values corresponds to a driver-side skew. A storage medium having stored thereon a computer program having instructions executable using a data processing device, the instructions comprising: Delivering a first edge to a first channel of the signal source; The first edge through a fanout circuit having an input connected to the first channel and an output connected to M (M> 1) channels of a signal source, wherein the M channels do not include the first channel Transmitting M to M channels; Obtaining a measurement corresponding to each first edge of the M channels; Delivering a second edge to each of the N channels of the signal source; A second of a signal source other than one of the N channels, through a drive-side circuit having a plurality of inputs connected to each of the N (N> 1) channels of the signal source, each second edge of the N channels. Delivering to a channel; And Obtaining a measurement value corresponding to the time at which each second edge of the N channels is received; The difference in the measured value between each first edge of the M channels corresponds to inter-lane comparator skew, And the difference in the measurement value corresponding to the time at which each second edge of the N channels is received corresponds to a driver-side skew.

Images