JP2002082148A - Method and apparatus for correction of timing of semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a judgment-system deskewing operation and an application- system deskewing operation, at the same frequency as the actual measured frequency. SOLUTION: Signal waveforms are output to a short-circuit jig 2 from drivers 23 to 2n-1, at pins other than an a first tester pin as an object to be acquired. On the basis of their composited waveform, the delay amount of a variable delay means 26 for a comparator, at a second tester pin is increased or decreased. The timing correction of a strobe signal supplied to a comparator 82 is made. When the timing correction with reference to all of the comparator 82 and comparators 84 to 8n is finished, the short-circuit jig 2 is removed. In a state with the output end of the tester pin opened, signal waves are output from all drivers 21, 23 to 2n-1. While the timing-corrected strobe signal is used as reference delay amounts of variable delay means 51, 53 to 5n-1 for the respective drivers, at the first tester pin are increased or decreased. The timing correction of signal waveforms supplied to the comparators 62, 64 to 6n is made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for correcting the timing of various test signals of a semiconductor test apparatus.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor test apparatus or the like, one disclosed in Japanese Patent Application Laid-Open No. 4-127073 is known as a device for correcting the timing of a signal supplied to a driver or a comparator. FIG. 1 shows an outline of this prior art. In this prior art, a dedicated IC (short jig) 2 in which each signal pin is short-circuited is replaced with a semiconductor test apparatus (IC) in place of a device to be measured such as an IC memory.
Tester) 3. The control circuit 10 operates the timing generator 11. The timing generator 11 applies all the outputs of the drivers 21 to 2n of the tester pins other than the correction target pin to the short jig 2. For example, when the correction target pin is a pin including the driver 21, a signal is applied to the short jig 2 from the other tester pin drivers 22 to 2 n. These signals have a single combined waveform combined at the short end of the short jig 2. The control circuit 10 corrects the timing of the strobe signal supplied to the comparators 31 and 41 of the tester pins by increasing and decreasing the delay amount of the variable delay circuit for comparator 61 based on the composite waveform. The timing correction process described above is performed on the comparators 31 to 3n and 41 to 4n of all the tester pins while sequentially switching the correction target pins.

When the timing correction is completed, the output end of the tester pin is opened or the short jig 2
The control circuit 10 increases and decreases the delay amount of the driver variable delay circuits 51 to 5n based on the timing of the comparators 31 to 3n and 41 to 4n of each tester pin, and applies the delay amounts to the drivers 21 to 2n. The timing of the signal to be corrected is corrected. The above-mentioned comparators 31 to 3n, 4
The timing correction for 1 to 4n is called a determination system deskew, and the timing correction for the drivers 21 to 2n is called an application deskew. Conventionally, the application system deskew has been performed after the determination system deskew has been performed.

[0004]

In the above-described application system deskew, the output waveforms output from the drivers 21 to 2n reach the output end of the tester pin or the shoot end of the short jig 2 via one signal line. Then, each of the comparators 31 to 3n and 41 to 4n detects the reflected waveform that has been reflected there and returned via the same signal line. Therefore, the comparators 31 to 3n, 41 to 41
In 4n, the application system deskew is performed on the reflection waveform including the path length from the reflection point to the drivers 21 to 2n. Therefore, conventionally, the path length is set to TDR
(Time Domain Reflectometry
r), and the timing edge is temporally corrected based on the path length.

However, recently, a direct rambus D
Measurement frequency 50 such as RAM (D-RDRAM)
The need to measure high-speed memories such as 0 [MHz] and data rate 1 [GHz] has increased. In order to measure such a high-speed memory, it is important to correct timing in a high-speed frequency band, and the timing accuracy thereof is required to be as high as ± 50 [ps]. Also,
Measurement frequency of 100 [MHz] and 500
Since the frequency characteristics (propagation characteristics) and impedance characteristics of the signal line are significantly different from the measurement frequency of [MHz], it is preferable to perform deskew in the frequency band actually measured. However, since the TDR measures the path length using the reflected waveform, the measurement frequency is 500 [MHz].
At such a high speed, it was very difficult to measure the path length without distinguishing between the reflected waveform and the output waveform. Therefore, it is practically impossible to perform deskew at a measurement frequency of 500 [MHz] in the past.
The result of the deskew performed at [MHz] has been applied to the case of a measurement frequency of 500 [MHz] as it is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has a timing correction method and apparatus for a semiconductor test apparatus capable of performing a judgment system deskew and an application system deskew at the same frequency as the actual measurement frequency. The purpose is to provide.

[0007]

According to a first aspect of the present invention, there is provided a timing correction method for a semiconductor test apparatus, comprising: a first group of tester pins having at least drive means; and a second group of tester pins having at least comparator means. Connecting to the signal pins of the short jig via signal lines, respectively, and driving the first tester pins other than the first tester pins for which the determination system deskew is to be obtained in the first tester pin group. Means for outputting a signal waveform to the short jig, and connecting the signal line to a first tester pin, which is a target for determination system deskew acquisition, based on a single synthesized waveform synthesized at the short end of the short jig. The delay amount of the variable delay means for the comparator of the second tester pin connected via Performing a determination system deskew by performing a timing correction of the supplied strobe signal; and, in a state where the timing correction is completed for all the first and second tester pins and the short jig is removed, A signal waveform is output from all the drive means of the first tester pin group, and the delay amount of each driver variable delay means of the first tester pin is increased / decreased based on the timing-corrected strobe signal. Performing the timing of the signal waveform supplied to the comparator means of the second tester pin connected to the first tester pin via the signal line, thereby performing the application system deskew. It is a thing.

A tester pin of an ordinary semiconductor test device has a drive unit and a comparator unit, and these are connected to an I / O.
Switched and used by switch. In the present invention, the first tester pin has at least drive means,
It is sufficient that the tester pin group has at least comparator means. Therefore, the first and second tester pins may have drive means and comparator means like normal tester pins, or the first tester pin may be a drive-only pin and the second tester pin may be a comparator-only pin. There may be. In a semiconductor test apparatus having such a tester pin, a conventionally known short jig is mounted, and first and second test pins are connected to each signal pin of the short jig. Connect through. That is, the drive means and the comparator means are connected to the respective signal pins of the short jig via separate signal lines. The control means outputs the signal waveform to the shorting jig from the driver means of the first tester pin other than the first tester pin for which the determination system deskew is to be obtained, as in the related art. Then, these signals become a single synthesized waveform synthesized at the short end of the short jig. The control means increases or decreases the amount of delay of the comparator variable delay means of the second tester pin connected via a signal line to the first tester pin from which the determination system deskew is to be obtained, based on the synthesized waveform. Then, the timing of the strobe signal supplied to the comparator means of the second tester pin is corrected. This timing correction processing is performed by the first and second acquisition targets of the determination system deskew.
Is performed for all the comparator means of the second tester pins while sequentially switching the test pins. After this timing correction is completed, the short jig is removed, and the output end of the tester pin is opened. Since the drive means and the comparator means are connected to the respective signal pins of the short jig via separate signal lines, even when the short jig is removed, the drive means and the comparator means have different signal pins. It remains connected through the wire. Therefore, a signal waveform is output from all the driving means of the first tester pin group, and the delay amount of each driver variable delay means of the first tester pin is increased and decreased with reference to the timing-corrected strobe signal. The application system deskew is performed by correcting the timing of the signal waveform supplied to the comparator means of the second tester pin connected to one tester pin via a signal line. As described above, since the application-system deskew returns the driver output directly to the comparator via the different signal lines, the timing of the application-system deskew is corrected in a form including the path length from the driver to the device end. Since the path length can be measured, it is not necessary to measure the path length in advance, and even when the measurement frequency is as high as about 500 [MHz], the timing can be easily corrected at the same frequency.

According to a second aspect of the present invention, there is provided a timing correction method for a semiconductor test apparatus according to the first aspect, wherein the determination system deskew is further executed after the application system deskew is completed. . This is because the rise of the synthesized waveform synthesized at the short end of the short jig becomes steep by performing the judgment system deskew and the application system deskew, and the same judgment system deskew is performed again based on the steep synthesized waveform. By doing so, the accuracy of deskew is improved.

According to a third aspect of the present invention, in the method of correcting a timing of a semiconductor test apparatus according to the first aspect of the present invention, the first tester pin and the second tester pin may include a driver variable delay unit, a driver unit, It comprises a variable delay means for a comparator and a comparator means. This is limited to the case where the first and second tester pins have a drive unit and a comparator unit like a normal tester pin.

According to a fourth aspect of the present invention, there is provided a timing correction apparatus for a semiconductor test apparatus, comprising: a first tester pin group having at least drive means; a second tester pin group having at least comparator means; And a short jig in which each of these signal pins is connected to the first tester pin and the second tester pin via a signal line, respectively. A signal waveform is output from the driving means of the first tester pin other than the first tester pin for which the determination system deskew is to be acquired in one tester pin group to the short jig, and the signal waveform is synthesized at the short end of the short jig. With reference to a single synthesized waveform, the signal is connected to the first tester pin from which the determination system deskew is to be obtained via the signal line. Decision system deskew is performed by increasing or decreasing the delay amount of the comparator variable delay means of the second tester pin and correcting the timing of the strobe signal supplied to the comparator means. And the second tester pin is terminated, and in a state where the short jig is removed, a signal waveform is output from all the driving means of the first tester pin group, and the timing corrected strobe signal is used as a reference. The delay amount of the variable delay means for each driver of the plurality of first tester pins is increased / decreased and the second tester pin is connected to the first tester pin via the signal line.
And control means for performing application system deskew by performing timing correction of the signal waveform supplied to the comparator means of the tester pin.
This is an invention relating to a device for realizing the method of correcting a timing of a semiconductor test device of the first aspect, and the operation thereof is the same as that of the first aspect.

According to a fifth aspect of the present invention, in the semiconductor device tester according to the fourth aspect of the present invention, the control means may further execute the determination system deskew after the application system deskew is completed. It was made. This corresponds to claim 2.

According to a sixth aspect of the present invention, in the semiconductor device tester according to the fourth aspect of the present invention, the first tester pin and the second tester pin may include a driver variable delay unit, a driver unit, It comprises a variable delay means for a comparator and a comparator means. This corresponds to claim 3.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the accompanying drawings. FIG. 2 shows an example of the timing correction device of the semiconductor test device of the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals.

A semiconductor test apparatus 1 according to this embodiment
Is composed of a control circuit 10, a timing generator 11, variable delay circuits 51 to 5n, 61 to 6n, drivers 21 to 2n, comparators 81 to 8n, and I / O switches 71 to 7n. Here, n is an even number. Although an actual semiconductor test apparatus has other components such as a pattern generator, a pin control circuit, and a fail bit memory (not shown), it is necessary in this specification to understand the features of the present invention. Only parts are shown. Note that the comparator 8
1 to 8n are high-level comparators 31 to 3 in FIG.
n and the low-level comparators 41 to 4n are collectively shown. When the comparator 81 is hereinafter referred to in the present specification, both the high-level comparator 31 and the low-level comparator 41 are indicated. I do.

The control circuit 10 performs overall control, operation and management of the semiconductor test apparatus 1, and has a microprocessor configuration. Therefore, although not shown,
The control circuit 10 includes a ROM for storing a system program, a RAM for storing various data, and the like.
The control circuit 10 outputs various control signals and data to each component.

The timing generator 11 outputs a high-speed operation clock to a pattern generator (not shown), a pin control circuit, a fail bit memory, etc., based on the timing data stored in its internal memory, and outputs the clock to the device under test. It controls data write timing and read timing.

The timing correction apparatus according to this embodiment adjusts the timing at which the signal output from the timing generator 11 is input to each of the drivers 21 to 2n and the comparators 81 to 8n. Short jig 2
Instead of a device under test such as an IC memory, each signal pin is constituted by a dedicated IC in which the signal pins are short-circuited. The short jig 2 is connected to each tester pin of the semiconductor test device 10. Odd-numbered tester pins and even-numbered tester pins are connected to respective signal pins of the short jig 2 via separate signal lines. This connection relationship is maintained even when the short jig 2 is removed. That is, the first and second tester pins are connected to the uppermost signal pin of the short jig 2 via different signal lines, and the third and fourth tester pins are connected to the different signal lines to the next signal pin. In the same manner, odd-numbered tester pins and even-numbered tester pins are connected to the respective signal pins via separate signal lines, and the n-1th and n-th tester pins are connected to the lowermost signal pin. Are connected via separate signal lines.

In FIG. 2, the first tester pin includes a driver 21, a comparator 81, a driver variable delay circuit 51, and a comparator variable delay circuit 61. Similarly, the second to n-th tester pins have drivers 22 to 2n, comparators 82 to 8n, driver variable delay circuits 52 to 5n, and comparator variable delay circuits 62.
To 6n. It should be noted that in FIG.
The illustration of the tester pins from (n) to (n-1) is omitted.

Normally, between each tester pin and the short jig 2 is an interface board composed of a plurality of (n) coaxial cables or the like corresponding to the total number of input / output terminals (n) of the semiconductor mounting device. The connections are made, and the connection relationship is associated with each other by a relay matrix (not shown), so that transmission of various signals is performed between a predetermined terminal and a coaxial cable. Therefore, as shown in FIG. 1, the conventional interface board is configured such that all the signal lines connect each tester pin and each terminal of the short jig 1 on a one-to-one basis. However,
In this embodiment, the interface board is configured such that one terminal of the short jig 2 is connected to two tester pins. That is, as shown in FIG. 1, when each tester pin and the short jig 2 are connected in a one-to-one manner, a semiconductor test apparatus capable of simultaneously measuring 64 memories is used. By making the connection relationship, the number of memories that can be measured at the same time is reduced to half, that is, 32. That is, in this embodiment, the deskew at a high frequency is accurately performed at the expense of about half of all tester pins.

The following describes how the timing correction device of this embodiment performs deskew at a high frequency. First, the operation of the determination system deskew will be described. The timing generator 11 outputs signals from all drivers other than the determination system deskew acquisition target in a state where the timing of the application system is not corrected. Driver 2 whose judgment system deskew acquisition target is the first tester pin
In the case of 1, the control circuit 10 controls the drivers 23, 25, 27 to 2n− of the odd-numbered tester pins other than the driver 21.
1 so as to output a signal waveform. These signal waveforms become a single combined waveform combined at the short end of the short jig 2. Using this synthesized waveform as a reference clock, the control circuit 10
, The timing of the strobe signal supplied to the comparator 82 of the second tester pin is corrected, and the determination system deskew is performed.

Next, when the determination system deskew acquisition target is the driver 23 of the third tester pin, the control circuit 10
Control is performed so that signal waveforms are output from the drivers 21, 25 to 2n-1 of the odd-numbered tester pins other than the driver 23. Using the composite waveform of these signal waveforms as a reference clock, the control circuit 10
The delay amount of No. 4 is increased or decreased, the timing of the strobe signal supplied to the comparator 84 of the fourth tester pin is corrected, and the determination system deskew is performed. Hereinafter, similarly, the control circuit 10 executes the judgment-related deskew while sequentially switching the correction target pins also for the drivers 25, 27 to 2n-1 of the odd-numbered tester pins.

Next, the operation of the application deskew will be described. When the above-described determination system deskew is completed, the control circuit 10 performs the application system deskew using the timing strobe corrected by the determination system deskew as a reference clock. When the short jig 2 is removed, the control circuit 10 controls the drivers 21, 23, 2 of the odd-numbered tester pins.
5-2n-1 so as to output a signal waveform, and the signal waveform is output to the comparator 8 of each even-numbered tester pin.
2, 84 to 8n, and based on that, the delay amount of each of the odd-numbered variable delay circuits 51, 53 to 5n-1 is increased or decreased, and the application system deskew is executed.

When the above-described application system deskew is completed, the control circuit 10 performs the determination system deskew again in the same manner. This is because the determination system deskew and the application system deskew are performed, so that the rising of the synthesized waveform synthesized at the short end of the short jig 2 becomes steep. This is because the accuracy of the deskew can be improved by executing the same determination system deskew again based on the steep synthesized waveform.

As described above, according to the timing correction apparatus of this embodiment, since the application system deskew returns the driver output directly to the comparator via separate signal lines, the driver performs device deskew. Since the timing correction of the application system deskew can be performed in a form including the path length up to the path length, there is no need to measure this path length in advance. Therefore, even when the measurement frequency is as high as about 500 [MHz], the timing can be corrected at the same frequency.

In the above-described embodiment, the variable delay circuits 61 and 63 for the comparators of the odd-numbered tester pins are used.
-6n-1, comparators 81, 83-8n, and driver variable delay circuits 52, 5 for even-numbered tester pins.
4 to 5n and the drivers 22, 24 to 2n are not used and may be omitted. However, in this case, the interface board cannot be replaced with the one shown in FIG. Therefore, although seemingly useless, the configuration shown in FIG. 2 makes it possible to support memories of all speeds.

[0027]

According to the timing correction method and apparatus of the present invention, the judgment system deskew and the application system deskew can be performed at the same frequency as the actual measurement frequency.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of a conventional technology.

FIG. 2 is a diagram showing an example of a timing correction device of the semiconductor test device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... IC tester 2 ... Short jig 10 ... Control circuit 11 ... Timing generator 21-2n ... Driver 31-3n, 41-4n, 81-8n ... Comparator 51-5n, 61-6n ... Variable delay circuit 71-7n ... I / O switch

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiroshi Hikawa 3-16-3 Higashi, Shibuya-ku, Tokyo F-term in Hitachi Electronics Engineering Co., Ltd. 2G032 AA01 AB06 AE06 AE08 AG07 AH02 AL00

Claims (6)

[Claims] Connecting a first group of tester pins having at least drive means and a second group of tester pins having at least comparator means to respective signal pins of a short jig via respective signal lines; A signal waveform is output from the drive means of the first tester pin other than the first tester pin for which the determination system deskew is to be obtained in the first tester pin group to the short jig,
A comparator of the second tester pin connected via the signal line to a first tester pin for which a determination system deskew is to be obtained with reference to a single synthesized waveform synthesized at a short end of the short jig. Performing a decision-based deskew by increasing or decreasing the delay amount of the variable delay means for use and performing timing correction of the strobe signal supplied to the comparator means; and wherein the timing correction is applied to all the first and second tester pins. On the other hand, with the short jig removed,
A signal waveform is output from all the drive means of the first tester pin group, and the delay amount of each driver variable delay means of the first tester pin is increased / decreased based on the timing-corrected strobe signal. Performing the timing of the signal waveform supplied to the comparator means of the second tester pin connected to the first tester pin via the signal line, thereby performing the application system deskew. A timing correction method for a semiconductor test apparatus. 2. The timing correction method for a semiconductor test apparatus according to claim 1, wherein the determination system deskew is further performed after the application system deskew is completed. 3. The method according to claim 1, wherein the first tester pin and the second tester pin include a driver variable delay unit, a driver unit, a comparator variable delay unit, and a comparator unit. A characteristic timing correction method for a semiconductor test apparatus. 4. A first tester pin group having at least a drive means, a second tester pin group having at least a comparator means, and a plurality of signal pins are short-circuited, respectively. A short jig in which each signal pin is connected to the first tester pin and the second tester pin via a signal line, respectively, a first jig which is a determination system deskew acquisition target in the first tester pin group Outputting a signal waveform from the driving means of the first tester pin other than the tester pin to the short jig;
A comparator of the second tester pin connected via the signal line to a first tester pin for which a determination system deskew is to be obtained with reference to a single synthesized waveform synthesized at a short end of the short jig. The determination system deskew is performed by increasing or decreasing the delay amount of the variable delay means for use and correcting the timing of the strobe signal supplied to the comparator means, and this timing correction is performed for all the first and second tester pins. In a state where the short jig is removed, a signal waveform is output from all the driving means of the first tester pin group, and the plurality of first tester pins are output based on the timing-corrected strobe signal. The delay amount of the variable delay means for each driver of the tester pin is increased and decreased to be connected to the first tester pin via the signal line. Timing correction device for a semiconductor test apparatus according to the second feature in that it is configured to include a control means for applying system deskew by performing timing correction of the signal waveforms applied to comparator means tester pin that. 5. The timing correction device of a semiconductor test apparatus according to claim 4, wherein the control unit further executes the determination system deskew after the application system deskew is completed. 6. The method according to claim 4, wherein the first tester pin and the second tester pin include a driver variable delay unit, a driver unit, a comparator variable delay unit, and a comparator unit. Characteristic timing correction device for semiconductor test equipment.