KR20080014995A - Semiconductor testing apparatus - Google Patents

Abstract

A semiconductor testing apparatus in which measurement accuracy is prevented from being reduced and the number of to-be-tested devices that can be simultaneously measured is increased. The semiconductor testing apparatus has a driver DR for inputting a signal to a pin of DUTs (200), a signal line connected at one end to the output end of the driver DR and having connection points provided in the middle of the signal line, and a termination resistor (28) connected to the other end of the signal line. The connection points provided in the signal line are respectively connected to the DUTs (200).

Description

Semiconductor Test Equipment {SEMICONDUCTOR TESTING APPARATUS}

The present invention relates to a semiconductor test apparatus for performing a functional test on a plurality of devices under test.

Conventionally, when performing a functional test on a plurality of devices under test using a semiconductor test apparatus, the output side of one driver is branched to connect two devices under test, and from one driver to these two devices under test. A method of simultaneously inputting a common test pattern is known (see Patent Document 1, for example). By making such a connection, it becomes possible to perform a functional test on many devices under test with a small number of drivers.

Patent Document 1: Japanese Patent Application Laid-Open No. 2000-292491 (pages 2 to 6, FIGS. 1 to 5)

By the way, in the method disclosed in Patent Document 1, for example, when the impedance of the signal line connected to the output end side of the driver is 50?, The impedance of each of the two signal lines to be branched must be 100?. Theoretically, if the impedance of the signal line at the branch point is set to 200 Ω and four of these signal lines are used, matching with the 50 Ω signal line connected to the output side of the driver can be achieved. A functional test can be performed for. However, in practice, the impedance of the wiring in the socket board for electrical connection of the device under test is in the upper limit of about 100 Ω, and it is not possible to increase the number of branches under test, that is, the number of devices under test that can perform the functional test at the same time. there is a problem. On the other hand, if the number of branches is set to 4 or more using such a low impedance signal line, reflection of the signal occurs due to impedance mismatch and the signal waveform is disturbed, so that the measurement accuracy is lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of such a point, and an object thereof is to provide a semiconductor test apparatus which can increase the number of devices under test that can be measured while preventing a decrease in measurement accuracy.

MEANS TO SOLVE THE PROBLEM In order to solve the above-mentioned subject, the semiconductor test apparatus of this invention is connected with the driver which inputs the application signal provided for a test to the pin of the device under test, and the one end is connected to the output terminal of the driver, and the some connection point provided in the middle And a termination line connected to the other end of the signal line, and each of the plurality of devices under test is connected to each of the plurality of connection points. As a result, it is possible to connect a plurality of devices under test to the signal lines without increasing the impedance of the signal lines, thereby eliminating the restrictions caused by the impedances of the signal lines and increasing the number of devices under test. .

The apparatus further includes test signal waveform generating means for generating a signal waveform required for the functional test of the device under test, receiving the signal waveform, generating an application signal with a driver, and connecting the generated application signal to a signal line. It is desirable to input for each of the plurality of devices under test. Thereby, it becomes possible to input a common application signal to the device under test which increased the number, and to carry out a functional test simultaneously.

In addition, it is preferable to match the output impedance of the driver described above, the impedance of the termination resistor, and the impedance of the signal line. As a result, disturbance of the signal waveform due to reflection of the signal output from the driver can be prevented, and a decrease in measurement accuracy can be prevented. For example, if the output impedance of the driver is 50 Ω, the impedance of the signal line is also set to 50 Ω. However, such a signal line is easy to realize, and the increase in the number of devices under test and the decrease in measurement accuracy are prevented. In addition, ease of control can be realized.

In addition, the main board is wired by a pin electronics mounted with the above-described driver and a driver channel having a termination resistor, and a coaxial cable connected to the pin electronics to form part of a signal line connected to each of the driver and the termination resistor; It is preferable to provide a socket board which is connected to the main board and is equipped with a plurality of devices under test, and which has a wiring which forms part of the signal line. This makes it possible to simultaneously test a large number of devices under test without increasing the impedance of the wiring in the socket board more than necessary.

Moreover, it is inserted between the DC power supply which produces | generates at least one of the voltage and current required for the DC test of the device under test mentioned above, the 1st switch which connects a DC power supply with respect to a signal line, and a driver and a signal line. It is preferable to further provide the 2nd switch which opens and closes a line. This makes it possible to selectively perform both the function test and the DC test on a plurality of devices under test using the same signal line.

In the semiconductor test apparatus of the present invention, one end is connected to a driver for a plurality of channels for inputting an application signal to be applied to a pin of a device under test, and an output terminal of the driver. The wiring length of the signal line which has a signal line which has a connection path connected to a pin sequentially in series, and connects in series between a plurality of devices under test is set to the same propagation delay amount in each of a plurality of channels. By making the wiring lengths of the signal lines of the respective channels the same and setting the same propagation delay time, separate timing control is unnecessary.

Moreover, it is preferable to further provide the termination resistor connected to the other end of the signal line connected to the above-mentioned driver. Thereby, reflection of a signal can be suppressed.

Moreover, the socket board of this invention is provided in the semiconductor test apparatus mentioned above, and is equipped with the some test device, and has the signal line which the several test device carries out the serial connection of the corresponding pin. By using such a socket board, it is possible to connect a plurality of devices under test without increasing the impedance of the signal line, and at the same time, the number of devices under test can be increased.

Moreover, it corresponds to the propagation delay amount accompanying the wiring length of the signal line which sequentially connects a plurality of devices under test in series above, and responds to the delay of the timing which arises in the application signal applied to the pin of each device under test. Based on this, it is preferable to adjust the delay timing for the IO channel connected to each IO pin of the plurality of devices under test. Thereby, the timing which takes in the output signal of each device under test according to the difference of the input timing of an application signal can be adjusted.

The above-described adjustment of the delay timing for the IO channel sets a delay amount for the second driver provided in the IO channel to offset the difference in propagation delay amount accompanying the difference in the wiring length of the signal line. For the comparator provided in the IO channel, it is preferable to set a delay amount that cancels the difference in propagation delay amount accompanying the difference in the wiring length of the signal line. Thereby, timing adjustment of both the driver and the comparator provided in each IO channel can be performed.

1 is a diagram showing an overall configuration of a semiconductor test apparatus of an embodiment.

2 is a diagram illustrating a connection state between a driver channel and an IO channel in the pin electronics and the DUT.

3 is a diagram showing a modification of a driver channel capable of supporting both a functional test and a DC test.

It is a figure which shows the structure of the modification which has a branch.

5 is a diagram illustrating a connection configuration of a modification in which no termination resistor is used.

* Description of the symbols for the main parts of the drawings *

10: semiconductor test apparatus main body 12: tester control unit

14: timing generator 16: pattern generator

18: data selector 20: format control

22: pin electronics 24, 24A, 24B: driver channel (Dch)

26: IO channel 28, 28B: termination resistor

30: motherboard 32: coaxial cable

40: socket board 60: workstation

200: DUT (device under test)

Hereinafter, the semiconductor test apparatus of an embodiment to which the present invention is applied will be described in detail. 1 is a diagram showing an overall configuration of a semiconductor test apparatus of an embodiment. This semiconductor test apparatus includes the semiconductor test apparatus main body 10 and the workstation 60 in order to perform various tests, such as a functional test and a DC test, with respect to several DUT (device under test 200). . The workstation 60 controls the whole series of test operations, such as a function test, and timing calibration operation, and implements the interface with a user. As the DUT 200, various semiconductor devices such as semiconductor memories and logic ICs can be considered.

The semiconductor test apparatus main body 10 executes various tests on the DUT 200 by executing a predetermined test program transmitted from the workstation 60. For this reason, the semiconductor test apparatus main body 10 includes a tester control unit 12, a timing generator 14, a pattern generator 16, a data selector 18, a format control unit 20, and pin electronics 22. . These tester control unit 12, timing generator 14, pattern generator 16, data selector 18, and format control unit 20 correspond to test signal waveform generating means.

The tester control unit 12 is connected to each component such as the timing generator 14 via a bus and executes a test program transmitted from the workstation 60, thereby performing control necessary for various test operations for each component. Conduct.

The timing generator 14 sets the basic period of the test operation and generates various timing edges included in the set basic period. The pattern generator 16 generates various pattern data. The data selector 18 assigns the logical pin numbers, which are various patterns output from the pattern generator 16, to the physical pin numbers of the DUT 200, and corresponds them. The format control unit 20 generates a waveform generated by the pattern generator 16 and applied to the DUT 200 based on the pattern data selected by the data selector 18 and the timing edge generated by the timing generator 14. Control is performed.

The pin electronics 22 are for taking a physical interface to the DUT 200, and are based on the waveform signal FD or strobe signal STB generated by the waveform control of the format control unit 20, and in fact, the DUT ( A signal input and output between 200 and 200 is generated. For this reason, the pin electronics 22 is provided with the some driver channel (Dch: 24) and the some IO channel (Ioch: 26). The pin electronics 22 is usually housed in a dedicated test head, and has a structure that can be separated from the apparatus main body.

Driver channel 24 generates the actual test waveform that is input to the driver pins of DUT 200. For this reason, the driver channel 24 has the driver DR and the variable delay element VD which adjusts the timing of the waveform signal FD input to this driver DR. Here, the driver pins are pins that apply only test waveforms to the DUT 200, such as address pins and various control pins of the memory device. The driver DR applies a test waveform, which is a delayed waveform signal FD output from the format control unit 20 at an arbitrary timing through the variable delay element VD, to the DUT 200. The variable delay element VD may be provided in the format control unit 20.

The IO channel 26 generates an actual test waveform applied to the IO pin of the DUT 200, and receives a response signal actually output from the IO pin to perform timing determination in synchronization with the strobe signal STB. Therefore, the IO channel 26 is connected to the variable delay element VD, the comparator CP, and the comparator CP, which adjust the timing of the driver DR and the waveform signal FD inputted to the driver DR. The variable delay element VD which adjusts the timing of the input strobe signal STB is provided. Here, the IO pin is an input / output pin, which is a pin that performs the application of a test waveform and the timing of the response signal like the data pin of the memory device. The comparator CP samples the response signal at a timing based on the strobe signal STB outputted from the format control unit 20 and input through the variable delay element VD. Supply to a circuit (not shown).

In addition, the main body 30 of the semiconductor test apparatus 10 is equipped with a main board 30 for intermediating between the socket board 40 and the pin electronics 22 and is described in detail through the coaxial cable 32 in the main board 30. One pin electronics 22 is connected to the socket board 40. In the socket board 40, a plurality of DUTs 200 are mounted through an IC socket (not shown), and wiring for connecting the driver pins or IO pins of the DUTs 200 to the main board 30 is made.

FIG. 2 is a diagram showing a connection state between a driver channel 24 and an IO channel 26 in the pin electronics 22 and a plurality of n (for example, four) DUTs 200. In this embodiment, one driver channel 24 and four DUTs 200 (200-1, 200-1, 200-3, 200-4) in the pin electronics 22 correspond to each other. That is, a common signal output from the driver DR in this driver channel 24 is input to the same driver pin of each of the four DUTs 200-1 to 200-4, and the four DUTs 200-1 to 200-4) and the like are performed simultaneously.

Specifically, the output terminals of the driver DR in the driver channel 24 are coaxial cables 32 and 32-1 in the main board 30, wirings C1, C2, C3, C4, and the like in the socket board 40. C5) and the coaxial cables 32 and 32-2 in the main board 30 are connected to the terminating resistor 28 in the driver channel 24. The output impedance of the driver DR in the driver channel 24 is set to 50 Ω. In addition, the coaxial cables 32-1 and 32-2 in the main board 30, the wirings Cl, C2, C3, C4 and C5 in the socket board 40, and the termination resistor 28 in the driver channel 24. Each impedance of is also set to 50?. Therefore, the signal output from the driver DR in the driver channel 24 is transmitted to the termination resistor 28 without causing reflection. The termination resistor 28 may be provided in the socket board 40 or the main board 30.

In the socket board 40, the driver pins of the DUT 200-1 are connected to the connection points of the wirings C1 and C2. Similarly, the driver pins of the DUT 200-2 are connected to the connection points of the wirings C2 and C3. The driver pins of the DUT 200-3 are connected to the connection points of the wirings C3 and C4. The driver pins of the DUT 200-4 are connected to the connection points of the wirings C4 and C5. As described above, in this embodiment, the wirings C1, C2, C3, C4, and C5 in the socket board 40 are cascaded (serial connection), and a plurality of DUTs 200-1 to 200-4 are connected to the connection points of the respective wirings. ) Is connected.

The connection between the IO pins included in each of the DUTs 200-1 to 200-4 and the respective IO channels 26 in the pin electronics 22 is performed as in the prior art. That is, each IO pin of the DUT 200-1 and each IO channel 26 are connected so as to be one-to-one, and a pass / fail determination for a signal output from each IO pin is separately performed.

Here, in FIG. 2, the waveforms applied to the driver pins of the respective DUTs are applied at different timings so as to be represented by the delay times DL1 to DL4. On the other hand, the delay times DL21 to DL24 of the four IO channels 26a to 26d become the same. In this case, the offset delay amount DLx is set for the variable delay element VD of the driver DR provided on the IO channel 26 side for each DUT and the variable delay element VD of the strobe signal STB. Delay correction to give is necessary. That is, in the case of the IO channel 26b, offset delay amount DLx = DL2-DL1 is provided. In the case of the IO channel 26c, the offset delay amount DLx = DL3-DL1 is given. In the case of the IO channel 26d, an offset delay amount DLx = DL4-DL1 is provided. In addition, it is preferable to wire a plurality of adjacent DUTs such that the offset delay amount DLx is minimized. In addition, since the driver channel 24 exists in multiple channels, it is necessary to design the wiring pattern in the socket board 40 so that the delay time DL1-DL4 corresponding to each driver channel 24 may become the same, respectively. . In addition, in order to minimize skew between the channels, it is preferable to perform timing calibration for the plurality of IO channels 26 and the plurality of driver channels 24 to perform skew adjustment.

In the semiconductor test apparatus of this embodiment, one strand comprising a coaxial cable 32-1, wirings C1, C2, C3, C4, C5, and a coaxial cable 32-2 is connected to the driver DR in the driver channel 24. One end of the signal line is connected, and four DUTs 200-1 to 200-4 are connected to other places along the way of the signal line. By matching the impedance of the coaxial cable 32-1, the wiring C1 and the like and connecting the terminating resistor 28 to the tip of the signal line, the reflection of the signal in the middle and at the tip of the signal line can be eliminated. Therefore, the fall of the measurement accuracy resulting from the disturbance of the signal waveform by reflection can be prevented. In addition, since it is not necessary to increase the impedance of the wiring C1 and the like in the socket board 40 in order to increase the number of DUTs 200 as in the related art, the number of DUTs 200 that can be measured at the same time can be easily set to 2 or more. I can increase it. As a result, in the case of the driver channel 24 having hundreds to thousands of channels, the number of channels can be significantly reduced, and thus a more inexpensive semiconductor test apparatus can be realized.

In this way, it is possible to connect the plurality of DUTs 200 to the signal line without increasing the impedance of the signal line, thereby eliminating the restriction by the impedance of the signal line and increasing the number of DUTs 200 that can be measured simultaneously. There is a number. In addition, it is possible to input a common application signal to a plurality of DUTs 200 having a larger number and to perform a function test at the same time.

In addition, this invention is not limited to the Example mentioned above, A various deformation | transformation is possible within the scope of the summary of this invention. For example, in the above-described embodiment, the configuration in the case where the signals output from the driver DR are input to the four DUTs 200-1 to 200-4 when the functional test is performed has been described. In the DC test for supplying a constant current, almost the same configuration can be used simply by making a slight change.

3 is a diagram showing a modification of a driver channel capable of supporting both a functional test and a DC test. The driver channel 24A shown in FIG. 3 has a configuration in which switches 50, 52, 56 and a DC power supply 54 are added to the driver channel 24 shown in FIGS. 1 and 2. The switch 50 is arranged between the output terminal of the driver DR and the work of the coaxial cable 32-1 in the main board 30, and interrupts the connection between them. The switch 52 is disposed between the termination resistor 28 and one end of the coaxial cable 32-2 in the main board 30 to interrupt the connection therebetween. The switch 56 is disposed between the DC power supply 54 and one end of the coaxial cable 32-1 in the main board 30 and interrupts the connection therebetween. The DC power supply 54 generates a constant voltage or a constant current necessary for the direct current test. The switches 50 and 56 correspond to the first switch, and the switch 52 corresponds to the second switch, respectively.

In the case of performing a functional test using the driver channel 24A mentioned above, the switches 50 and 52 are turned on and the switch 56 is turned off. By performing such a switch control, the connection state like the driver channel 24 shown in FIG. 2 is implement | achieved, and a functional test is performed after that. The above switch control is performed by the tester control unit 12.

In the case of performing the DC test, the switches 50 and 52 are turned off, and the switch 56 is turned on. By performing such switch control, a connection state is realized in which only the DC power supply 54 is connected to one end of the signal line formed by the coaxial cable 32-1, the wiring C1, or the like, and one end of the signal line is opened. DC test is then performed. In this manner, both the functional test and the DC test can be selectively performed on the plurality of DUTs 200 using the same signal line. In addition, the termination resistor 28 or the switch 52 may be provided in the socket board 40 or the main board 30.

In the above-described embodiment, the present invention may be combined with the same branch as in the prior art. It is a figure which shows the structure of the modification which has a branch. The driver channel 24B shown in FIG. 4 has a structure in which the termination resistor 28B is added to the driver channel 24 shown in FIG. The main board 30B has a configuration in which one strand of coaxial cables 32 and 32-3 connecting the driver channel 24B and the socket board 40B is added. The socket board 40B includes two signal lines formed by the wirings C1 to C5 in the socket board 40 shown in FIG. 2, and one end of each of the two signal lines is connected to the main board 30B. Has a branching structure commonly connected to the coaxial cable 32-1. In order to prevent reflection of a signal at the connection point (branch point) between the coaxial cable 32-1 and the two-strand signal line, the two-wire signal line when the impedance of the coaxial cable 32-1 is 50? Each impedance of is set to 100Ω. Therefore, the impedances of the two termination resistors 28 and 28B in the driver channel 24B are also set to 100?. By combining the methods of branching the wirings in the socket board 40B in this manner, it is possible to increase the number of DUTs 200 that can be measured simultaneously without causing signal reflection.

FIG. 5 is a diagram showing a connection configuration of a modification in which no termination resistor is used, and the connection configuration in which the termination resistor 28 is removed in the configuration shown in FIG. 2 is shown. Also in this case, the impedance of the transmission line from the output terminal to the far end of the driver channel 24 is 50?, But at the connection point of the wirings C1 to C4 to each DUT, the capacitance component is slightly applied. It causes a drop in impedance. When using the DUT which can tolerate the waveform quality of the test waveform when not terminating using the terminating resistor 28, a connection configuration in which the terminating resistor 28 is removed may be adopted as shown in FIG.

In addition, although the socket board 40 was connected to the pin electronics 22 via the main board 30 in the above-mentioned embodiment, each of these board names differs according to the manufacturer of a semiconductor test apparatus, or the like. For example, the main board 30 connected to the pin electronics 22 may be referred to as a performance board, and the combination of the main board 30 and the socket board 40 may be realized by a combination of three or more boards. In some cases, as shown in Fig. 2, the present invention can be applied as long as a plurality of DUTs 200 are connected in the middle of a single signal line.

According to the present invention, it is possible to connect a plurality of devices under test to a signal line without increasing the impedance of the signal line, thereby eliminating the restriction by the impedance of the signal line and increasing the number of devices under test. Can be.

Claims (10)

A driver for inputting an applied signal to a pin of a device under test for a test; A signal line having one end connected to an output terminal of the driver and having a plurality of connection points provided on the way; And a terminating resistor connected to the other end of the signal line, and connecting each of the plurality of devices under test to each of the plurality of connection points. The method of claim 1, Further comprising test signal waveform generating means for generating a signal waveform required for the functional test of the device under test, And receiving the signal waveform to generate an application signal to the driver, and input the generated application signal to each of the plurality of devices under test connected to the signal line. The method of claim 1, And an output impedance of the driver, an impedance of the termination resistor, and an impedance of the signal line. The method of claim 3, wherein Pin electronics equipped with the driver and a driver channel having the termination resistor; A main board wired by a coaxial cable connected to the pin electronics to form part of the signal line connected to the driver and the termination resistor, respectively; And a socket board which is connected to the main board and is equipped with wiring for forming a part of the signal line at the same time as the plurality of devices under test are mounted. The method according to any one of claims 2 to 4, A DC power supply generating at least one of a voltage and a current required for a DC test of the device under test; A first switch connecting said DC power supply to said signal line; And a second switch inserted between the driver and the signal line to open and close the line. A driver for a plurality of channels for inputting an applied signal to a pin of a device under test for a test; A signal line having one end connected to an output terminal of the driver and having a connection path sequentially connected to corresponding pins of a plurality of devices under test, The semiconductor test apparatus of which the wiring length of the said signal line which connects in series between the plurality of devices under test is set to the same propagation delay amount in each of the plurality of channels. The method of claim 6, And a termination resistor connected to the other end of the signal line connected to the driver. A socket board provided in the semiconductor test apparatus according to claim 1 and on which a plurality of devices under test are mounted, And the signal line for serially connecting corresponding pins of the plurality of devices under test. The method of claim 6, On the basis of a delay in timing generated in an applied signal applied to a pin of each device under test, corresponding to a propagation delay amount associated with the wiring length of the signal line sequentially connecting the plurality of devices under test; And a delay timing adjustment for an IO channel connected to each IO pin of the plurality of devices under test. The method of claim 9, Adjusting the delay timing for the IO channel sets a delay amount for the second driver provided in the IO channel to offset the difference in propagation delay amount accompanying the difference in the wiring length of the signal line, The semiconductor test apparatus which sets the delay amount which cancels the difference of the propagation delay amount accompanying the difference of the wiring length of the said signal line with respect to the comparator provided in the said IO channel.

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