JP2000091893A - Pulse generating circuit and tester using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse generating circuit for realizing wide delay adjustment width, and generating a highly precise delay pulse, an a tester for realizing highly precise selection using this pulse generating circuit. SOLUTION: This pulse generating circuit to be used for a tester for measuring an LSI generates a pulse with an arbitrary delay time. This pulse generating circuit is constituted of a clock delay generating circuit 1 for generating a delay pulse in the cycle units of an inputted clock pulse, a gate delay generating circuit 2 for generating a delay pulse by gate delay based on the delay pulse outputted by the clock delay generating circuit 1, and a load delay generating circuit 3 for controlling a delay time according to an output load and generating a delay pulse based on the delay pulse outputted by the gate delay generating circuit 2. This pulse generating circuit is constituted by combining three circuit systems in which delay precision is different.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generation circuit technology, and more particularly to a pulse generation circuit which has a wide delay adjustment range and is suitable for generating a highly accurate delay pulse, and is effective when applied to a tester using the same. About technology.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in the technical field of LSI, the performance of this LSI has been improved, and with this, the performance requirements of a tester for measuring the LSI have become strict. In order to change an input signal or an output strobe with high accuracy, a demand for a high-precision delay pulse generation circuit is increasing. For example, a technique of generating a delay pulse by combining a clock pulse and a gate delay can be considered.

[0003] As a technique relating to such a delay pulse generating circuit, for example, February 10, 1990
The technology described in the literature of "Complete Master of Oscillation Circuits for Electronic Circuits" published by Japan and Japan Publishing Association.

[0004]

In the above-described delay pulse generation circuit, a delay pulse is generated by combining a clock pulse and a gate delay. However, it is conceivable that sufficient accuracy cannot be obtained.

Accordingly, an object of the present invention is to provide a pulse generation circuit capable of generating a highly accurate delay pulse with a wide delay adjustment range by combining different delay pulse generation circuits, and a highly accurate delay pulse using the same. A tester capable of sorting is provided.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the pulse generating circuit according to the present invention combines the three of the generation of the delay pulse, the clock pulse, the gate delay, and the change of the gate input capacitance,
Each has a first, second, and third delay generation circuit that generates a delay pulse.

In this configuration, the first delay generation circuit includes a decrementer and an all-zero checker, the second delay generation circuit includes a plurality of buffers and a plurality of selectors, and the third delay generation circuit includes a plurality of logic gates for load capacitors. It is configured to include a buffer and the like.

Further, a tester according to the present invention has timing generating means including the pulse generating circuit, test pattern generating means, transmitting / receiving means, measuring means, control means and the like.

Therefore, according to the pulse generating circuit, it is possible to generate a timing signal with high accuracy and a wide delay range. As a result, this pulse generation circuit is set to LS
When used in the tester I, it is possible to sort LSIs with high accuracy. Further, in addition to the LSI tester, the present invention can be applied to an EB drawing apparatus, various measuring instruments, and the like.

This is based on a combination of three methods having different delay precisions, thereby realizing a highly accurate delay generation circuit having a wide delay adjustment range.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a pulse generating circuit according to an embodiment of the present invention. FIGS. 2 to 4 are circuit diagrams showing respective delay generating circuits in the pulse generating circuit according to the present embodiment. Is a waveform diagram showing the operation of the pulse generation circuit, and FIG. 6 is a configuration diagram showing an LSI tester using the pulse generation circuit according to the present embodiment.

First, the configuration of the pulse generating circuit according to the present embodiment will be described with reference to FIG.

The pulse generating circuit according to the present embodiment is used, for example, in a tester for measuring an LSI, and is a circuit for generating a pulse with an arbitrary delay time. And a clock delay generation circuit 1 for generating a delay pulse in cycle units of
A gate delay generation circuit 2 that generates a delay pulse by a gate delay is combined with a load delay generation circuit 3 that generates a delay pulse by controlling a delay time by an output load based on the output delay pulse. I have.

The clock delay generation circuit 1 includes a selector SL1 and a selector SL, as shown in FIG.
A flip-flop FF1 connected to the output of L1, a decrementer DC1 and an all-zero checker AZ1 connected in parallel to the output of the flip-flop FF1
And a flip-flop FF2 connected to the output of the all-zero checker AZ1, etc., for generating a delay in clock cycle units. The operation is controlled by the load signal LOAD and the count signal CIN input to the selector SL1 based on the clock pulse CLK input to the flip-flops FF1 and FF2.
The UT is output.

The gate delay generation circuit 2 includes a plurality of buffers BF1 connected in cascade, as shown in FIG.
1 to BF16 and a plurality of selectors SL11 to SL16
And a circuit that generates a delay by a gate delay. Input is clock delay generation circuit 1
And the selectors SL11 to SL11 based on the delay pulse PIN1 input to the buffer BF11.
The operation is controlled by the control signal CONS1 input to SL15, and the delay pulse POUT is output from the selector SL11.
1 is output.

The load delay generating circuit 3 is, for example, as shown in FIG.
, Two buffers BF21 and BF22,
A plurality of load capacity logic gates AND21 and AND2 connected in parallel between the buffers BF21 and BF22.
4 and a circuit for controlling the delay time by the output load. The input is connected to the output of the gate delay generation circuit 2, and based on the delay pulse PIN2 input to the buffer BF21, each logic gate A
Control signal CONS2 input to ND21 to AND24
, And the buffer BF22 outputs the delay pulse POUT2.

Next, the operation of this embodiment will be described with reference to FIG.
The operation of the pulse generation circuit will be described with reference to FIG. FIG. 5 shows the waveforms of the input clock pulse CLK and the delay pulses POUT, POUT1, and POUT2 of the respective circuits.

(1) The clock delay generation circuit 1 receives, for example, a clock pulse CLK having a period T in which ON / OFF is repeated with the same pulse width.

In the clock delay generation circuit 1, the load signal LOAD is turned on to start up, and when data corresponding to the number of cycles to be delayed from the count signal CIN is input, the data is input to the flip-flop FF1 via the selector SL1. In synchronization with the clock pulse CLK, the decrement process is repeatedly performed through the selector SL1, the flip-flop FF1, and the decrementer DC1, and when the all-zero checker AZ1 becomes all zero, the delay pulse POUT is output through the flip-flop FF2. The delay pulse POUT of this output has a delay time of t = n · T, where T is the cycle of the clock pulse CLK and n is the input value of the count signal CIN. Although this circuit uses the decrementer DC1, it can also be configured using an overflow by an incrementer.

(2) In the gate delay generation circuit 2, each of the selectors SL11 to SL11 is controlled by each of the control signals CONS1.
By controlling the operation of SL15, each of the buffers BF11 to BF1 is controlled.
6, the input / output path via each of the selectors SL11 to SL16 is changed to input the delay pulse PIN1.
The delay pulse POUT1 is output based on (= POUT). The delay pulse POUT1 is a delay of one stage and the selector 1-stage buffer and t _d, when the number of stages and selected m, the delay signal by t1 = m · t _d of time.

(3) In the load delay generation circuit 3,
Utilizing the fact that the delay differs between when the input capacitance of each of the logic gates AND21 to AND24 changes and when it does not change, each of the logic gates A is controlled by each of the control signals CONS2.
The operation of ND21 to AND24 is controlled to adjust the fine delay by changing the load capacitance, and the delay pulse P is set based on the input delay pulse PIN2 (= POUT1).
OUT2 is output. This delay pulse POUT2
Assuming that the delay of one input capacitance change is t _c , the changed number is 1 and the buffer delay is t _b , t 2
= L · t _c + t _b .

As described above, in the pulse generation circuit including the combination of the clock delay generation circuit 1, the gate delay generation circuit 2, and the load delay generation circuit 3, the clock delay generation circuit 1, the gate delay generation circuit 2, the load delay generation circuit Finer delay adjustment can be performed in the order of the circuit 3.

Next, as an example using the pulse generation circuit, the configuration of an LSI tester will be described with reference to FIG.

The LSI tester is, for example, as shown in FIG.
A main processor MP for controlling the entire tester, a buffer storage BS capable of bidirectional data transfer between the main processor MP, a reference level supply unit RPS, a local memory LM, a fail memory FMF,
Algorithmic pattern generator ALPG, fail memory FMM, timing generator TG, DC measurement unit DCM and DC power supply unit DPS, pin electronics PE for transmitting / receiving signals between each unit and LSI, and test And a test board TB on which the LSI is mounted.

The operation of this LSI tester is based on the control of the main processor MP and the pin electronics PE.
, A test pattern from the local memory LM, a pattern signal from the algorithmic pattern generator ALPG, and a timing signal from the timing generator TG are respectively input, and a DC function test of the LSI mounted on the test board TB is performed. As a result of this test, the fail information is stored in the fail memories FMF and FMM and used for failure analysis of the LSI. Further, a DC parametric test is performed using the DC measurement unit DCM.

In this LSI tester, in particular, the timing generator TG includes a pulse generation circuit composed of a combination of the clock delay generation circuit 1, the gate delay generation circuit 2, and the load delay generation circuit 3 described above. A timing signal for testing can be generated in a wide delay range by fine delay adjustment. As a result, LSIs can be sorted with high accuracy.

Therefore, according to the pulse generation circuit of the present embodiment, by combining the clock delay generation circuit 1, the gate delay generation circuit 2, and the load delay generation circuit 3 having different delay precisions, a high precision and a wide range are provided. A timing signal in a delay range can be generated. When this pulse generation circuit is used in an LSI tester, LSIs can be sorted with high accuracy.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, the clock delay generation circuit, the gate delay generation circuit, and the load delay generation circuit are not limited to the circuit configurations shown in FIGS. The present invention is also applicable to a case where a function is realized. For example, as a logic gate for the load capacitance shown in FIG.
A gate or the like can be used.

In order to prevent the influence of the device variation, the power supply of the delay generation circuit is separated from the pulse generation circuit, a ring oscillator is provided in the delay generation circuit, and the output frequency of the delay generation circuit is controlled by the output frequency. By varying the power supply voltage, a specified delay value can be obtained.

Further, two pulse generating circuits are used,
It is also possible to accurately generate a pulse of an arbitrary length as a rising detection pulse and a falling detection pulse.

In the above embodiment, the case where the pulse generating circuit is applied to an LSI tester has been described. However, the present invention is applied to an EB drawing apparatus for drawing a pattern on a wafer or a mask using an electron beam, various measuring instruments, and the like. Can also be applied.

[0036]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By having first, second, and third delay generation circuits that generate each delay pulse by a change in clock pulse, gate delay, and gate input capacitance,
Since three methods having different delay accuracy can be combined, it is possible to generate a timing signal with high accuracy and a wide delay range.

(2) By using the pulse generation circuit as a tester, it becomes possible to select an LSI with high accuracy.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a pulse generation circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram showing a clock delay generation circuit in the pulse generation circuit according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a gate delay generation circuit in the pulse generation circuit according to one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a load delay generation circuit in the pulse generation circuit according to one embodiment of the present invention.

FIG. 5 is a waveform chart showing an operation of the pulse generation circuit according to one embodiment of the present invention.

FIG. 6 is a configuration diagram showing an LSI tester using the pulse generation circuit according to one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 clock delay generation circuit 2 gate delay generation circuit 3 load delay generation circuit SL1 selector FF1, FF2 flip-flop DC1 decrementer AZ1 all-zero checker BF11-BF16 buffer SL11-SL16 selector BF21, BF22 buffer AND21-AND24 logic gate MP main processor BS buffer storage RPS reference level supply unit LM local memory FMF fail memory ALPG algorithmic pattern generator FMM fail memory TG timing generator DCM DC measurement unit DPS DC power supply unit PE pin electronics TB test board

Continued on the front page (72) Inventor Kazuyoshi Sato 3-16-6 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Toshiei Keikoin 1 Horiyamashita, Hadano-shi, Kanagawa F-term in Hitachi Information Technology (reference) 2G032 AA01 AA04 AD06 AE11 AE16 AG01 AG07 5J049 AA07 AA08 AA31 CC05

Claims (5)

[Claims] 1. A pulse generation circuit for generating a predetermined delay pulse using an input clock pulse,
A first delay generation circuit that generates a delay pulse in cycle units of the clock pulse based on the clock pulse; and a delay pulse generated by a gate delay based on the delay pulse output from the first delay generation circuit. A second delay generation circuit for generating;
And a third delay generation circuit for controlling a delay time by an output load to generate a delay pulse based on the delay pulse output from the second delay generation circuit. 2. The pulse generation circuit according to claim 1, wherein the first delay generation circuit includes a decrementer and an all-zero checker, inputs data corresponding to the number of cycles to be delayed, and outputs the data to the clock pulse. A pulse generation circuit, wherein the decrementer performs a decrement process in synchronization with the decrementer, and outputs a delay pulse when the value becomes all zero by the all zero checker. 3. The pulse generation circuit according to claim 1, wherein the second delay generation circuit includes a plurality of buffers and a plurality of selectors, and operates the respective buffers and the respective selectors according to a control signal. A pulse generating circuit for controlling a delay time and outputting a delay pulse by changing an input / output path. 4. The pulse generation circuit according to claim 1, wherein said third delay generation circuit includes a plurality of logic gates for load capacitance and a buffer, and controls the operation of each of said logic gates by a control signal. A pulse generator for controlling the delay, outputting a delay pulse via the buffer, by adjusting a fine delay based on a change in load capacitance caused by each of the logic gates. 5. A tester using the pulse generation circuit according to claim 1, comprising a timing generation unit, a test pattern generation unit, a transmission / reception unit, a measurement unit, and a control unit. A tester, wherein the timing generation means includes the pulse generation circuit.