KR102440440B1 - Semiconductor device inspection equipment - Google Patents

Abstract

A semiconductor element inspection apparatus is provided. The semiconductor device inspection apparatus receives first and second pattern data sequentially from an algorithm pattern generator (ALPG) and an algorithm pattern generator that sequentially generates first and second pattern data, and first and second a pin electronics (PE) configured to apply first and second output data to the semiconductor device under test (DUT) based on the pattern data, wherein the pin electronics include a second pattern data subsequent to the first and second pattern data. and a timing generator (TG) that outputs second output data while receiving 3 pattern data, and the pin electronics receives a match detection signal corresponding to the first output data from the semiconductor device under test.

Description

Semiconductor device inspection device {SEMICONDUCTOR DEVICE INSPECTION EQUIPMENT}

The present invention relates to a semiconductor element inspection apparatus.

A semiconductor device is produced in a wafer state, and after assembly as a semiconductor package is completed, it is finally subjected to an electrical inspection before being delivered to a user. This electrical inspection is a task to find defects generated in the wafer production process or assembly process, remove defective products, and select only good products.

In particular, in semiconductor devices such as DRAM or Flash, which are rapidly increasing in capacity, high speed, and multi-pin, increasing inspection efficiency in an electrical inspection process is emerging as an important problem in response thereto.

Recently, a semiconductor device inspection process has been studied in the direction of improving hardware high-speed inspection performance of an automatic test equipment (ATE) in order to increase inspection efficiency.

A plurality of semiconductor elements are simultaneously inspected to increase inspection efficiency. In order to perform a program on the plurality of semiconductor elements, it is necessary to detect a match result in which all of the plurality of semiconductor elements are in a ready state. It is possible to improve the hardware high-speed inspection performance by increasing the efficiency.

SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a semiconductor device inspection apparatus that shortens a subsequent inspection time after match detection.

Another technical problem to be solved by the present invention is to provide an apparatus for inspecting semiconductor devices that shortens the inspection time by reducing the test time for match detection.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

An apparatus for inspecting a semiconductor device according to some exemplary embodiments for achieving the above technical problem includes an algorithm pattern generator (ALPG) that sequentially generates first and second pattern data, and first and second pattern data from an algorithm pattern generator A pin electronics (PE) that sequentially receives the input and applies the first and second output data to the semiconductor device under test (DUT) based on the first and second pattern data; , a timing generator (TG) outputting second output data while receiving third pattern data subsequent to the first and second pattern data, wherein the pin electronics includes the first output data from the semiconductor device under test. is provided with a match detection signal corresponding to .

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the first pattern data corresponds to a match command, and pin electronics provides the match command to the semiconductor device under test.

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the signal generator outputs second output data in response to the match detection signal.

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the pin electronics further includes a memory configured to store second and third pattern data.

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the signal generator provides a match command to the semiconductor device under test based on pattern data stored in a memory.

In the semiconductor device inspection apparatus according to some embodiments for achieving the above technical problem, when it is determined that the pattern data cannot be stored in the memory, the pin electronics provides a pattern stop request signal to the algorithm pattern generator.

In an apparatus for inspecting a semiconductor device according to some embodiments of the present invention, the signal generator includes a determination unit that receives a match result signal corresponding to a match detection signal and outputs a flag bit signal in response to the match result signal do.

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the signal generator converts the second pattern data into the first flip-flop data in synchronization with the ZOH clock signal generated based on the flag bit signal and the clock signal and a second flip-flop outputting the first flip-flop data as the second output data in synchronization with the output first flip-flop and the clock signal.

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the determination unit receives a clock signal, the determination unit outputs a first flag bit signal based on the clock signal, and based on the first flag bit signal , a toggle operation of the ZOH clock signal is performed.

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the determination unit receives a match command signal and outputs a second flag bit signal in response to the match command, wherein the match command signal is applied to the first pattern data. Correspondingly, based on the second flag bit signal, the toggle operation of the ZOH clock signal is not performed.

An apparatus for inspecting a semiconductor device according to some embodiments of the present disclosure for achieving the above technical problem includes an algorithmic pattern generator (ALPG) that sequentially generates first and second pattern data, and sequentially inputs the first and second pattern data. receiving, and applying the first and second output data to the first semiconductor device under test (DUT) based on the first and second pattern data, and a first match corresponding to the first output data from the first semiconductor device under test The first and second pattern data are sequentially received from the first Pin Electronics (PE) receiving the detection signal and the algorithm pattern generator, and based on the first and second pattern data, it is transmitted to the second semiconductor device under test. Corresponding to the first match detection signal from the second pin electronics and the first pin electronics that apply the third and fourth output data and receive the second match detection signal corresponding to the third output data from the second semiconductor device under test a first digital signal is provided, a second digital signal corresponding to a second match detection signal is provided from the second pin electronics, and a match result is matched to the first and second pin electronics based on the first and second digital signals an AND operator providing a signal, wherein the first pin electronics generates second output data based on the match result signal and the second pattern data, and the second pin electronics generates second output data based on the match result signal and the fourth pattern data. Generate fourth output data.

According to some embodiments of the present invention, a semiconductor device inspection apparatus includes a first determiner configured to receive a match result signal and output a first flag bit signal in response to the match result signal. and the second pin electronics includes a second determination unit that receives a match result signal and outputs a second flag bit signal in response to the match result signal.

In the semiconductor device inspection apparatus according to some embodiments of the present invention for achieving the above technical problem, the first pin electronics is synchronized with the first ZOH clock signal generated based on the first flag bit signal and the clock signal to the second pattern data. The display device further includes a first flip-flop for outputting first flip-flop data and a second flip-flop for outputting the first flip-flop data as second output data in synchronization with a clock signal, wherein the second pin electronics includes a second flag A third flip-flop outputting second flip-flop data with respect to the fourth pattern data in synchronization with the second ZOH clock signal generated based on the bit signal and the clock signal, and the fourth flip-flop data in synchronization with the clock signal It further includes a fourth flip-flop for outputting the output data.

In an apparatus for inspecting a semiconductor device according to some embodiments to achieve the above technical object, the toggle operation of the first ZOH clock signal is performed by the first flag bit signal, and the second ZOH clock signal is changed by the second flag bit signal. A toggle operation is performed.

In an apparatus for inspecting a semiconductor device according to an embodiment of the present invention, the first determination unit and the second determination unit receive a clock signal, and the first determination unit outputs a first flag bit signal based on the clock signal, , the second determination unit outputs a second flag bit signal based on the clock signal, a toggle operation of the first ZOH clock signal is performed based on the first flag bit signal, and a second ZOH based on the second flag bit signal A toggle operation of the clock signal is performed.

In the semiconductor device inspection apparatus according to some embodiments for achieving the above technical problem, the first pin electronics outputs second output data while receiving third pattern data subsequent to the first and second pattern data, and The 2-pin electronics outputs fourth output data while receiving the third pattern data.

1 is a block diagram illustrating an apparatus for inspecting a semiconductor device according to some embodiments of the present invention.
2 is a block diagram illustrating pin electronics according to some embodiments of the present invention.
3 is a block diagram illustrating a signal generator according to some embodiments of the present invention.
4 is a block diagram illustrating a match AND operator according to some embodiments of the present invention.
5 is a ladder diagram for explaining an operation of a semiconductor device inspection apparatus according to some embodiments of the present invention.
6 to 8 are views for explaining the operation of the semiconductor device inspection apparatus according to some embodiments of the present invention.
9 is a view for explaining the effect of the semiconductor device inspection apparatus according to some embodiments of the present invention.

Embodiments of the present invention are described in detail with reference to the accompanying drawings. Identical components are indicated in different drawings but are designated by the same or like reference numerals. In the following description, specific details, such as detailed configurations and components, are provided merely to aid a general understanding of the embodiments of the present invention. Accordingly, it will be apparent to those skilled in the art that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present invention. Also, descriptions of well-known functions and structures may be omitted for clarity and brevity. The terms described below are terms defined in consideration of the functions of the present invention, and may vary according to the user, intention or custom of the user. Accordingly, definitions of terms should be determined according to the context throughout this specification.

The present invention is capable of various modifications and various embodiments, of which embodiments are described in detail below with reference to the accompanying drawings. However, it is to be understood that the present invention is not limited to these examples, but includes all modifications, equivalents and alternatives within the scope of the present invention.

Terms including first, second, etc. ordinal numbers may be used to describe various elements, but structural elements are not limited by the terms including ordinal numbers. The term may only be used to distinguish one element from another. For example, a first structural component may be referred to as a second structural component without departing from the scope of the present invention. Similarly, the second structural component may also be referred to as a first structural component. As used herein, the term “and/or” includes any and all combinations of one or more related items.

All terms used herein are used only to describe various embodiments of the present invention, but are not intended to limit the present invention. The singular form is intended to include the plural unless the context clearly indicates otherwise. In the present invention, the term "comprising" or "having" refers to the presence of a feature, number, step, action, structural element, part, or combination thereof, and the presence thereof or one or more other features, number, It is to be understood that this does not exclude the presence or additional probabilities of steps, operations, structural components, parts, or combinations thereof.

All terms used herein have the same meaning as understood by one of ordinary skill in the art to which this invention belongs, unless defined otherwise. Terms such as commonly used dictionary definitions should be interpreted as having the same meaning as the contextual meaning of the related technical field, and unless clearly defined in the present invention, it should be interpreted as having an ideal or excessively formal meaning. should not

The electronic device according to some embodiments may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (eg, a smartphone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the present invention, the electronic device is not limited to those described above.

The terminology used herein is not intended to limit the present invention, but is to cover various modifications, equivalents, or substitutions to the embodiments in question. In connection with the description of the appended drawings, like reference numerals may be used to refer to similar or related elements. The singular form of the noun corresponding to the item may include the plural, unless the relevant context clearly indicates otherwise. As used herein, "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", Each phrase such as "at least one of A, B or C" may include all possible combinations of the items listed together in one of the phrases. As used herein, terms such as "primary," "secondary," "first," and "second" may be used to distinguish a corresponding element from another element, but in other aspects (e.g., For example, it is not intended to limit the components in importance or order). A component (eg, a first component) is "connected to", "coupled with", "with" another element (eg, a second component), with or without the terms "in operation" or "in communication with" When referred to as “coupled to,” “connected to,” or “connected to,” the component may be directly coupled to another component (eg, wired), wirelessly, or directly through a third component.

As used herein, the term “module” may include a unit embodied in hardware, software, or firmware, and other terms such as “logic”, “logic block”, “part” and “circuitry” may be used interchangeably with other terms such as ". A module may be one complex component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, according to one embodiment, the module may be implemented in the form of an application specific integrated circuit (ASIC).

1 is a block diagram illustrating an apparatus for inspecting a semiconductor device according to some embodiments of the present invention. 2 is a block diagram illustrating pin electronics according to some embodiments of the present invention. 3 is a block diagram illustrating a signal generator according to some embodiments of the present invention. 4 is a block diagram illustrating a match AND operator according to some embodiments of the present invention.

1 to 4, the semiconductor device inspection apparatus 100 is a processor 110, an algorithm pattern generator (Algorithmic Pattern Generator; ALPG) 120, first to n-th pin electronics (Pin Electronics; PE) ( 130_1-130_n), first to n-th channels 140_1-140_n, and a match AND operator 150 .

The processor 110 executes a test program for a waveform to be applied to the device under test (DUT) 200_1-200_n. And, it performs an overall control role for the remaining components.

The test program may perform a direct current test, an alternating current test, and a function test, and in this case, the function test may check the function according to an actual operation program of a semiconductor memory device, for example, DRAM or Flash. .

That is, the test program writes the signal generated by the semiconductor device inspection apparatus 100 to the semiconductor device under test 200_1-200_n, reads it from the semiconductor device under test 200_1-200_n, and compares it with an expected pattern. By confirming, an electrical test is performed on the semiconductor devices under test 200_1-200_n.

The content of the waveform to be applied to the semiconductor device under test (DUT) is made in the form of a pattern (also referred to as a test vector) and input and stored in the pattern memory in the algorithm pattern generator 120, which is stored in the pattern memory. The pattern data is used to sequentially output logic data through the pin electronics 130_1-130_n. The output logic data includes an address to be applied to the semiconductor device under test (DUT), data, and a command including a match command/write command/erase command and the like.

The algorithm pattern generator 120 according to some embodiments of the present invention may sequentially transmit the plurality of pattern data PDs to the plurality of first to nth pin electronics 130_1-130_n, respectively, and the first to nth pin electronics 130_1-130_n. A pattern stop request signal may be received from the n-pin electronics 130_1-130_n. Before receiving the pattern stop request signal from the first to nth pin electronics 130_1-130_n, the algorithm pattern generator 120 may continuously provide a plurality of pattern data PD at a predetermined period.

Each of the first to n-th fin electronics 130_1-130_n is connected to the first to n-th semiconductor devices under test 200_1-200_n through respective first to n-th channels 140_1-140_n, and the first to Logic data may be provided to the n-th semiconductor device under test 200_1-200_n, and each of the first to n-th pin electronics 130_1-130_n may pass through the first to n-th channels 140_1-140_n. A state signal of the semiconductor device 200_1-200_n may be provided.

Referring to FIG. 2 , the pin electronics 130 may include a signal generator 131 , a memory 132 , and a digital converter 133 . The pin electronics 130 may correspond to the first to nth pin electronics 130_1-130_n of FIG. 1 , and the description of each of the signal generator 131 , the memory 132 and the digital converter 133 to be described later is described below. It is obvious that it is applied to the description of the signal generator, the memory, and the digital converter included in the first to nth pin electronics 130_1-130_n of FIG. 1 .

Referring to FIG. 3 , the signal generator 131 may receive a plurality of pattern data PD and a clock signal CLK from the algorithm pattern generator 120 , and sends a pattern stop request signal to the algorithm pattern generator 120 . and may provide a plurality of pattern data PD and a plurality of output data PD_out corresponding to the clock signal CLK to the semiconductor device under test 200 . The output data PD_out may correspond to the aforementioned logic data.

The signal generator 131 may include a first flip-flop 1311 , a second flip-flop 1312 , a determination unit 1313 , a clock AND operator 1314 , and a comparator 1316 .

The first flip-flop 1311 may receive a plurality of pattern data PD provided to the algorithm pattern generator 120 or stored pattern data PD′ provided from the memory 132 , and a clock AND operator 1314 . ) may output the flip-flop data FD in synchronization with the ZOH clock signal ZOH_Rate and provide it to the second flip-flop 1312 .

The second flip-flop 1312 may receive the flip-flop data FD provided from the first flip-flop 1311 , and output the output data PD_out in synchronization with the clock signal CLK to obtain a channel CH may be provided to the semiconductor device under test 200 through Although not shown in the drawing, the output size may be adjusted via a driver.

The determination unit 1313 receives the clock signal CLK, the match command signal M_CMD, and the match result signal MatchO provided from the match AND operator 150 , and receives the clock signal CLK and the match command signal M_CMD) and the match result signal (MatchO) to output a flag bit (F/B). The match command signal M_CMD is data input when the pattern data corresponding to the match command among the pattern data PD or the pattern data PD′ stored in the first flip-flop 1311 is provided, or the pattern data PD ) or the stored pattern data PD'.

When the match command signal M_CMD is input, the determination unit 1313 outputs a high-level second flag bit signal 2 ^nd F/B (refer to FIG. 5 ). After the second flag bit signal 2 ^nd F/B, when a predetermined number of cycle clock signals CLK are input or a high-level match result signal MatchO is input, the low-level first flag bit signal 1 ^st F/B, see FIG. 5). The level of the flag bit F/B output by the determination unit 1313 is not limited to the above high/low level example, and the high/low level may be changed according to a design change such as arrangement of an inverter.

The clock AND operator 1314 may receive the inverted flag bit F/B from the determiner 1313 and may output the ZOH clock signal ZOH_Rate to the first flip-flop 1311 .

The clock AND operator 1314 receives the second flag bit signal 2 ^nd F/B so that the toggle operation of the ZOH clock signal ZOH_Rate is not performed. Since the toggle operation of the ZOH clock signal ZOH_Rate is not performed, the first flip-flop 1311 does not output the flip-flop data FD corresponding to the pattern data PD.

The clock AND operator 1314 receives the first flag bit signal 1 ^st F/B to perform a toggle operation of the ZOH clock signal ZOH_Rate. Since the toggle operation of the ZOH clock signal ZOH_Rate is performed, the first flip-flop 1311 outputs the flip-flop data FD corresponding to the pattern data PD.

The comparator 1316 is provided from the digital converter 133 and receives high/low data H/L corresponding to the state signal of the semiconductor device under test 200, and pre-processes the high/low data H/L. The match pass/fail of the semiconductor device under test 200 is determined by comparing with the stored expected value, and a digital signal DD is provided to the match AND operator 150 according to the determination result.

Referring to FIG. 2 , the memory 132 may store pattern data PD continuously provided to the pin electronics 130 . Of the pattern data PD, pattern data PD that is not directly input to the first flip-flop 1311 (refer to FIG. 3 ) may be stored, and the stored pattern data PD may be provided to the first flip-flop 1311 . .

When the pattern data PD of more data than the storage capacity of the memory 132 is provided, the signal generator 131 provides a pattern stop request signal to the algorithm pattern generator 120 . Thereafter, according to an embodiment, the algorithm pattern generator 120 may provide the pattern data PD again according to the pattern request signal of the signal generator 131 .

The digital converter 133 receives a match detection state signal of the semiconductor element under test 200 from the semiconductor element under test 200 , and converts the state signal into high/low data H/L to generate a signal generator 131 . ) can be provided.

1 and 4 , the match AND operator 150 receives the first to n-th digital signals DD1-DDn from the signal generators 131 of each of the first to n-th pin electronics 130_1-130_n. may be provided, and output the match result signal MatchO according to the first to nth digital signals DD1-DDn to the signal generator 131 of each of the first to nth pin electronics 130_1-130_n. can provide

When all signal generators 131 of the first to n-th pin electronics 130_1-130_n provide the first to n-th digital signals DD1-DDn corresponding to a match path, the match AND operator 150 sets a high The level match result signal MatchO may be output and provided to the signal generator 131 of all the first to n-th pin electronics 130_1-130_n. A high-level match result signal MatchO means that all the semiconductor devices under test 200_1-200_n are match-passed.

5 is a ladder diagram for explaining an operation of a semiconductor device inspection apparatus according to some embodiments of the present invention. 6 to 8 are views for explaining the operation of the semiconductor device inspection apparatus according to some embodiments of the present invention.

5 and 6 , the algorithm pattern generator 120 sequentially provides the first pattern data to the fourth pattern data P1 - P4 to all the pin electronics 130 ( S111 - S114 ).

The first pattern data P1 and the fourth pattern data P4 correspond to a match command, and the second pattern data P3 and the third pattern data P4 include a write command/read command/erase command and the like. It can correspond to the program command to be executed. The order of pattern data transmission is exemplary, and the technical idea of the present invention is not limited to the transmission order of the pattern data.

The algorithm pattern generator 120 continuously provides the first pattern data to the fourth pattern data P1 - P4 to all the pin electronics 130 at regular intervals (T). The pin electronics 130 receives the first pattern data P1 at a first time t1 . Subsequent second to fourth pattern data P2-P4 may be stored in the memory 132 of the pin electronics 130 .

The pin electronics 130 determines that the first pattern data P1 corresponds to the match command ( S120 ). Accordingly, the match command signal M_CMD is input to the determination unit 1313 , and accordingly, the determination unit 1313 outputs a high level second flag bit 2 ^nd F/B, and a ZOH clock signal ZOH_Rate Makes the toggle operation of is not performed.

When it is determined that the first pattern data P1 corresponds to the match command, the signal generator 131 outputs the first output data P1_out and provides it to the semiconductor device under test 200 ( S130 ).

The semiconductor device under test 200 performs a matching operation according to the first output data P1_out ( S140 ). After the match operation of the semiconductor device under test 200 is completed, the pin electronics 130 receives a match detection signal from the semiconductor device under test 200 ( S150 ).

Referring additionally to FIG. 7 , the comparator 1316 of the pin electronics 130 provides a high-level digital signal DD to the match AND operator 150 in response to the match detection signal indicating that the match operation is complete ( S161 ).

When the match AND operator 150 receives a high level digital signal DD from all pin electronics 130 , it generates a high level match result signal MatchO and provides it to all pin electronics 130 ( S162 , S163 ). ).

The determination unit 1313 outputs a low-level first flag bit 1 ^st F/B at a second time t2 according to the high-level match result signal MatchO, and toggles the ZOH clock signal ZOH_Rate. operation is performed, and the signal generator 131 outputs output data corresponding to the pattern data after the second time t2.

The signal generator 131 provides second output data P2_out based on the second pattern data P2 while a third pattern following the first and second pattern data P1 and P2 is provided at a predetermined period. is output (S171).

The signal generator 131 outputs the third output data P3_out based on the third pattern data P2 after the output of the second output data P2_out ( S172 ).

The signal generator 131 receives the fourth pattern data P1 at the third time t3 ( S114 ). After being stored in the memory 132 of the pin electronics 130 , the fourth pattern data P1 may be provided from the memory 132 to the signal generator 131 at a third time t3 .

The pin electronics 130 determines that the fourth pattern data P4 corresponds to the match command (S180). Accordingly, the match command signal M_CMD is input to the determination unit 1313 , and accordingly, the determination unit 1313 outputs a high level second flag bit 2 ^nd F/B, and a ZOH clock signal ZOH_Rate The toggle operation of is made to be non-executed again.

When it is determined that the fourth pattern data P4 corresponds to the match command, the signal generator 131 outputs the fourth output data P4_out and provides it to the semiconductor device under test 200 ( S190 ). The semiconductor device under test 200 performs a matching operation according to the fourth output data P4_out ( S200 ).

8 is a timing diagram for explaining another operation of the pin electronics of the present invention. 6 and 8 , when a clock signal of N cycles (N clk), which is a predetermined number, is provided after a first time t1 , the determination unit 1313 provides a high-level match result signal MatchO The first flag bit 1 ^st F/B of a low level is output at the second time t2' even if it is not.

The determination unit 1313 causes the toggle operation of the ZOH clock signal ZOH_Rate to be performed after the second time t2', and the signal generator 131 outputs the pattern data after the second time t2'. output data.

Comparing the interval with the first time t1, the interval between the second time t2' and the first time t1 is greater than the interval between the second time t2 and the first time t1 in FIG. could be wider.

9 is a view for explaining the effect of the semiconductor device inspection apparatus according to some embodiments of the present invention.

Referring to FIG. 9 , the semiconductor device inspection apparatus 100 according to some embodiments of the present disclosure continuously provides a match command, and the algorithm pattern generator 120 generates pattern data corresponding to the match command by one clock. It is assumed that 200 stages of operation are performed on a cycle basis, and 100 stages of operation are performed on a clock cycle basis for the pin electronics 130 to generate output data for a match command.

The algorithm pattern generator 120 generates first pattern data corresponding to the first match command and provides it to the pin electronics 130 , and immediately responds to the second pattern data corresponding to the second match command and the third match command. The third pattern data may be sequentially generated. That is, the algorithm pattern generator 120 of the semiconductor device inspection apparatus 100 according to some embodiments of the present disclosure may perform a pipeline operation.

A time required for the semiconductor device testing apparatus 100 according to some embodiments of the present disclosure to continuously provide output data for the first to third match commands to the semiconductor device under test 200 is 1 throughput In this case, through the pipeline operation of the algorithm pattern generator 120 , the semiconductor device inspection apparatus 100 may perform an operation of about 700 stages, so that it may take about 700 clock cycles.

However, unlike the present invention, when the algorithm pattern generator 120 does not perform the pipeline operation, it may take at least about 900 clock cycles, thereby performing an inefficient operation compared to the present invention.

Through the pipeline operation of the algorithm pattern generator 120 , the pin electronics 130 can immediately perform an operation on the subsequent pattern data stored in the memory 132 after match detection, so that the Inspection efficiency can be increased by shortening inspection time.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

110: processor 120: algorithm pattern generator
130: pin electronics 150: match AND operator
131: signal generator 1311: first flip-flop
1312: second flip-flop 1313: judgment unit
1314: clock AND operator 1316: comparator

Claims (4)

an algorithmic pattern generator (ALPG) for sequentially generating first and second pattern data; and
Pin electronics that sequentially receives the first and second pattern data from the algorithm pattern generator and applies first and second output data to a semiconductor device under test (DUT) based on the first and second pattern data (Pin Electronics; PE), including,
The pin electronics includes a timing generator (TG) that outputs the second output data while receiving third pattern data subsequent to the first and second pattern data;
the pin electronics receives a match detection signal corresponding to the first output data from the semiconductor device under test;
The signal generator is
a determination unit receiving a match result signal corresponding to the match detection signal and outputting a first flag bit signal in response to the match result signal;
a first flip-flop for outputting the second pattern data as first flip-flop data in synchronization with a ZOH clock signal generated based on the first flag bit signal and a clock signal;
and a second flip-flop configured to output the first flip-flop data as the second output data in synchronization with the clock signal. According to claim 1,
The determination unit receives a match command signal and outputs a second flag bit signal in response to the match command, wherein the match command signal corresponds to the first pattern data;
and wherein the toggle operation of the ZOH clock signal is not performed based on the second flag bit signal. delete delete

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