JP2001358185A - Test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test system which can reduce the residence time for a wafers of a lot which are to be immediately tested in a test process and efficiently test small number of many kinds of wafers. SOLUTION: The test system for testing wafers comprises a waver prober for carrying wafers of devices under test to a test position, two test stations provided with electronic circuits having a prescribed number of test channels, and a testing fixture for pressing and contacting each test channel in the two test stations to each pad of a plurality of chips of the wafers carried by the wafer prober, thereby electrically connecting them. By simultaneous measurement of plurality of chips the wafers are tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test system in which two test stations are connected to a single wafer prober to reduce the period in which small lots or wafers of a lot to be urgently tested stay in a test process. .

[0002]

2. Description of the Related Art The configuration and operation of an example of the prior art will be described with reference to FIGS. As shown in FIG. 3, a test system of two stations and two probers comprises a workstation 10 and a mainframe 2
0, two test stations 30, two test fixtures 50, and two wafer probers 60. Then, the two wafers 7 of the device to be measured
Test by simultaneously measuring 0.

[0003] The workstation 10 is an input / output means that serves as an interface between the test system and a person. The main frame 20 includes a power supply unit of the test system, a computer, a test signal generation unit, a logical comparator, and the like. The test station 30 includes an electronic circuit for each test channel. The test fixture 50 is an interface between the wafer 70 of the device under test and the test station 30, and electrically connects a signal of an electronic circuit of the test station 30 to the wafer 70. The wafer prober 60 receives a control signal from the main frame 2 and transports a wafer from the cassette to below the test fixture 50.

Next, a configuration between the test station 30 and the wafer prober 60 will be described with reference to a block diagram of FIG. However, for simplicity of the drawing, only one test station 30 and one wafer prober 60 are shown, but the description is omitted because the total number of channels of the test system is merely distributed to two. The signal lines of one test station 30 are a driver DR and a comparator CP, and only one channel is shown.
Usually, it consists of several hundred channels or more.

The configuration between the test station 30 and the wafer prober 60 includes a pin electronics 31, a connector 32, a motherboard 36, a pogo pin 34, a performance board 51, a pogo pin 52, and a probe card 53 provided with a probe needle 54. It consists of:

Here, the performance board 51 and the probe card 53 can be exchanged by the pogo pins 34 and 52 to meet the purpose such as the type of wafer to be tested and the number of channels to be simultaneously tested. Also,
The components to be exchanged, the performance board 51, the pogo pins 52, and the probe card 53 are referred to as a test fixture 50.

The pin electronics 31 includes a driver DR for amplifying a test pattern to a desired voltage level, and an electronic circuit such as a comparator CP for comparing a signal from a device under test with a voltage and outputting it as a logic signal for a test channel. The connector 32 has a structure in which a large number of channels are connected to the motherboard and a signal has a small insertion force. The pogo pins 34 and 52 have an extensible tip, and are electrically connected by pressure contact. The performance board 51 mounts a probe card 53 via pogo pins 52. The probe card 53 is electrically connected to the pad of the wafer 70 by the probe needle 54.

Next, an outline of the operation of the test system will be described with reference to the block diagram of FIG. Although the internal configuration of the test system differs depending on the type of the wafer 70 to be tested, an example in which a logic wafer is tested will be described here. The pattern generator 5 generates logical data in synchronization with the basic clock signal output from the timing generator 4. In the waveform shaper 6, a test pattern is generated based on the logic data from the pattern generator and the clock signal from the timing generator 4. In the pin electronics 31, the test pattern is amplified to a desired voltage level by a driver, and the connector 32, the motherboard 36, the pogo pins 34, and the performance board 51 are amplified.
And output to the input pad of the wafer 70 via the pogo pins 52 and the probe needles 54 of the probe card 53.

Similarly, the output signal from the output pad of the wafer 70 is transmitted to the probe needle 54 of the probe card 53, the pogo pin 52, the performance board 51, and the pogo pin 3.
4, the motherboard 36, and the connector 32, and the comparator CP of the pin electronics 31 compares the voltages and outputs a logical signal. In the logical comparator 7, at the timing of the strobe signal from the timing generator 4, the logical output signal of the DUT 91 and the expected value from the pattern generator 5 are logically compared to make a pass / fail judgment.

Next, a method of testing a wafer in a conventional test system using two stations and two wafer probers will be described with reference to FIG.

In the test system shown in FIG. 5, wafers to be tested by the two test stations 30 are tested by executing one program and simultaneously measuring the same product type.

For example, when the number of channels of each test station is set to 512 and each chip is measured and tested by 256 channels, two chips of one wafer can be measured simultaneously by one wafer prober.
Four chips can be measured simultaneously with two wafer probers.

If one wafer 70 is 400 chips and two chips are simultaneously measured and tested by one wafer prober, one wafer can be tested by 200 simultaneous measurements. If two wafer probers are used, two wafers can be tested simultaneously by 200 simultaneous measurements. Therefore, for example, when the lot B and the lot C of the same type A and the same number of wafers are tested, the test system is efficient.

On the other hand, in recent years, semiconductor devices tend to be from a large number of small varieties to a small number of varieties. There is also a tendency to avoid prospective production for the purpose of inventory reduction. Therefore, the production plan of semiconductor devices frequently changes, and in the wafer test process as well, it is required to reduce the period during which wafers of small lots or urgently tested lots stay in the test process. However, the conventional test system has a problem that it is difficult to respond to a demand for testing a large number of kinds of wafers in small quantities.

[0015]

As described above, the conventional test system has a problem that it is difficult to respond to a demand for testing a small number of wafers of various kinds. Therefore, the present invention has been made in view of such a problem, and its purpose is to
An object of the present invention is to provide a test system capable of shortening a period in which a wafer of a lot to be urgently tested stays in a test process and efficiently testing a small number of wafers of various kinds.

[0016]

That is, a first aspect of the present invention, which has been made to achieve the above object, is to provide a test system for testing a wafer, wherein one wafer for transferring a wafer of a device under test to a test position is provided. A prober, two test stations provided with electronic circuits of a predetermined number of test channels, and respective pads of a plurality of chips of a wafer conveyed by the one wafer prober to each test channel of the two test stations. And a test fixture that is electrically connected by pressing and contacting the test chip, and tests a wafer by simultaneously measuring a plurality of chips.

According to a second aspect of the present invention, which has been made to achieve the above object, the test fixture is composed of two performance boards and one pressing contact means,
The gist is the test system according to the first aspect of the present invention in which the signal lines of each test channel are connected by a coaxial cable.

Furthermore, a third aspect of the present invention, which has been made to achieve the above object, is a gist of the test system according to the second aspect of the present invention, wherein the pressing contact means is a film probe unit.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
The configuration and operation will be described with reference to FIGS. As shown in FIG. 2, the test system for two stations and one wafer prober is
, A main frame 20, two test stations 30, one test fixture 40, and one wafer prober 60. Then, a plurality of chips of one wafer 70 of the device to be measured are simultaneously measured and tested.

That is, the components of the work station 10, the main frame 20, the test station 30, and the wafer prober 60 are the same as those in the related art, and only the test fixture 40 is different. Therefore, the description of the same components and operations as those in the related art has been described in the related art and will not be repeated.

The test fixture 40 comprises two performance boards 41, a plurality of coaxial cables 42, and a probe card 43, as shown in FIG. The performance board 41 has the same structure as the conventional one on the motherboard 36 side, but forms a pattern for connecting the coaxial cable 42 on the probe card 43 side.

Since the coaxial cable 42 transmits a signal, a thin coaxial cable having a characteristic impedance of, for example, 50Ω is used. For the termination of the coaxial cable 42, the center line and the external conductor are directly soldered to the pads of the board, or the coaxial cable 42 is connected to the boards of the performance board 41 and the probe card 43 by using extremely small pins and sockets.

The probe card 43 is a pressing contact means for making a pressure contact with each chip of the wafer 70 by a probe needle 44 and electrically connecting the chips. In order to simplify the drawing, the probe card 43 of FIG. 1 uses two channels from each test station 30 and the chip of the wafer 70 has two channels.
The figure shows a configuration that allows simultaneous measurement.

When the number of channels is large, a film-shaped probe unit which can easily be multi-channeled may be used as the pressing contact means instead of the probe card 43. For the film probe unit, for example,
As a method of manufacturing a probe unit (JP-A-11-511-1)
971) Since it is disclosed, detailed description is omitted. The film-shaped probe unit makes a bump (protrusion) provided on the sheet-shaped elastic body press each of the chips of the wafer 70 so as to make electrical contact with each pad.

Next, the relationship between the number of channels and simultaneous measurement will be described. In the test system of the present invention, assuming that the number of channels of each test station 30 is the same as the conventional one, the test fixture 40 which is a channel of one pressing contact means by combining the electronic circuits of the channels of the two test stations is used. Since it is used, simultaneous measurement with twice the number of channels as before can be performed with one wafer prober.

For example, assuming that the number of channels of each test station is 512, the number of channels of the probe card 43 of the pressing contact means in which the number of channels of the two test stations is the same is 1024. Further, if one wafer 70 has 400 chips and each chip is measured by 256 channels, four chips can be measured and tested simultaneously, so that one wafer prober 60 performs one measurement by 100 simultaneous measurements. The wafer can be tested.

Next, the conventional two test stations 3
FIG. 6 shows a difference in wafer test time between a test system using zero and two wafer probers 60 and a test system using two test stations 30 and one wafer prober 60 of the present invention. This will be described below with reference to FIGS.

For example, as shown in FIG. 6, when a wafer of a device under test tests a single lot B of type A,
In the conventional test system shown in FIG. 6A, one wafer prober is idle, but in the test system of the present invention shown in FIG. 6B, one wafer prober is twice as large as the conventional one. You can test the number of channels. Therefore, as shown in FIG. 6C, the wafer test of the single lot of the type A can be reduced to half the time of the test system of the present invention as compared with the conventional test system.

As shown in FIG. 7, the wafer test is performed on a lot basis.
When an urgent lot F to be urgently tested occurs in the middle of the lot C, lot D, and lot E test processes, the lot D and the lot E are compared in the conventional test system (a) shown in FIG. If the emergency lot F occurs during the test, the test of the emergency lot F is performed after the tests of the lot D and the lot E are completed, and the test system of the present invention shown in FIG. If the emergency lot F occurs during the test, the emergency lot F can be tested immediately after the completion of the lot D. Therefore, FIG.
As shown in (C), when an urgent lot F to be urgently tested occurs in the middle of the test process, the test of the urgent lot F can be started earlier in the test system of the present invention as compared with the conventional test system. Therefore, the waiting time can be reduced, and the test time of the emergency lot F itself is 1
/ 2 time.

As shown in FIG. 8, when the type of wafer test target is an odd lot, for example, when testing lots B, C, D, and 3 lots of type A,
In the conventional test system shown in FIG. 8A, one of the wafer probers is in an idle state when testing the last odd-numbered lot D. However, in the test system of the present invention shown in FIG. One wafer prober can test twice the number of channels as before. Accordingly, as shown in FIG. 8C, in the case of an odd lot, the test system of the test system of the present invention finishes the test time of the last odd lot D in half the time compared to the conventional test system. I do.

As shown in FIG. 9, the wafer test is performed for each lot mounted on a fixed number of cassettes. If a wafer of the lot has a fraction, for example,
In the case where the number of wafers in each of the lots B, C, and D of the type A is 25 and the number of wafers in the fraction lot E is 5, the conventional test system shown in FIG. And the test of lot E require the same test time as the case of no fraction, and the test system of the present invention shown in FIG. Save time. Therefore,
As shown in FIG. 9C, when a lot of wafers has a fraction, the test time of the last fraction lot is reduced to the fractional number of wafers in the test system of the present invention as compared with the conventional test system. The time can be shortened in proportion.

By the way, compared with the conventional test system and the test system of the present invention, the test time for testing even number lot wafers of the same type is the same, but the conventional test system requires two wafer probers. In contrast, only one test system is required in the test system of the present invention, so that the cost of the wafer prober can be reduced by half. Further, the test system of the present invention can be applied to a wafer to be tested without limitation even if the wafer to be tested is logic, memory, mixed analog / digital, or other types.

[0034]

The present invention is embodied in the form described above and has the following effects. That is,
Two test stations can be connected to one wafer prober to test multiple chips on a wafer, so that the period during which wafers of small lots or urgently tested lots stay in the test process can be shortened. This has the effect of reducing the cost of the wafer prober by half.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of a test system according to the present invention.

FIG. 2 is a configuration diagram of a test system according to the present invention.

FIG. 3 is a configuration diagram of a conventional test system.

FIG. 4 is a block diagram of a main frame of the test system and a main part configuration diagram.

FIG. 5 is a diagram illustrating a wafer test method using a conventional test system.

FIG. 6 is a comparison diagram of test times between a conventional case and the present invention in the case of a single lot.

FIG. 7 is a comparison diagram of test times between the conventional case and the present invention when there is an emergency lot.

FIG. 8 is a comparison diagram of test times between the conventional example and the present invention in the case of odd lots.

FIG. 9 is a comparison diagram of the test time between the related art and the present invention when there is a fraction lot.

[Explanation of symbols]

 Reference Signs List 4 timing generator 5 pattern generator 6 waveform shaper 7 logical comparator 10 workstation 20 mainframe 30 station 31 pin electronics 32 connector 34 pogo pin 36 motherboard 40 test fixture 41 performance board 42 coaxial cable 43 probe card 44 probe needle 50 Test Fixture 51 Performance Board 52 Pogo Pin 53 Probe Card 54 Probe Needle 60 Wafer Prober 70 Wafer

Claims (3)

[Claims] 1. A test system for testing a wafer, comprising: a wafer prober for transferring a wafer of a device under test to a test position; two test stations provided with an electronic circuit having a predetermined number of test channels; A test fixture for electrically connecting each test channel of the two test stations with each pad of a plurality of chips of the wafer conveyed by the one wafer prober to electrically connect the test channels. A test system characterized by testing a wafer by measurement. 2. The test system according to claim 1, wherein the test fixture comprises two performance boards and one pressing contact means, and connects the signal lines of each test channel by a coaxial cable. 3. The test system according to claim 2, wherein the pressing contact means is a film probe unit.