CN112213621B - Wafer testing system and wafer testing method - Google Patents
Wafer testing system and wafer testing method Download PDFInfo
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- CN112213621B CN112213621B CN202010999829.2A CN202010999829A CN112213621B CN 112213621 B CN112213621 B CN 112213621B CN 202010999829 A CN202010999829 A CN 202010999829A CN 112213621 B CN112213621 B CN 112213621B
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention provides a wafer test system and a test method, wherein the system comprises: the probe card, the ARM processor and the main control unit are connected in sequence, and the probe card is provided with at least two contact points; the ARM processor monitors the test state information of each contact and transmits the test state information to the main control unit; receiving a start-stop command of the main control unit to control the start, pause or end of each contact; the main control unit obtains a start-stop command according to the test state information; the start-stop command comprises: controlling the contact of the previous test item to pause until all contacts finish the test of the previous test item, and starting all contacts to carry out the current test item; controlling the contact points which finish the current test item to pause until all the contact points finish the test of the current test item, and starting all the contact points to carry out the next test item; and controlling all the contacts to finish the test. The synchronous completion of the test items among different contacts ensures that different contacts are in the same test item at the same time, enhances the precision of wafer test and improves the test yield.
Description
Technical Field
The present invention relates to the field of semiconductor testing, and more particularly, to a wafer testing system and a wafer testing method.
Background
The semiconductor manufacturing process generally includes integrated circuit design, wafer fabrication, wafer test, wafer dicing, chip packaging, and finished chip test. The wafer test is a test after the wafer is manufactured, and is used for verifying whether each chip (DIE) on the wafer meets device characteristics and other design specifications. The wafer refers to a chip used for manufacturing a semiconductor integrated circuit, and the wafer is called a wafer because the wafer is circular in shape, and various circuit element structures can be manufactured on the chip to form an IC product with a specific electrical function. The technical test of the wafer is very strict, and mainly verifies whether the circuit of the product is good or not, and verifies whether the function of the driving wafer meets the requirements of terminal application or not.
The test of the driving wafer is mainly performed by using a dedicated tester, and in the test, a probe card having a plurality of probes is generally used, a test pad is disposed on a chip, the probes of the probe card and the test pads of the chips on the wafer are in contact with each other to form an electrical connection for performing an electrical test, so that the test of the plurality of chips in the wafer is respectively performed through a plurality of contacts (sites) on the probe card. The conventional method is that all the contacts in the wafer test are independently tested in sequence at the same time, and the different contacts do not consider what test items are done with each other and interfere with each other to cause measurement deviation. Because the production quality of different tested chips is different and/or the process running speed of the test contact points of the tested chips is different, the test time difference of different contact points of the wafer test is larger, so that the different contact points can interfere with each other when testing different test items, and the yield loss is caused. For example, when a part of the contacts of the wafer test items of high voltage and large current, and a part of the contacts are testing items of low voltage and small current, that is, different nodes are in different test items at the same time, at this time, a test item signal of low voltage and small current is affected by EMI of a test item signal of high voltage and large current, and a measurement error occurs to cause a wafer test result over kill, that is, a chip passing the test is tested as a test fail, so that yield loss is caused.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a wafer testing system and a wafer testing method, which are used to solve the problems of excessive yield misjudgment (over kill) and yield loss of the wafer testing result caused by the measurement error in the wafer testing in the prior art, in which all the contacts on the probe card are independently tested in sequence at the same time.
To achieve the above and other related objects, the present invention provides a wafer test system, comprising: the system comprises a probe card, an ARM processor and a main control unit;
the probe card is provided with at least two contact points (sites), and each contact point is respectively connected with different chips to be tested;
the ARM processor is connected with the probe card and used for monitoring the test state information of the tested chip corresponding to each contact and transmitting the test state information to the main control unit; simultaneously receiving a start-stop command of the main control unit to control the start, pause or end of each contact according to the start-stop command;
the main control unit is connected with the ARM processor and used for receiving the test state information transmitted by the ARM processor and calculating to obtain the start-stop command according to the test state information; the start-stop command comprises: the ARM processor controls the contact points which finish the previous test item to pause and wait until all the contact points finish the test of the previous test item, and all the contact points are opened to carry out the current test item; the ARM processor controls the contact points which finish the current test item to pause and wait until all the contact points finish the test of the current test item, and all the contact points are opened to carry out the next test item; and when all the test items of the tested chip are tested, the start-stop command controls all the contacts to finish the test through the ARM processor.
Optionally, the previous test item is a low-voltage test item, the current test item is a high-voltage test item, and the next test item is a low-voltage test item.
Further, the high voltage of the high voltage test item is greater than 8 volts.
Optionally, the chip under test includes an arithmetic logic chip, a flash memory chip or a sensor chip; the probe card comprises at least one driving circuit board, and each driving circuit board is provided with at least one contact.
Further, the probe card comprises 32 driver circuit boards, and each driver circuit board is provided with 2 contacts.
The invention also provides a wafer testing method, which comprises the following steps:
providing a wafer to be tested and the wafer test system of any one of the above items, wherein the wafer to be tested is provided with at least two chips to be tested;
connecting the probe card with the tested chip, wherein each contact is respectively connected with different tested chips;
starting the wafer test system, sending a starting and stopping command to the ARM processor by the main control unit, and receiving the starting and stopping command by the ARM processor to control all the contacts to be opened to start testing the tested chip;
the ARM processor monitors test state information of the tested chip corresponding to each contact and transmits the test state information to the main control unit, the main control unit calculates and obtains the start-stop command according to the test state information, the start-stop command controls the contact completing a previous test item to pause and wait through the ARM processor until all the contacts complete the test of the previous test item, all the contacts are started to carry out the current test item, then the ARM processor controls the contact completing the current test item to pause and wait until all the contacts complete the test of the current test item, and all the contacts are started to carry out the next test item;
and circulating the previous step until all the test items of the tested chip are tested, and controlling all the contacts to finish the test by the start-stop command through the ARM processor.
Optionally, the previous test item is a low-voltage test item, the current test item is a high-voltage test item, and the next test item is a low-voltage test item.
Further, the high voltage of the high voltage test item is greater than 8 volts.
Optionally, the chip under test includes an arithmetic logic chip, a flash memory chip or a sensor chip; the probe card comprises at least one driving circuit board, and each driving circuit board is provided with at least one contact.
Further, the probe card comprises 32 driver circuit boards, and each driver circuit board is provided with 2 contacts.
As described above, the wafer test system and the wafer test method of the invention can realize synchronous completion of test items between different contacts in the wafer test process, and ensure that different contacts are in the same test item at the same time, thereby reducing EMI influence generated by different contacts in different test items at the same time, enhancing the wafer test precision and improving the test yield.
Drawings
FIG. 1 shows a MAP of a tested die in a wafer under test.
FIG. 2 is a diagram showing the position of a plurality of probes on two contacts of a probe card.
FIG. 3 is a flowchart illustrating a wafer testing method according to an embodiment of the present invention.
FIG. 4 is a schematic diagram showing the operation states of the high voltage test items of different contacts when the tested chip is in a certain high voltage test item in the wafer testing method of the present invention.
Description of the element reference numerals
10 wafer to be tested
11 chip to be tested
12 Probe
13 support layer
14 electric layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed according to actual needs, and the layout of the components may be more complicated.
The conventional wafer test method is to complete the test of the tested chips through all the contacts (sites) on the probe card (probe card) independently and sequentially, and no consideration is given to what test items are done between different contacts, which will not interfere with each other to cause measurement deviation, because different tested chips have different production quality and/or different process running speeds of the test contacts belonging to the tested chips, so the test time difference of different contacts of the wafer test is large, when some contacts test high-voltage and large-current test items, some contacts are testing small-voltage and small-current test items, that is, different nodes are in different test items at the same time, as shown in fig. 1, a MAP diagram of a wafer 10 to be tested is shown, for example, two tested chips 11 adjacent in a dotted frame may belong to different contacts, based on the mutual independence of the contact tests, the two neighboring chips 11 under test may be in different test items. As shown in fig. 2, it is known that a plurality of probes 12 on a probe card are arranged in parallel, and the probes have a certain length, which is not negligible, for example, as shown in fig. 2, the probes have a length of 1105 μm, because all the probes 12 are arranged in parallel, the probes between two adjacent contacts can generate parasitic capacitance during testing, and the parasitic effect is more obvious as the probe length is longer, when two contacts are respectively in a large-voltage large-current test item and a small-voltage small-current test item, significant EMI influence is generated on the small-voltage small-current test item, and measurement errors occur to cause an excessive yield misjudgment (over kill) of a wafer test result. Table 1 below shows current data obtained by continuously testing 36 bit lines (WL) for 8 times using the test parameters of the wafer test system in table 2, where the wafer test system in table 2 uses model T5830P, 288 channels using 2 power channels, 24 driver boards, and 6 probe points as a module, and selects a VSIM (i.e., input voltage value, measurement current value) measurement mode, where the voltage input range is-10V to +32V, the current measurement range is-80 uA to +80uA, and the current measurement accuracy nA excludes the influence of machine test accuracy, and the test deviation is caused by interference between different contacts. It can be seen from the table that the interference causes the current measurement error to far exceed the deviation range allowed by the precision, reducing the test precision and causing the yield loss of the test.
TABLE 1
TABLE 2 test parameters for wafer test systems
Based on the above problems, the inventors have conducted detailed research and analysis to provide a wafer testing system and a wafer testing method based on the system.
The wafer test system comprises: the system comprises a probe card, an ARM processor and a main control unit;
the probe card is provided with at least two contact points (sites), and each contact point is respectively connected with different chips to be tested;
the ARM processor is connected with the probe card and used for monitoring the test state information of the tested chip corresponding to each contact and transmitting the test state information to the main control unit; simultaneously receiving a start-stop command of the main control unit to control the start, pause or end of each contact according to the start-stop command;
the main control unit is connected with the ARM processor and used for receiving the test state information transmitted by the ARM processor and calculating to obtain the start-stop command according to the test state information; the start-stop command comprises: the ARM processor controls the contact points which finish the previous test item to pause and wait until all the contact points finish the test of the previous test item, and all the contact points are opened to carry out the current test item; the ARM processor controls the contact points which finish the current test item to pause and wait until all the contact points finish the test of the current test item, and all the contact points are opened to carry out the next test item; and when all the test items of the tested chip are tested, the start-stop command controls all the contacts to finish the test through the ARM processor.
By the wafer test system, synchronous completion of test items among different contacts can be realized, and the different contacts are ensured to be in the same test item at the same time, so that EMI (electro-magnetic interference) influence generated when the different contacts are in different test items at the same time is reduced, the wafer test precision is enhanced, and the test yield is improved.
Because the EMI influence of the test item signal with small voltage and small current by the test item signal with large voltage and large current is more obvious, on the basis of saving the production cost, the high-voltage test item between two low-voltage test items can be synchronously completed between different contacts, even if all the contacts are in the test of the high-voltage test item at the same time, thereby avoiding the high-voltage test item and the low-voltage test item existing at the same time between different contacts and reducing the EMI influence.
By way of example, the high voltage of the high voltage test item may be defined herein as a voltage greater than 8 volts, with EMI effects resulting from voltages greater than 8 volts being increasingly significant.
As an example, the wafer test system of the present embodiment is suitable for a chip under test including not only low-voltage test items but also high-voltage test items in any wafer test items, such as an arithmetic logic chip, a flash memory chip, a sensor chip, and the like, where wafer test items of such chips are prone to generate EMI influence during a test process.
By way of example, the probe card includes at least one driver circuit board, each driver circuit board having at least one of the contacts thereon, e.g., when the probe card includes only one driver circuit board, then the driver circuit board has at least two of the contacts thereon; when the probe card comprises at least two driving circuits, each driving circuit board is provided with at least one contact. It is common that the probe card includes 32 driver circuit boards, each of which has 2 contacts, but the design can be made according to the specific situation as long as the probe card has at least two contacts.
The embodiment further provides a wafer testing method, which is implemented based on the wafer testing system, and the wafer testing method includes:
step 1): providing a wafer to be tested and the wafer test system, wherein the wafer to be tested is provided with at least two chips to be tested;
step 2): connecting the probe card with the tested chip, wherein each contact is respectively connected with different tested chips;
step 3): starting the wafer test system, sending a starting and stopping command to the ARM processor by the main control unit, and receiving the starting and stopping command by the ARM processor to control all the contacts to be opened to start testing the tested chip;
step 4): the ARM processor monitors test state information of the tested chip corresponding to each contact and transmits the test state information to the main control unit, the main control unit calculates and obtains the start-stop command according to the test state information, the start-stop command controls the contact completing a previous test item to pause and wait through the ARM processor until all the contacts complete the test of the previous test item, all the contacts are started to carry out the current test item, then the ARM processor controls the contact completing the current test item to pause and wait until all the contacts complete the test of the current test item, and all the contacts are started to carry out the next test item;
step 5): and (4) circulating the step 4) until all the test items of the tested chip are tested, and controlling all the contacts to finish the test by the start-stop command through the ARM processor.
As an example, only the high-voltage test item between two low-voltage test items may be set to be completed synchronously between different contacts, that is, the previous test item is the low-voltage test item, the current test item is the high-voltage test item, and the next test item is the low-voltage test item.
Here, the high voltage of the high voltage test item is a voltage that can generate significant EMI influence at the time of test, and the voltage may be defined as a voltage greater than 8 volts, and the EMI influence due to the voltage greater than 8 volts is gradually significant.
As an example, the wafer testing method of the present embodiment is suitable for a chip to be tested, such as an arithmetic logic chip, a flash memory chip, a sensor chip, etc., which includes not only low-voltage test items but also high-voltage test items in any wafer test items, and the wafer test items of such chips are prone to generate EMI influence during the testing process.
By way of example, the probe card includes at least one driver circuit board, each driver circuit board having at least one of the contacts thereon, e.g., when the probe card includes only one driver circuit board, then the driver circuit board has at least two of the contacts thereon; when the probe card comprises at least two driving circuits, each driving circuit board is provided with at least one contact. It is common that the probe card includes 32 driver circuit boards, each of which has 2 contacts, but the design can be made according to the specific situation as long as the probe card has at least two contacts.
As shown in fig. 3 and 4, as an example, the wafer testing method of the embodiment is described by taking the probe card having three contacts (sites), and the wafer to be tested has three testing items of a low voltage testing item, a high voltage testing item, and a low voltage testing item in sequence, as known by those skilled in the art, in an actual wafer test, the probe card may have more nodes, and the wafer to be tested has more testing items, for example, a typical flash memory chip may have 40 to 80 testing items, and the probe card may have 16, 32, 64 or more nodes.
Firstly, completing the early preparation work of wafer testing, namely providing a wafer to be tested and the wafer testing system, and completing the connection between the wafer to be tested and the wafer testing system; then, the wafer test system is started, the main control unit (such as a CPU) sends a starting and stopping command for starting to the ARM processor, and the ARM processor receives the starting and stopping command for starting to control all the contact points 1, 2 and 3 to be started to test the tested chip; firstly, testing a first low-voltage test item, wherein a contact 1 finishes the first low-voltage test item after the time T1, a contact 2 finishes the first low-voltage test item after the time T2, a contact 3 finishes the first low-voltage test item after the time T3, T1 < T2 < T3, in the process, the ARM processor monitors the test state information of the chip to be tested corresponding to each contact and transmits the test state information to the main control unit, the main control unit obtains the start-stop command according to the test state information, the start-stop command controls the contact 1 and the contact 2 to pause and wait after finishing the corresponding first low-voltage test item through the ARM processor, waits for the first low-voltage test item of the contact 3 to be finished until the first low-voltage test item of the contact 3 is finished, and the main control unit obtains the start-stop command according to the test state information transmitted by the ARM processor, the ARM processor controls the connection point 1, the connection point 2 and the connection point 3 to be opened to carry out a second high-voltage test item; in the test process of the second high-voltage test item, the ARM processor monitors the test state information of the tested chip corresponding to each contact, and transmits the test state information to the main control unit, the main control unit calculates to obtain the start-stop command according to the test state information, the start-stop command controls the contact of the completed second high-voltage test item to pause and wait through the ARM processor (as shown in fig. 4, the contact 2 and the contact 3 complete the second high-voltage test item first, so the contact 2 and the contact 3 pause and wait for the contact 1 to complete the second high-voltage test item after completing the second high-voltage test item) until all the contacts complete the test of the second high-voltage test item, and the main control unit calculates to obtain the start-stop command according to the test state information transmitted by the ARM processor to control the contact 1 through the ARM processor, The contact 2 and the contact 3 are opened to carry out a low-voltage test item of the third item; and finally, the three test items of the contact 1, the contact 2 and the contact 3 are all tested, and the main control unit controls the contact 1, the contact 2 and the contact 3 to finish the test through the ARM processor.
By the wafer testing method, the synchronous completion of the test items among different contacts can be realized in the wafer testing process, and the different contacts are ensured to be in the same test item at the same time, so that the EMI influence generated when the different contacts are in different test items at the same time is reduced, the wafer testing precision is enhanced, and the testing yield is improved.
It should be noted that, all the modules involved in this embodiment are logic modules, and in practical application, one logic unit may be one physical unit, may also be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, a unit which is not so closely related to solve the technical problem proposed by the present invention is not introduced in the present embodiment, but it does not indicate that there is no other unit in the present embodiment.
In summary, the present invention provides a wafer testing system and a wafer testing method, which can achieve synchronous completion of test items between different contacts during a wafer testing process, and ensure that different contacts are in the same test item at the same time, thereby reducing EMI influence caused by different contacts being in different test items at the same time, enhancing wafer testing accuracy, and improving testing yield. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A wafer test system, comprising: the system comprises a probe card, an ARM processor and a main control unit;
the probe card is provided with at least two contact points, and each contact point is connected with different chips to be tested respectively;
the ARM processor is connected with the probe card and used for monitoring the test state information of the tested chip corresponding to each contact and transmitting the test state information to the main control unit; simultaneously receiving a start-stop command of the main control unit to control the start, pause or end of each contact according to the start-stop command;
the main control unit is connected with the ARM processor and used for receiving the test state information transmitted by the ARM processor and calculating to obtain the start-stop command according to the test state information; the start-stop command comprises: the ARM processor controls the contact points which finish the previous test item to pause and wait until all the contact points finish the test of the previous test item, and all the contact points are opened to carry out the current test item; the ARM processor controls the contact points which finish the current test item to pause and wait until all the contact points finish the test of the current test item, and all the contact points are opened to carry out the next test item; when all the test items of the tested chip are tested, the start-stop command controls all the contacts to finish the test through the ARM processor; wherein, the former test item is a low-voltage test item, the current test item is a high-voltage test item, and the next test item is a low-voltage test item.
2. The wafer test system of claim 1, wherein: the high voltage of the high voltage test item is greater than 8 volts.
3. The wafer test system of claim 1, wherein: the chip to be tested comprises an operational logic chip, a flash memory chip or a sensor chip; the probe card comprises at least one driving circuit board, and each driving circuit board is provided with at least one contact.
4. The wafer test system of claim 3, wherein: the probe card comprises 32 driver circuit boards, and each driver circuit board is provided with 2 contacts.
5. A wafer testing method is characterized by comprising the following steps:
providing a wafer to be tested and the wafer testing system according to any one of claims 1 to 4, wherein the wafer to be tested has at least two chips to be tested;
connecting the probe card with the tested chip, wherein each contact is respectively connected with different tested chips;
starting the wafer test system, sending a starting and stopping command to the ARM processor by the main control unit, and receiving the starting and stopping command by the ARM processor to control all the contacts to be opened to start testing the tested chip;
the ARM processor monitors the test state information of the tested chip corresponding to each contact, and transmitting the test state information to the main control unit, the main control unit calculates and obtains the start-stop command according to the test state information, the start-stop command controls the contact which finishes the previous test item to suspend waiting through the ARM processor until all the contacts finish the test of the previous test item, all the contacts are started to carry out the current test item, then the ARM processor controls the contact points which finish the current test item to pause and wait until all the contact points finish the test of the current test item, all the contact points are started to carry out the next test item, wherein the previous test item is a low-voltage test item, the current test item is a high-voltage test item, and the next test item is a low-voltage test item;
and circulating the previous step until all the test items of the tested chip are tested, and controlling all the contacts to finish the test by the start-stop command through the ARM processor.
6. The wafer testing method as claimed in claim 5, wherein: the high voltage of the high voltage test item is greater than 8 volts.
7. The wafer testing method as claimed in claim 5, wherein: the chip to be tested comprises an operational logic chip, a flash memory chip or a sensor chip; the probe card comprises at least one driving circuit board, and each driving circuit board is provided with at least one contact.
8. The wafer testing method as claimed in claim 7, wherein: the probe card comprises 32 driver circuit boards, and each driver circuit board is provided with 2 contacts.
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