JPH0354842A - Test of integrated circuit element - Google Patents

Abstract

PURPOSE:To contrive a reliable test for the connection state of all integrated circuit elements by a method wherein two pieces of test pads are provided, the test pad on one side of the test pads is connected to one conductor wire, a plurality of conductor wires other than the above one conductor wire are connected to other test pad and the disconnection of leads to correspond to the bonding state of IC pads is tested by a self-checking function. CONSTITUTION:First, switching gates A1 to An are all turned-OFF by a scan circuit 10. Then, a signal is sent from the circuit 10 to switching gates B1 to Bn and the gates B1 to Bn are turned-ON in order in a prescribed order. In this state, a continuity check between test pads 4a and 4b is conducted. Thereby, the disconnection test of leads 3 to correspond to the bonding state of IC pads C1 to Cn and Cn+1 can be conducted. Accordingly, a reliable test for the connection state of all integrated circuit elements can be conducted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for testing an integrated circuit device, and in particular, a method for testing the connection state of an integrated circuit device after it is connected to a TAB tape serving as an integrated circuit holding means. The present invention relates to a method for testing integrated circuit devices suitable for testing.

[Conventional technology]

Integrated circuits (rlc) cut out from silicon wafers
It's called J. ) TAB as one of the chip mounting technologies
(Tape Automa ted Bonding)
The method is known (for example, Nikkei Microdevice l9
(See September 1987 issue, pages 99-106). This T is shown in Figure 4.
This figure shows the IC chip i bonded using the AB method and its surrounding area. In the same figure, IC Tinop l
is bonded and held on a TAB tape 2 made of polyimide whose longitudinal direction is in the X direction. This TAB
Leads (conductor wires) 3 for bonding are printed on the tape 2 in advance at equal intervals. During bonding, the TAB tape 2 is sent out in the X direction in accordance with the movement of a large number of IC chips arranged in a straight line, using a principle similar to the frame-by-frame feeding of a projection film, and the leads 3 and IC chips are placed in a predetermined position on the bonding tool. 1 is transferred, the inside of the lead 3 (inner lead) and a plurality of connection terminals (panods) provided on the IC chip are bonded (connected Vf.) together. When one bonding is completed, the next lead and IC
The bonding tool is transferred to a predetermined position of the bonding tool and bonding is performed, and the same operation is repeated thereafter. As a result, a TAB table 2 in which a large number of bonded IC chips 1 are arranged in the X direction as shown in FIG. 4 is obtained. As a method for testing the IC chimp 1 loaded onto the TAB tape 2, a method using a test socket is known. Figure 5 shows this test socket 5,
A schematic sectional view of the TAB tape 12 attached to this is shown.

This method uses the upper part 5a and lower part 5b of the test socket 5.
The TAB tape 2 on which the IC chip 1 is placed is sandwiched between the contact bin 6 provided on the lower surface of the upper part 5a of the test socket and the test pad 4 on the TAB tape 2.
and a predetermined voltage and voltage via the external bottle 7.
The electrical and operational characteristics of the IC chip are tested by supplying a signal to the IC chip. Furthermore, this method can simultaneously test whether the bonding between the IC chip 1 and the leads 3 is good or bad.

Another method for testing the IC tip 1 bonded to the TAB tape 2 is to use a blow bar. This is a method of testing the electrical characteristics and operating characteristics of the IC chip by bringing a bloper (a probe for receiving test signals) into direct contact with the test bath 4 without using the test socket 5 as shown in Fig. 5. . This method also uses the IC chip 1 and lead 3, similar to the method using a test socket.
It is possible to detect bonding defects with

In addition to testing after bonding to the TAB tape 2 as described above, a scan test method is known as one of the methods for testing the operation of the IC chip 1 before bonding to the TAB tape 2. This method is I
Inside the C chip, a scan test circuit is built in separately from the circuit that performs the original function of the 1C chip, and the scan circuit that monitors this scan test circuit tests the rC path (the part where the bonding bump is formed) and the internal The test is performed by sequentially turning on and off (scanning) switching gates provided between the circuit and the circuit in a predetermined pattern. According to this method, it is not necessary to contact the test blooper with all IC panels, but only with a small number of IC panels (for example, IC pads for IO pins for a 200-bin IC), and the scan circuit is used to scan the test blooper. By switching the isochiing gates, it is possible to perform test 1 which is equivalent to bringing a blow bar into contact with all IC pads.

[The invention tries to solve i! l title]

By the way, in the case of the test method using the test socket 5 shown in FIG. 5, since the contact between the contact bottle 6 and the test socket 4 is mechanical, the TAB tape 2 is A certain distance is required between each printed test pad. On the other hand, as the distance between the test pads increases, a wider TAB table 2 is inevitably required, and an expensive polyimide TAB table 2 is required.
A large amount of AB tape must be used, resulting in high costs.

Looking at a specific example, if the test pad spacing is 0.25 mm for a tC of 200 pins, the TAB tape needs to be 35n+m wide. However, considering test reliability, etc., it is necessary to set the test pad spacing to about 0.5 mm, and in this case, 75 mm wide TAB tape must be used, which increases the cost accordingly. This leads to an increase in the price of individual ICs. In addition, when ICs have more than 200 pins, in addition to the problem of spacing between test pads, the wiring and structure of the leads and test bands printed on the TAB tape become complicated, and it is also difficult to ensure that the contact pins and test pads are in contact with each other. It becomes difficult. In particular, in line with the recent trend toward increasing the number of pins, 300 bins in the future,
When a multi-bin IC with 500 pins appeared, TA
B-tape cost, test socket cost, test cost, and test reliability are major issues.

The same problem as above arises with the method of testing using a blow bar, and the test equipment using the blow bar becomes large-scale, increasing the test cost.

On the other hand, in the case of the scan test method, the above problem does not occur, but since the scan test method is a test method before bonding the IC chip,
The connection state between the IC pad and the lead of the TAB tape that occurs during bonding cannot be tested. It is an object of the present invention to provide a method for testing an integrated circuit element that can reliably test the connection status of all integrated circuit elements (particularly poor connections and oven failures), disconnection of the conductor, etc. by connecting to the conductor of a circuit holding means. purpose.

[Means to solve the problem]

To achieve the above object, the present invention connects a plurality of connection terminals of an integrated circuit element having a self-diagnosis function therein to a plurality of conductive wires provided on an integrated circuit holding means for holding the integrated circuit element. In the method for testing an integrated circuit device, the connection state of the integrated circuit device is tested after the integrated circuit device has been tested, comprising: providing first and second test pads on the integrated circuit holding means, and connecting the first test pad to one conducting wire. death,
A plurality of conductive wires other than the one R wire are connected to the second test pad, and the self-diagnosis function tests the first and second test pads.
The connection status of each of the plurality of connection terminals and the plurality of conductive wires is tested through the test pad. [Function] According to the present invention, the plurality of paths connected from the plurality of connection terminals to the original circuit of the integrated circuit element are temporarily turned on in a predetermined order by the self-diagnosis a function by the above fJI'ifl, As a result, the first test pad and the second test pad are connected via the path that is turned on.
In such a connected state, by testing the conduction state between the No. 1 test pad and the second test pad, it is possible to detect a connection failure at the connection terminal corresponding to the path turned on. By sequentially turning on multiple paths using the self-diagnosis function, the first and second
It is possible to test connections at all connection terminals by simply using the test pads. For this reason, it is no longer necessary to provide the same number of test pads as the number of connection terminals (number of pins) on the integrated circuit holding means as in the conventional method.
In addition to the first and second test pads, only the test bands necessary for the self-diagnosis function may be provided.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. Similar to FIG. 4, FIG. 1 shows a state in which each connection terminal of an IC chip 1, which is one of the integrated circuit elements, is bonded to leads (conductor wires) 3 printed on a TAB tape 2, which serves as an integrated circuit holding means. It shows. In addition, in FIG. 1, the same reference numerals are given to the same parts as in FIG. 4, and detailed explanation thereof will be omitted. In this embodiment, the arrangement of the test pads and pads of the conventional TAB tape 2 shown in FIG. 4 is changed to the arrangement shown in FIG. (Only the corresponding lead placement is shown.) That is, in the conventional method, a large number of test pads are provided on the TAB tape 2 as shown in FIG. 4, but in this embodiment, two test pads 4a and 4b are provided as shown in FIG. All leads 3 other than the lead 3a that is provided and connected to the test pad 4a
Connect b to test pad 4b. FIG. 2 is a block diagram showing the connection state between the test pads 4a and 4b of FIG. 1 and the IC chip 1, and the internal circuit of the IC chip 1. As shown in FIG. In the same figure, one end is connected to the test buffed 4
IC pads (connection terminals) C+, Cz, . . . , C, 1 (
Here, n corresponds to the number of pins of the IC. ) and an IC pad C, . . . for connecting the other end of the lead 3a connected to the test pad 4a. It has I.

Further, inside the IC chip 1, a scan circuit 10, switching gates A1 to A-'B+ to B, and their peripheral circuits are pre-installed during the manufacture of the IC chip.

The scan circuit 10 is used to perform a scan test on the IC chip before bonding, but in this embodiment it is also used to test the connection state between the leads 3 and the IC chip 1 after bonding. Switching gate A, ~A0 and switching gate Bl-B,
, are sequentially turned on or off by signals sent from the scan circuit 10, and the circuits 11+ to 1l,l and the IC puffed C+" perform the original functions of the RC chi knob.
The scan circuit 10 also has a test pad 13a for supplying power to the scan circuit IO via the rc pads 12a and 12b.
- Connected to 13b. Although not shown in FIG. 2, the IC chip 1 is provided with energy for performing a scan test before bonding and a circuit for supplying or detecting a predetermined signal. However, since this circuit is not directly related to testing the connection state of the IG pad after bonding, its explanation will be omitted here.

Next, a procedure for testing the connection state after bonding will be described. First, the scanning circuit IO turns off all the switching gates A I "A," (
That is, the IC paths C, -Cn and the circuits 11+ to 11, , are quickly disconnected. ). Next, signals are sent from the scan circuit 10 to the switching gates 81-B, , and as shown in FIG. -I3, are sequentially turned on in a predetermined order. For example, when the switching gate BI is on, the test pad 4a is connected to the test pad 4b via the IC pad C p *+, the switching gates B, . By checking the continuity between the test panodes 4a and 4b in this state, the IC bathodes C1 and C Il*
, and the corresponding bonding condition test 3
A disconnection test can be performed. In the same manner as below, switch gate B. ~ By sequentially turning on B7, the corresponding IC panod C! A test for the bonding of ~C7 and a UT line test for each corresponding lead 3 can be performed.

As mentioned above, by using the scan circuit IO even after bonding the IC chip 1 to the TAB tape 2, the test pad required for the post-bonding test is 4a.
・There are only four, 4b-13a-13b, which makes it possible to test the bonding of all IC pads. Therefore, compared to the conventional method using a test socket (see FIG. 5) or the method using a prober, the number of required test pads is extremely small.

〔Effect of the invention〕

As described above, according to the present invention, the number of test pads to be provided on the TAB tape is extremely reduced compared to conventional methods, so the number of mechanical contact points with external circuits during testing is greatly reduced, and the number of test pads to be provided on the TAB tape is significantly reduced. It is possible to secure a sufficient distance between the test puffs and the contact pins, and to ensure the contact between the test puff and the contact pins, thereby improving the reliability of the test. Furthermore, since the number of test panels required is extremely small, even if the number of pins of an integrated circuit increases, the area of TAB tape used will not be required as much as in the past, which means that the expensive 'T A
The amount of B-table used can be reduced, and manufacturing costs can also be reduced by 1.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing a TAB tape used in an embodiment of the present invention and an IC chip connected to the TAB tape, and FIG. Figure 3 is a timing chart showing the operation of the switching gate; Figure 4 is the test pad and IC chinobu on the TAB tape used in the conventional test method; and Figure 5 shows the connection state of the test socket 1.
・It is a schematic cross-sectional view of a state in which TAB tape is sandwiched. 1...! J product circuit (IC) chip, 2-...TAB tape, 3, 3a, 3b...lead,
4.4a.4b.13a.13b. ．． ．． test pad,
5... Test socket, 6... Contact pin, 7... External bin, 10... Scan circuit, 11. ~1! I1...Circuit, 12a'l2b-C. ~Cfi. ．． --- IC Pasodo, A. -AII -Bl ~B, 1...Sui notching gate.

Claims (1)

[Claims] After connecting a plurality of connection terminals of an integrated circuit element having a self-diagnosis function therein to a plurality of conductive wires provided on an integrated circuit holding means for holding the integrated circuit element, the integrated circuit In a method for testing an integrated circuit device for testing the connection state of the device, first and second test pads are provided on the integrated circuit holding means, the first test pad and one conducting wire are connected,
A plurality of conductive wires other than the one conductive wire are connected to the second test pad, and the self-diagnosis function tests the first and second test pads.
1. A method for testing an integrated circuit device, comprising testing connection states between the plurality of connection terminals and the plurality of conductive wires through test pads.