JP2682004B2 - Digital integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital integrated circuit for processing digital signals and a digital integrated circuit for facilitating testing of a printed circuit board on which the digital integrated circuit is mounted.

2. Description of the Related Art In recent years, digital integrated circuits are increasing in surface mounting type such as flat packages in order to increase mounting density.

An example of the above-described conventional digital integrated circuit will be described below with reference to the drawings.

FIG. 5 is a block diagram of a conventional digital integrated circuit. In FIG. 5, 1a to 1d are input terminals and 2a
2d is an output terminal, 4 is an oscillator, 5 is a digital signal processing unit for processing a digital signal, and 9 is an oscillator such as a crystal oscillator, which is connected to the oscillator 4.

The operation of the digital integrated circuit configured as described above will be described below.

The clock 10 generated by the oscillator 9 and the oscillator 4 and the input signal supplied from the input terminals 1a to 1d are processed by the digital signal processing unit 5, and necessary signals are output at the output terminals 2a to 2d.

However, in the above configuration, the output terminals 2a to 2d
Furthermore, the output signal is not constant, and it is difficult to find a defect such as a soldering defect during mounting.

In view of the above problems, the present invention provides a digital integrated circuit that facilitates the discovery of defects during mounting.

Means for Solving the Problems In order to solve the above problems, a digital integrated circuit according to the present invention includes a digital signal processing unit that inputs and processes a signal input from an input terminal and a clock signal, and one or a plurality of digital signal processing units. A test terminal, a selector circuit for switching and outputting an input signal input from the input terminal, a signal output from the digital signal processing unit, and the clock signal according to a signal input from the test terminal; and the selector. And an output terminal for outputting a signal from the circuit.

With the above-described structure, the present invention switches the output of the selector circuit according to the signal applied to the test terminal, outputs the clock signal or the inverted signal of the clock or the input signal input from the input terminal, and outputs the digital integrated circuit. It is easy to find defects during mounting.

Embodiment A digital integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a digital integrated circuit according to the first embodiment of the present invention.

In FIG. 1, 1a to 1d are input terminals, 2a to 2d are output terminals, 3a and 3b are test terminals, 6a to 6d and 7a to 7d are selector circuits, and input A, Input B is selected and a signal is output from Y. A clock signal 10 is obtained by the oscillator 4 and the oscillator 9, and an inverted signal of the clock signal 10 is obtained by the inverting circuit 8. A digital signal processing unit 5 processes the input signal input from the input terminals 1a to 1d and the clock signal 10. Here, the clock signal 10 or the clock inversion signal is connected to the input A of the selector circuits 6a to 6d, and the input signal supplied from the input terminals 1a to 1d is connected to the input B. The outputs Y of the selector circuits 6a to 6d are connected to the inputs A of the selector circuits 7a to 7d, and the outputs of the digital signal processing section 5 are connected to the inputs B, respectively. The outputs Y of the selector circuits 7a-7d are connected to the output terminals 2a-2d.

The operation of the digital integrated circuit configured as described above will be described below with reference to FIGS. 1 and 2.

First, FIG. 2 shows an example of a circuit for realizing the selector circuits 6a to 6d and 7a to 7d, which is composed of OR gates 11 and 12, an AND gate 13 and an inverting circuit 14.

In FIG. 2, if the input S is "L", the inverting circuit 14
The output of the OR gate 11 is "H", and the output of the OR gate 11 is always "H" regardless of the input B. On the other hand, the output of the OR gate 12 is the input A
And the output Y of the AND gate 13 becomes the same as the signal given at the input A. Conversely, if the input S is "H", the output of the OR gate 12 is always "H".
Therefore, the output Y of the AND gate 11 becomes the same as the signal given by the input B. As described above, the selector circuit of FIG. 2 obtains the signal of the input A when the input S is "L" and the signal of the input B when the input S is "H".

In FIG. 1, at the time of actual operation, the test terminal 3b is at "L" level, and the selector circuits 7a to 7d have the input A
Signal is selected, and the signal obtained from the digital signal processing unit 5 is output to the output terminals 2a to 2d. At the time of the mounting test, first, the test terminal 3b is set to "H" and the test terminal 3a is set to "H". At this time, the clock signal 1 is output to the output terminals 2a and 2c.
0, the inverted signal of the clock signal 10 is output to the output terminals 2b and 2d, respectively. By observing the waveform of this output signal on the mounted printed circuit board or the like, the mounting test of the output terminal can be easily performed.

Next, if only test terminal 3a is set to "L", output terminals 2a to 2d
Input signals supplied from the input terminals 1a to 1d are directly output to. At this time, if the waveforms of the input signal and the output signal are observed and compared, the mounting test of the input terminal can be easily performed.

As described above, according to this embodiment, the two test terminals 3
a, 3b, selector circuits 6a to 6d, 7a to 7d controlled by signals applied to the test terminals, a clock signal 10 and an inverted signal of the clock signal obtained from the oscillator 4, and a plurality of input terminals 1a to 1d. And a plurality of output terminals 2a to 2d,
Input to the selector circuits 6a to 6d, 7a to 7d, the clock signal 10 or an inverted signal of the clock signal or the input terminal 1a to
Connect the input signal input from 1d, and select the selector circuit above.
By outputting the output signals of 6a to 6d and 7a to 7d from the output terminals 2a to 2d, the clock signal can be
An inverted signal of 10 or a clock or an input signal input from the input terminals 1a to 1d is output from the output terminals 2a to 2d, and the mounting test of the digital integrated circuit can be easily performed.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram of a digital integrated circuit showing a second embodiment of the present invention. In Figure 3 1a
1 to 1c are input terminals, 15 is a clock input terminal, and the others are similar to those of the configuration of FIG. The difference from the configuration of FIG. 1 is that the number of input terminals 1a to 1c is smaller than the number of output terminals 2a to 2d, and the input of the selector circuit 7d is
Inverted signal of clock signal 10 and digital signal processing unit 5
The clock signal 10 is supplied from the clock input terminal 15.

Since the output terminals 2a, 2b, 2c of the digital integrated circuit configured as described above operate in the same manner as in FIG. 1, the mounting test of the input terminals 1a to 1c and the output terminals 2a to 2c can be easily performed during the test. It For the output terminal 2d, set the test terminal 3b to "H".
By doing so, an inverted signal of the clock signal 10 is output, so that the mounting test of the output terminal 2d becomes easy. As described above, the mounting test can be easily performed even when the number of input terminals is smaller than the number of output terminals.

FIG. 4 is a block diagram showing an embodiment in which the number of input terminals is larger than the number of output terminals. In Figure 4, 3c
Is a third test terminal, and 16a is a selector circuit controlled by a signal applied to the third test terminal 3c. Other configurations are almost the same as those in FIG. 3, and therefore detailed description will be omitted. 4th
In the figure, if the test terminal 3c is set to "H", the selector circuit
The output of 16a becomes the signal given from the input terminal 1c. When both the test terminals 3a and 3b are set to "H", the output terminals 2a to 2b
The clock signal 10 or an inverted signal of the clock signal 10 is output to the. Next, when only the test terminal 3a is set to "L", the signals applied to the input terminals 1a to 1c are output as they are to the output terminals 2a to 2c. Therefore, input terminals 1a-1c and output terminals 2a-2c
The implementation test of can be done easily.

Further, when the test terminal 3c is set to “L”, the signal given from the input terminal 1d is output to the output terminal 2c,
Implementation test of 1d becomes easy. As described above, the mounting test can be easily performed even when the number of input terminals is larger than the number of output terminals.

As described above, according to the present invention, one or a plurality of test terminals and a plurality of selectors for selecting and outputting one signal from a plurality of input signals by the signals applied to the test terminals. A circuit, a clock signal obtained from an oscillator for generating a clock or a clock input terminal, a plurality of input terminals and a plurality of output terminals, and the clock signal or an inverted signal of the clock signal or the above at the input of the selector circuit. By connecting the input signal input from the input terminal and outputting the output signal of the selector circuit from the output terminal, the mounting test of the digital integrated circuit can be easily performed, and the defect during mounting can be easily found.

[Brief description of the drawings]

1 is a block diagram of a digital integrated circuit in a first embodiment of the present invention, FIG. 2 is a circuit diagram of a selector circuit, and FIG. 3 is a block diagram of a digital integrated circuit in a second embodiment of the present invention. FIG. 4 is a block diagram of a digital integrated circuit according to the third embodiment of the present invention, and FIG. 5 is a block diagram of a conventional digital integrated circuit. 1a to 1d …… Input terminals, 2a to 2d …… Output terminals, 3a to 3c ……
Test terminal, 4 ... Oscillator, 5 ... Digital signal processor, 6a-6d, 7a-7d, 16a ... Selector circuit, 10 ... Clock signal.

Claims (1)

(57) [Claims] 1. A digital signal processing unit for inputting and processing a signal and a clock signal input from an input terminal, one or a plurality of test terminals, an input signal input from the input terminal and the digital signal processing. A selector circuit for switching and outputting the signal output from the unit and the clock signal according to the signal input from the test terminal, and an output terminal for outputting the signal from the selector circuit. Digital integrated circuit.