JPH04282913A - Semiconductor integrated circuit with bypass circuit built therein - Google Patents

Abstract

PURPOSE:To facilitate a complicated test in terms of a board level by integrating a bypass circuit even to a high speed operation circuit because a delay in a signal by a selector is not necessary to be taken into account. CONSTITUTION:Upon the receipt of a test mode switching signal from an input section 10, mode changeover switches 2, 3 are conductive, the normal mode is switched into the test mode, and an output terminal 5 of an output buffer 7 and an output terminal 4 of an input buffer 6 are connected via a bypass circuit 1. Moreover, the output buffer 7 receives an output high impedance switching signal from an input section 11 in this case and the impedance reaches a high impedance. Since the output terminal 5 of the output buffer 7 and the output terminal 4 of the input buffer 6 are connected via the changeover switches 2, 3 in this way, the signal is bypassed at a high speed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit incorporating a bypass circuit.

0002

2. Description of the Related Art In a conventional semiconductor integrated circuit with a built-in bypass circuit, as shown in FIG. 2, the output terminal 4 of an input buffer 6 is branched, one end being connected to a bypass circuit 1 and the other being a normal operation circuit. Bypass circuit 1 and internal circuit 8 are further connected to output buffer 7 via selector 9 .

By switching the selector 9, the bypass circuit 1 and the internal circuit 8 are selected.

0004

[Problems to be Solved by the Invention] In this conventional semiconductor integrated circuit with a built-in bypass circuit, a selector is provided between the bypass circuit and internal circuit, and the output buffer, so the selector causes a signal delay, resulting in a high-speed There was a problem in that a bypass circuit could not be incorporated into the operating circuit.

An object of the present invention is to provide a semiconductor integrated circuit with a built-in bypass circuit that can incorporate a bypass circuit even in a high-speed operation circuit.

[0006]

[Means for Solving the Problems] The present invention provides a semiconductor integrated circuit having an input buffer and an output buffer.
A first mode changeover switch is provided at the output end of the input buffer, a second mode changeover switch is provided at the output end of the output buffer, and a bypass circuit is provided between the first mode changeover switch and the second mode changeover switch. It is characterized by having the following.

Further, according to the present invention, it is preferable that the output buffer is a three-state output buffer that becomes high impedance when the bypass circuit is selected.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The semiconductor integrated circuit with a built-in bypass circuit shown in FIG. ing.

Furthermore, this embodiment includes a plurality of input buffers 6, output buffers 7, mode changeover switches 2 and 3, and a plurality of bypass circuits 1.

The output terminal 4 of the input buffer 6 is branched, and one side is connected to the internal circuit 8 and the other side is connected to the bypass circuit 1 via the mode changeover switch 2. Internal circuit 8 is connected to output buffer 7 , and output end 5 of output buffer 7 is connected to bypass circuit 1 via mode changeover switch 3 .

A test mode switching signal is also applied to the mode switching switches 2 and 3 from the input section 10.
The output buffer 7 is supplied with an output high impedance switching signal from the input section 11 .

Next, the operation of this embodiment will be explained.

When the mode changeover switches 2 and 3 receive a test mode changeover signal from the input section 10, they become conductive and switch from the normal mode to the test mode, and the output end 5 of the output buffer 7 and the output end 4 of the input buffer 6 are connected via a bypass circuit 1.

[0015] Also, in this case, the output buffer 7
It receives an output high impedance switching signal from 1 and becomes high impedance.

In this way, in this embodiment, the output buffer 7
Since the output terminal 5 of the input buffer 6 and the output terminal 4 of the input buffer 6 are connected by the changeover switches 2 and 3, signals can be bypassed at high speed.

[0017]

[Effects of the Invention] As explained above, in the present invention, by providing a bypass circuit between the output end of the input buffer and the output end of the output buffer, there is no need to consider the signal delay caused by the selector in the conventional circuit. Since bypass circuits can be incorporated even in high-speed circuits, complex board-level tests can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of a conventional semiconductor integrated circuit with a built-in bypass circuit.

[Explanation of symbols]

1 Bypass circuit 2, 3 Mode selection switch 4 Output end of input buffer 5 Output end of output buffer 6 Input buffer 7 Output buffer 8 Internal circuit 9 Selector 10, 11 Input section

Claims (2)

[Claims] Claim 1: A semiconductor integrated circuit having an input buffer and an output buffer, wherein a first
A mode changeover switch is provided, a second mode changeover switch is provided at the output end of the output buffer, and a bypass circuit is provided between the first mode changeover switch and the second mode changeover switch. Semiconductor integrated circuit with built-in bypass circuit. 2. A semiconductor integrated circuit with a built-in bypass circuit according to claim 1, wherein the output buffer is a three-state output buffer that becomes high impedance when the bypass circuit is selected.