JPH0618627A - Testing circuit - Google Patents

Abstract

PURPOSE:To decrease the wiring region in an LSI system and to reduce the size of a chip by decreasing the number of wirings for test contained in a testing circuit for the system, wherein a plurality of units having the independent functions are coupled to one LSI. CONSTITUTION:Tristate buffers 102 for controlling the driving of test-output signal lines are arranged in the insides of a plurality of functional units constituting an LSI system. The tristate buffer 102 can be constituted in response to the output signal of a control unit for controlling the testing state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit, and in particular, in a system in which a plurality of units having independent functions are combined into one LSI, the system test is performed by a single unit or by combining several units. The present invention relates to a test circuit for performing a test.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a unit including a conventional test circuit. In FIG. 3, the unit core 301
Input terminals of the test signal input terminal 307 and the test signal input terminal 30 via the input signal multiplexer 303.
8 is connected. The output terminal of the unit core 301 is connected to each of the normal signal output terminal 305 and the test signal output terminal 306 via a buffer. Here, the normal signal output terminal 305 and the test signal output terminal 30
Since 6 is the same in logic, the test signal output terminal 30
Although 6 does not seem to be necessary logically, fan-out becomes a problem in an actual LSI, so it is necessary to divide it into two for normal signals and one for test signals, and to provide a buffer for each. However, in FIG. 3, this buffer is omitted for simplicity. Similarly, the fan-out buffer is omitted thereafter. The test mode control signal 304 is connected to the control signal input terminal of the input signal multiplexer 303.

When testing such a unit, the following operation is performed. When the test mode control signal 304 is low level, the input signal multiplexer 303 selects the normal signal input terminal 307 side, and when the test mode control signal is high level, the test signal input terminal 308 side is selected and the unit core 301 is selected. Is entered.

Since the output side is not controlled by the test mode control signal like the input side, the normal signal output terminal 305 and the test signal output terminal 306 have unit cores regardless of the high level / low level of the test mode control signal. The output signal of 301 is output.

FIG. 4 shows an example of a system composed of two functional units in which a test can be performed by itself. In FIG. 4, a unit 402 and a unit 403 are functional units each having a test circuit as shown in FIG. 3, and have two normal signal input terminals, two normal signal output terminals, and a test paired with them. It has two signal input terminals and two test signal output terminals, and one test mode control signal input terminal. The normal signal output terminal and the normal signal input terminal of the unit 402 and the unit 403 are connected to each other. External test signal input terminals 406 and 407
Are respectively connected to the two test signal input terminals of the two units. Unit 402 and unit 403-2
Each of the two test signal output terminals is a multiplexer 4
It is connected to the external test signal output terminal via 10, 411.

The test mode control signal 408 is connected to the control signal input terminal of the unit 402 and the control signal input terminal of the external output signal multiplexers 410 and 411 on the unit 402 side, and the test mode control signal 109 is
The control signal input terminal of the unit 403 is connected to the control signal input terminal of the unit 403 side of the external output signal multiplexers 410 and 411. Here, the control unit 401
Must have a structure that does not set two or more test mode control signals to a high level.

When testing the unit 402, the control unit 401 sets the test mode control signal 408 to high level. At this time, the test mode control signal 409 is at low level. External output signal multiplexer 410
Since the unit 402 side of 411 and 411 is selected, the unit 403 side becomes non-selected, and two output signals of the unit 402 are output from the external test signal output terminals 404,
It is output to 405.

Further, the test signal input terminal 308 in the input signal multiplexer 303 in FIG.
Since the side is selected, the test input signals from the external test signal input terminals 406 and 407 are applied to the two input terminals of the unit core, respectively. At this time, the output signal of the unit 403 is applied to the normal signal input terminal of the unit 402, and the external output signal multiplexer 41
The test output signals are input to the 0, 411 from the test signal output terminals of the units 402, 403. Therefore, the test of the unit 402 is not affected. Similarly, if the test mode control signal 409 is high level and 408 is low level, the unit 403 can be independently tested.

[0009]

In the case of the configuration shown in FIG. 4, two test input signal wirings and four test output signal wirings are required as test signal wirings from each functional unit to the external terminals. Also, four test mode control signal wires from the control unit to the external terminals and each functional unit were required.

Generally, the number of test wirings required to switch the test output signals from the n units to the external output is given as follows.

Since there are n test output signal wires for each external output terminal in the chip, if there are m external output terminals, the test output signal wires in the chip are mx.
n pieces were needed. Also, the test mode control wiring is 1 for each external terminal side and unit side for one unit.
Since the number of wirings is required one by one, 2 × n wirings are required for n units.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a test circuit in which the number of wirings is reduced.

[0013]

A test circuit according to the present invention has a structure in which a tri-state buffer for controlling driving of a test signal line is provided inside a plurality of functional units forming an LSI system and control for controlling a test state is performed. The tri-state buffer can be controlled in response to an output signal of the unit.

[0014]

1 is a block diagram showing the structure of a unit including a test circuit according to an embodiment of the present invention. In this embodiment, in FIG. 1, the input terminal of the unit core 101 is connected to the normal signal input terminal 1 via the input signal multiplexer 103.
07 and the test signal input terminal 108. One of the output terminals of the unit core 1 is directly connected to the normal signal output terminal 105, and the other is connected to the test signal output terminal 106 via the tri-state buffer 102.
It is connected to the. The test mode control signal 104 is the input signal multiplexer 103 and the tri-state buffer 1
02 is connected to the control signal input terminal.

When testing such a unit,
It operates as follows. When the test mode control signal 104 is at low level, the input signal multiplexer 103 selects the normal signal input terminal 107 side. At this time, the tri-state buffer 102 does not drive the test signal output terminal 106.

On the contrary, when the test mode control signal 104 is at the high level, the input signal multiplexer 103 selects the test signal input terminal 108 side. Further, the tri-state buffer 102 drives the test signal output terminal 106 to put the output signal of the unit core 101 on the test signal line.

That is, when the test mode control signal is at the high level, this unit is in the test mode and the test input signal is applied to the unit core input terminal and the unit core output signal is applied to the test output terminal.

Next, using the test circuit of this embodiment, 2
FIG. 2 shows an example of a system including a single functional unit 202 and 203 and performing a test by itself. In FIG. 2, in this example, the unit 202 and the unit 203 are functional units each having a test circuit as shown in FIG. 1 inside, and have two normal signal input terminals, two normal signal output terminals, and those terminals. It has two test signal input terminals and two test signal output terminals and a test mode control signal input terminal. The normal signal output terminals and the normal signal input terminals of the units 202 and 203 are connected to each other.

External test signal input terminals 206 and 20
7 is connected to the two test input terminals of the two units, respectively, and is connected to the external test signal output terminals 204 and 2
05 is connected to the two test signal output terminals of the two units, respectively. The test mode control signal 208 is connected to the control signal input terminal of the unit 202, and the test mode control signal 209 is connected to the control signal input terminal of the unit 203. Here, the control unit 201 needs to have a structure that does not set two or more test mode control signals to a high level.

Now to test the unit 202,
The control unit 201 sets the test mode control signal 208 to the high level. At this time, since the test signal input terminal 108 side is selected by the input signal multiplexer 103 in FIG. 1 on the input side inside the unit 202, the external test signal input terminal 2 is connected to the two input terminals of the unit core.
Input signals from 06 and 207 are applied respectively.

On the output side, the tri-state buffer 102 of FIG. 1 drives the test signal output terminal 106, so that two output signals of the unit core are output to the external test signal output terminals 204 and 205. At this time, the output signal of the unit 203 is applied to the normal signal input terminal of the unit 202, and the external test signal output terminal 20
4, 205 are connected to the test output signals from the test signal output terminals of the units 202 and 203, the unit 203 of the input signal multiplexer in the unit 202.
Since the side is unselected and the test signal output terminal is not driven by the tri-state buffer in the unit 203, it does not affect the test of the unit 202. Therefore, the test of the unit 202 can be performed independently. it can.

Similarly, test mode control signal 209
When is set to a high level, the unit 203 can be independently tested.

[0023]

The following Table 1 shows the results of comparison of the number of test signal wirings and control wirings with the conventional FIG. 4 of FIG. 2 using this embodiment.

[0024]

[Table 1]

Next, in the case where it is composed of n units, has one external test input terminal and m external test output terminals, the test signal wiring of the prior art and this embodiment,
The results of comparing the number of control wirings are shown in Table 2 below.

[0026]

[Table 2]

As is clear from Tables 1 and 2, the present invention can reduce the number of test control wirings and signal wirings, so that the chip size can be reduced. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a unit including a test circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a system for performing test output and input of two units using the test circuit of FIG.

FIG. 3 is a block diagram showing a configuration example of a unit including a test circuit according to a conventional technique.

FIG. 4 is a block diagram showing a conventional example of a system for performing test output and test input of two units.

[Explanation of symbols]

101, 301 Unit core 102 Tri-state buffer 103 Input signal multiplexer 104, 208, 209, 304, 408, 409
Test mode control signal 105,305 Normal signal output terminal 106,306 Test signal output terminal 107,307 Normal signal input terminal 108,308 Test signal input terminal 201,401 Control unit 202,203,402,403 Functional unit 204,205, 404, 405 External test signal output terminal 206, 207, 406, 407 External test signal input terminal 303 Input signal multiplexer 304 Test mode control signal 410, 411 External output signal multiplexer

Claims (2)

[Claims] 1. A tri-state buffer is provided in front of a test signal output terminal in each of a plurality of functional units constituting an LSI system, in response to an output signal of a control unit for controlling a test state, A test circuit characterized by controlling a state buffer. 2. From the control unit to each functional unit,
The test circuit according to claim 1, wherein only one test mode control signal line is connected.