JP3367451B2 - Macro core test apparatus and macro core test method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic test technology for a dedicated LSI (ASIC) for a specific customer, and particularly to reduce the number of external signal pins required for a macro core test and to provide a test input required for the macro core test. The present invention relates to a macro core test device and a macro core test method capable of providing a large number of output terminals.

[0002]

2. Description of the Related Art In recent years, dedicated LSI (AS) for specific customers
IC) is a system LSI called system-on-silicon, which is equipped with a large number of multifunctional blocks (macro cores) such as a CPU core, a memory macro core, and an analog macro core.
The ratio of is increasing. Many of these functional blocks (macro cores) are provided to customers as hard macro libraries by each LSI manufacturer.

FIG. 3 shows a dedicated LSI (ASI) for a specific customer.
Macro cores MACRO1, ..., MACRO in C)
4 shows an example of a conventional macro core test apparatus for testing each of the four. That is, in the conventional macro core test apparatus, the macro cores MACRO1, ..., MACRO
4 each include a test mode setting terminal TEST and test input / output terminals TEST1 and TEST as shown in FIG.
2 is provided. Macro core MACRO1, ..., MAC
Each of the RO4 has a macro test mode in addition to the normal operation, and when performing a macro test, each of the RO4 has a test input / output terminal TEST1 given to the terminal A1 and a test input / output terminal TEST2 given to the terminal A2. , MACR1, ..., MACR selected by the decoder P2
Input / output for test that can directly input / output a signal from an external terminal (not shown) after setting one of the test mode setting terminals TEST of O4 to the logic state "1" to switch from the normal operation mode to the macro test mode Terminal TEST1, T
Macro cores MACRO1, ..., MA using EST2
Perform a functional test on each CRO4 unit. In the case of this conventional method, the macro cores MACRO1, ..., MAC
Since a test mode setting terminal TEST for setting each macro test mode of RO4 is required, the number of test mode setting terminals TEST + maximum number of test input / output terminals (per macro core) ≤ used for test circuit There is a limit to the number of external signal pins possible. As such a conventional technique, for example, Japanese Patent Laid-Open No. 10-9036 is known.
There is one described in Japanese Patent No. 2 publication. That is, in a semiconductor integrated device having a plurality of circuit blocks inside, first signal selecting means for switching a signal supplied to a circuit block to be tested from a signal at the time of normal operation during a test to a signal supplied to an external terminal, It has a pattern compression means for pattern-compressing the output signal of the circuit block to be tested and outputting it from the external terminal after the test is completed, and a selector for selecting the output signal of the circuit block and outputting it from the external terminal at the time of the test becomes unnecessary. It is disclosed that the number of external terminals that output the output signals of the circuit block at the time of testing can be reduced and a macro having a large number of input / output signals can be tested.

[0004]

Macro cores MACRO1, ..., MAC having high functions in recent years such as CPU cores.
RO4 is often used, but these macro cores M
Because ACRO1, ..., MACRO4 have high function,
The number of input / output terminals for testing tends to increase. Also,
Other macro cores used in one product MACRO1, ...,
Since the number of mounted MACRO4 is also increasing, the number of macro test mode setting terminals required for that is also increasing. However, the conventional macro core test equipment has a macro core MAC that has high functionality in a product with a small number of signal pins in such a situation.
When a large number of RO1, ..., MACRO4 are mounted, there is a problem that the number of external signal pins that can be used in the test circuit is insufficient.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the number of external signal pins required for testing a macro core and to provide test input / output terminals required for testing the macro core. The object is to provide a macro core test apparatus and a macro core test method capable of providing a large number of devices.

[0006]

According to a first aspect of the present invention, there is provided a type 1 macrocore having a plurality of test input / output terminals and a test output terminal commonly connected to the test input terminals, and A plurality of second type macro cores having a smaller number of test input / output terminals than the first type macro cores and test output terminals commonly connected to the test input terminals, and a terminal for setting the test mode of the first type macro cores. And a test mode setting terminal which also serves as an input / output mode control terminal of an external bidirectional terminal used for setting the test mode of the second type macro core, the first type macro core not selected as a test mode, and / or Alternatively, the test output terminal of the second-type macro core is set in accordance with the signal level applied to the input / output mode control terminal. Resides in the macro core test apparatus characterized by having a two-way circuit is set to high impedance. The gist of claim 2 of the present invention is
The first-type macro core and / or the second-type macro core switches from the normal operation mode to the test mode when set to the first logic value, and the test input terminal and the test output terminal are enabled, and the test is performed. 2. The macro core test apparatus according to claim 1 , wherein a circuit configuration is such that a signal is directly applied to the test input terminal from the test mode setting terminal in the mode. Further, the gist of claim 3 of the present invention is to set one of a plurality of the second type macro cores to a first logical value according to a combination of signal levels input from the external bidirectional terminals. The macro core test apparatus according to claim 1 or 2 , further comprising a selection circuit for performing the operation. Further, the gist of claim 4 of the present invention is to provide a first-type macro core having a plurality of test input / output terminals and a test output terminal commonly connected to the test input terminal, and a number less than the first-type macro core. A plurality of second type macro cores each having a test input / output terminal and a test output terminal commonly connected to the test input terminal, and a second type macro core for setting a test mode of the first type macro core. For the LSI having a test mode setting terminal which also functions as an input / output mode control terminal of an external bidirectional terminal used for the test mode setting of the first type macro core and / or the non-selected test mode. The test output terminal of the second type macro core is set in accordance with a signal level applied to the input / output mode control terminal. Lee
Characterized by having a step of setting impedance
Resides in that macro core test method. Further, the gist of claim 5 of the present invention is that the first-type macro core and / or the second-type macro core switches from a normal operation mode to a test mode when set to a first logical value, and the test input 5. The macro core test method according to claim 4 , wherein the terminal and the test output terminal are enabled, and a signal is directly applied to the test input terminal from the test mode setting terminal in the test mode. Further, according to a sixth aspect of the present invention, any one of a plurality of the second type macro cores is set to a first logical value according to a combination of signal levels input from the external bidirectional terminals. The macro core test method according to claim 4 or 5 , further comprising:

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION The feature of each embodiment shown below is that a circuit for setting a test mode of a macro core in a system LSI having a large number of macro cores is dedicated to a test mode of a macro core having the largest number of test input / output terminals. There is a setting terminal. This makes it possible to use the external bidirectional terminal, which is an external terminal, as a test mode setting terminal exclusively for the macro core. As a result, the maximum number of test input / output terminals of the mounted macro core can be expanded with a limited number of external terminals. There is an effect that it becomes possible to do. Such a macro core test apparatus has a small number of signal pins that can be used as test terminals due to the use of a small number of packages, and a system LS having a large number of mounted macro cores.
Especially effective for I products. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a functional block diagram for explaining a macro core test apparatus according to a first embodiment of the present invention. The macro cores MACRO0, ...
The case where the macro test of MACRO4 is carried out is shown.
Here, the macro core is a circuit block having a certain function that has been designed in advance. In the macro core test apparatus shown in FIG. 1, the macro core MACRO0 (first-class macro core), which is equipped with one and has a large number of test input / output terminals.
And the number of individual test I / O terminals is small, but the number mounted is 4
, MACRO4 (second type macro core), bidirectional circuits (three-state buffer group) 14, 16, a selection circuit 12, and a macro core M.
A test mode setting terminal M1 dedicated to ACRO0 is provided.

The test mode setting terminal M1 is a terminal for setting the test mode of the macro core MACRO0, and is an external bidirectional terminal TEST used for setting the test mode of the macro cores MACRO1, ..., MACRO4.
1, TEST2 input / output mode control terminal T1
4, doubles as T16.

As a result, the external bidirectional terminals TEST1 and TEST2, which are external terminals, can be used also as the test mode setting terminal M1 dedicated to the macro core MACRO0. As a result, the test of the mounted macro core can be performed with a limited number of external terminals. It is possible to increase the upper limit of the number of input / output terminals. Such a macro core test device has a small number of signal pins that can be used as test terminals due to the use of a small number of packages, and is particularly effective for system LSI products having a large number of mounted macro cores.

The configuration of the embodiment of the invention will be described in more detail. In the macro core test apparatus of this embodiment, each macro core MACRO0, ..., MACRO4
Is a test mode setting terminal TEST and a test input terminal T
BI1, ..., TBI [N] (N: number of terminals for test mode setting), and test output terminals TBO1, ..., TBO
It has [M] (M: number of macros installed). The macro cores MACRO0, ..., MACRO4 have other terminals for normal operation, but they are not shown in this embodiment.

The test input terminals TBI1,
..., TBI [N], test output terminals TBO1, ..., TB
O [M] are commonly connected. That is, the macro core MACRO0 not selected as the test mode,
…, MACRO4 test output terminals TBO1,…, TB
All outputs of O [M] are high impedance (Hi-
Z), driving the output wiring is in the test mode of the macro cores MACRO0, ..., MAC
Only RO4 can be connected in common. Further, the test output terminals TBO [M-1] and the test output terminals TBO [M] of the macro cores MACRO1, ..., MACRO4 are external bidirectional terminals TEST1 and TEST2.
It is configured to output from.

When the test mode setting terminal TEST is set to the logic state "1", the macro cores MACRO0,
,, MACRO4 is switched from the normal operation mode to the test mode, the normal operation terminals (not shown) are disabled, and the test input terminals TBI1, ..., TBI [N]
And the test output terminals TBO1, ..., TBO [M] are enabled. Test input terminals TBI1, ..., TBI [N]
Has a circuit configuration in which a signal is directly applied from the test mode setting terminal M1 in the test mode.

On the other hand, the test output terminals TBO1, ..., TB
The signal output from O [M] has an output circuit configuration that can be directly taken out from an external output terminal (not shown) in the test mode.

With such an output circuit configuration, in the test mode, it is possible to perform a single function test of the macro cores MACRO0, ..., MACRO4 which does not depend on the peripheral logic circuit which is different for each product.

In the macro core test apparatus of this embodiment,
The test mode setting terminal M1 dedicated to the macro core MACRO0 having the largest number of test input / output terminals and the macro cores MACRO1, ..., MAC having a smaller number of test input / output terminals than that
RO4 test mode setting and macro core MACRO
It has an external bidirectional terminal TEST1 and an external bidirectional terminal TEST2 which also serve as the 0-only test mode setting terminal M1.

The input terminal sides of the external bidirectional terminal TEST1 and the external bidirectional terminal TEST2 are connected to the test mode setting terminals TEST of the macro cores MACRO0, ..., MACRO4 through the selection circuit 12 (denoted as 2 to 4 Decoder in the drawing). ing.

The external bidirectional terminal TEST1 and the external bidirectional terminal TEST2 are used as input states. First logical state: external bidirectional terminal TEST1 logical value = external bidirectional terminal TEST2 logical value = 0, second logical state: external Logical value of bidirectional terminal TEST1 = logical value of external bidirectional terminal TEST2 = 1, third logical state: logical value of external bidirectional terminal TEST1 =
1, logical value of external bidirectional terminal TEST2 = 0, fourth logical state: logical value of external bidirectional terminal TEST1 =
There are four logic states of 0 and the logical value of the external bidirectional terminal TEST2 = 1, and the macro core MACRO1,
…, One of the TEST terminals of MACRO4 is in the logical state ”
It can be set to 1 ". This enables control of the test mode setting of the macro cores MACRO1, ..., MACRO4.

The output terminals of the external bidirectional terminal TEST1 and the external bidirectional terminal TEST2 are connected to the macro core MACR.
O1 test output terminal TBO1 and test output terminal T
Each of them is connected to BO2. Macro core MACR
The test mode setting terminal M1 dedicated to O0 is the macro core M
A bidirectional circuit (three-state buffer group) that is directly connected to the test mode setting terminal TEST of ACRO0 and switches between the signal output from the test output terminal TBO1 of the macro core MACRO0 and the logic signal input from the external bidirectional terminal TEST1. ) 14 input / output control terminals T14 (high impedance in logic state "0", activated in logic state "1"), and signals output from test output terminal TBO2 of macro core MACRO0 and external bidirectional terminal TEST2 Input / output control terminal T16 (logical state) of the bidirectional circuit (three-state buffer group) 16 for switching the logical signal
It is connected to high impedance at 0 "and activated at logic state" 1 ").

Here, the macro cores MACRO1, ..., M
The number of external signal pins that can be used for testing ACRO4 is 6
4, if the number of test input / output terminals of the macro core MACRO1 is 63 and the number of test input / output pin terminals of the macro cores MACRO1, ..., MACRO4 is 61 or less, the terminals are shared in this embodiment. The number of test input / output terminals of the macro core MACRO0 (63) + the number of test dedicated terminals of the macro core MACRO0 (1) ≦ the number of usable external signal pins (64), and the macro core MA
CRO0 can be tested, but if the terminals are not shared, the number of test input / output terminals of the macro core MACRO0 (63) + the number of dedicated test terminals of the macro core MACRO0 (1) + the external bidirectional terminal TEST1 and the external Bidirectional terminal TEST2 (2) ≧ the number of usable external signal pins (64), and it becomes impossible to perform a unit function test of macro core MACRO0.

The operation of this embodiment will be described below. Figure 1
, MACRO1, ..., MACR
When each macro test of O4 is performed, the buffer 22 inputs the logic state "0" to the macro core MACRO0 by inputting the logic signal of the logic state "0" to the test mode setting terminal M1 dedicated to the macro core MACRO0.
To the test mode setting terminal TEST of the macro core M
ACRO0 in non-test mode and macro core MACRO
1, ..., MACRO 4 are set to the test mode, and in response to this, the bidirectional circuit (three-state buffer group) 14 that has received this logic state “0” at the input / output control terminal T14 has this logic state “0”. , The logic signal from the external bidirectional terminal TEST1 is valid and the logic signal from the test output terminal TBO1 of the macro core MACRO0 is invalid, that is, the logic signal from the external bidirectional terminal TEST1 is transmitted to the input terminal A1 of the selection circuit 12. Similarly, this logic state "0" is set to the input / output control terminal T1.
Bidirectional circuit received in 6 (three-state buffer group) 1
6 is an external bidirectional terminal TES according to this logic state "0".
The logic signal from T2 is valid and the macro core MACRO0
Of the logic signal from the test output terminal TBO1 of the test circuit, that is, the logic signal from the external bidirectional terminal TEST2 is transmitted to the input terminal A2 of the selection circuit 12, and the external bidirectional terminal TES is transmitted.
Based on the input signals from T1 and the external bidirectional terminal TEST2, the selection circuit 12 causes the macro cores MACRO1, ..., MA to
The macro mode MACRO1, ..., MAC is controlled by controlling each test mode setting terminal TEST of CRO4.
A functional test for each macro is sequentially performed on each RO4.

On the other hand, only when the macro test of the macro core MACRO0 is performed, the buffer 22 receives this logic state by inputting the logic signal of the logic state "1" to the test mode setting terminal M1 dedicated to the macro core MACRO0.
1 "is transmitted to the test mode setting terminal TEST of the macro core MACRO0 to set the macro core MACRO0 to the test mode and each of the macro cores MACRO1, ..., MACRO4 to the non-test mode, and accordingly, the logical state" 1 "is input / output. The bidirectional circuit (three-state buffer group) 14 received at the control terminal T14 invalidates the logic signal from the external bidirectional terminal TEST1 and validates the logic signal from the test output terminal TBO1 of the macro core MACRO0 according to the logic state "1". That is, the bidirectional circuit (three-state buffer group) 16 that transmits the logical state of the test output terminal TBO1 of the macro core MACRO0 to the external bidirectional terminal TEST1 and at the same time receives this logical state "1" at the input / output control terminal T16 In response to this logical state "1" The logic signal from the external bidirectional terminal TEST2 is invalid and the logic signal from the test output terminal TBO2 of the macro core MACRO0 is valid, that is, the logic state of the test output terminal TBO2 of the macro core MACRO0 is transmitted to the external bidirectional terminal TEST2. ,
From the test output terminal TBO1 and the test output terminal TBO2 of the macro core MACRO0 to the external bidirectional terminal TEST
1 and the circuit connected to the output terminal side of the external bidirectional terminal TEST2 becomes effective.

The external bidirectional terminal TEST1 and the external bidirectional terminal TEST2 have the macro core MACRO.
0, ..., Test mode setting terminal TEST of MACRO4
And the test mode setting terminal M1 dedicated to the macro core MACRO0.

As described above, according to the first embodiment, the following effects can be obtained. Macro core MACRO
0, ..., Test mode setting terminal TEST of MACRO4
And the test output terminal TBO1, of the macro core MACRO0
Since the TBO 2 is also used, there is an effect (first effect) of increasing the upper limit of the number of test input / output terminals of the mounted macro core with a limited number of external terminals.

Further, the macro cores MACRO0, ..., MA
After setting the test mode of CRO4, the macro core test apparatus of the present embodiment inputs / outputs a test signal to / from the test circuits (macro cores MACRO0, ..., MACRO4) from the external bidirectional terminals TEST1 and TEST2. ,…, MACRO4
The condition of the number of external signal pins that can be used for is the number of terminals for macro core test mode setting + (macro core 1
The maximum number of test input / output terminals (per connection) ≦ the number of external signal pins that can be used in the test circuit. As a result, the test mode setting terminal M1 dedicated to the macro core MACRO0 and the test output terminal TBO of the macro core MACRO0 having the largest number of test input / output terminals are provided.
By also using 1 and TBO2, there is an effect (second effect) that the upper limit of the number of test input / output terminals of the macro core that can be unit tested can be expanded with a limited number of external input / output terminals. This embodiment is particularly effective for a system LSI in which a small number of packages are used and a macro core having many test input / output terminals such as a CPU core and a large number of other macro cores are used.

(Second Embodiment) FIG. 2 is a functional block diagram for explaining a macro core test apparatus according to a second embodiment of the present invention. The macro core test apparatus of the second embodiment has the basic configuration as described above, but when the number M of mounted macros is large, the effect is further enhanced. The structure is shown in FIG. In FIG. 2, the number N of test mode setting terminals is the macro core MAC having the largest number of test input / output terminals.
It is necessary to satisfy 2 ^N ≧ M for the number M of macros mounted excluding RO0. In this case, N ≦ macro core MACRO0
As long as the conditions for the number of test output terminals are satisfied, N
The number of terminals of a book can be shared.

It should be noted that the present invention is not limited to the above-mentioned respective embodiments, and it is apparent that the respective embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, positions, shapes, etc. of the above-mentioned constituent members are not limited to those in the above-mentioned embodiment, and the number, positions, shapes, etc. suitable for carrying out the present invention can be adopted. Moreover, in each figure, the same components are denoted by the same reference numerals.

[0028]

Since the present invention is configured as described above, it has the following effects. Since the test mode setting terminal of the macro core is also used as the test output terminal of the macro core, the effect of expanding the upper limit of the number of test input / output terminals of the mounted macro core with a limited number of external terminals (first
Effect). In addition, after the test mode of the macro core is set, the external bidirectional terminal and the macrocore test apparatus of the present embodiment which inputs / outputs the test signal to / from the test circuit (macrocore) from the external bidirectional terminal are Pin number condition is the number of terminals for macro core test mode setting + (per macro core)
The maximum number of test input / output terminals ≦ the number of external signal pins that can be used in the test circuit. As a result, by combining the test mode setting terminal M1 dedicated to the macro core with the test output terminal of the macro core having the largest number of test input / output terminals, the test input / output of the macro core capable of unit test with a limited number of external input / output terminals. There is an effect (second effect) that the upper limit of the number of terminals can be widened.

[Brief description of drawings]

FIG. 1 is a functional block diagram for explaining a macro core test device according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram for explaining a macro core test device according to a second embodiment of the present invention.

FIG. 3 shows a conventional macro core test apparatus for testing each macro core in a dedicated LSI for a specific customer.

[Explanation of symbols]

12 ... Selection circuits 14, 16, ..., 1 [N-1], 1 [N] ... Bidirectional circuit (three-state buffer group) 22 ... Buffers A1, A2 ... Terminal M ... Macro mount number M1 ... Test mode setting terminal MACRO0, MACRO1, MACRO2, MACR
O3, MACRO4, ..., MACRO [N-1], MA
CRO [N] ... Macro core N ... Number of test mode setting terminals P2 ... Decoders T14, T16, T18, T110, ..., T1 [N-
1], T1 [N] ... I / O mode control terminals TBI1, ..., TBI [N-1], TBI [N] ... Test input terminals TBO1, TBO2, TBO3, ..., TBO [N-
1], TBO [N] ... Test output terminal TEST ... Test mode setting terminals TEST1, TEST2, ..., TEST [N-1], T
EST [N] ... External bidirectional terminal

Claims (6)

(57) [Claims] 1. A first-type macro core having a plurality of test input / output terminals and a test output terminal commonly connected to the test input terminal, a smaller number of test input / output terminals than the first-type macro core, and the test. A plurality of second type macro cores each having a test output terminal commonly connected to an input terminal, and a terminal for setting a test mode of the first type macro core, which is used for setting a test mode of the second type macro core. The test mode setting terminal also serving as the input / output mode control terminal of the external bidirectional terminal and the test output terminal of the first type macro core and / or the second type macro core not selected as the test mode, A bidirectional circuit that sets high impedance according to the signal level applied to the mode control terminal Macro core test apparatus characterized by having. 2. The first type macro core and / or the second type macro core switches from a normal operation mode to a test mode when set to a first logic value, and the test input terminal and the test output terminal are enabled. The macro core test device according to claim 1 , wherein the circuit configuration is such that a signal is directly applied to the test input terminal from the test mode setting terminal in the test mode. 3. A selection circuit for setting one of a plurality of the second type macro cores to a first logical value in accordance with a combination of signal levels input from the external bidirectional terminals. The macro core test apparatus according to claim 1 or 2 . 4. A first type macro core having a plurality of test input / output terminals and a test output terminal commonly connected to the test input terminal, a smaller number of test input / output terminals than the first type macro core, and the test. A plurality of second type macro cores each having a test output terminal commonly connected to an input terminal, and a terminal for setting a test mode of the first type macro core, which is used for setting a test mode of the second type macro core. The test of the first type macro core and / or the second type macro core not selected as a test mode for an LSI having a test mode setting terminal that also functions as an input / output mode control terminal of an external bidirectional terminal The output terminal goes high depending on the signal level applied to the input / output mode control terminal.
Characterized by having a step of setting impedance
Macro core test how. 5. The first type macro core and / or the second type macro core is switched from a normal operation mode to a test mode when set to a first logic value, and the test input terminal and the test output terminal are enabled. The macro core test method according to claim 4 , wherein a signal is directly applied to the test input terminal from the test mode setting terminal in the test mode. 6. A step of setting one of a plurality of the second type macro cores to a first logical value according to a combination of signal levels input from the external bidirectional terminals. The macro core test method according to claim 4, wherein