JPH0580131A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate production of test data for inspection for a logical integrated circuit constructed by an easy-to-inspect design method, and reduce the number of data pieces. CONSTITUTION:A test circuit part 4 is installed in an input/output buffer and is connected to form a shift register. This is partitioned into input and output to form shift registers A6, B5, which are tied into one by a changeover switch 9, or are switched separately to be connected with signal lines 7, 8 constituting detours. Thus the test data can be prepared independently because connections are made while partitioning is made into the input buffer part and output buffer part. Also it is possible to reduce the test data of the test circuit portion of a single side buffer, which allows shortening of the inspection time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit, and more particularly to a circuit configuration for facilitating inspection of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art There is a scan path method in a conventional design for facilitating inspection of a semiconductor integrated circuit.

FIG. 3 is a circuit diagram of a conventional logic integrated circuit, in which the scan path method is extended to an integrated circuit on a substrate.
This is an example of a technique called undary-scan (I
See EEE 1149.1-1990).

As shown in FIG. 3, a test circuit section 6 is incorporated between an internal logic circuit 3 of an integrated circuit 2 mounted on a substrate 1 and an input / output terminal 8 in addition to a signal line 7 for normal operation. Then, the test circuit unit 6 is connected in series during the test to form a shift register.

At this time, the test terminals of the integrated circuits 2 having the same structure are connected in series on the substrate 1 to form a dedicated path on the substrate 1 through which the test data passes.

As described above, since the integrated circuit 2 mounted can be accessed from the external test terminals scan-in and scan-out 4, 5, data is sent to the test circuit section 6 inside the integrated circuit 2 through this test data dedicated path. Perform an inspection.

[0007]

However, with respect to the above-mentioned conventional structure, the input / output buffers are not necessarily separated and connected to form the shift register in the package used. For this reason, the shift register formed by the test circuit unit 6 incorporated in the input / output buffer mixes input and output, and it is very difficult to create test data. Further, since all the test circuit units 6 of the input / output buffers of the circuit are connected, even if only the test data to the input buffer or the output buffer is required depending on the test contents, the data for all the test circuit units can be obtained. There were issues such as having to create it.

The present invention has been made in view of the above problems, and registers of a test circuit portion formed inside a logic integrated circuit are divided into input / output buffers to form shift registers regardless of the positions of terminals. It is an object of the present invention to provide a logic integrated circuit which can easily generate test data and can reduce the number of data.

[0009]

SUMMARY OF THE INVENTION A logic integrated circuit of the present invention is an integrated circuit having a plurality of buffer circuits for input and output on the periphery of a chip and each of the buffer circuits having a function of forming a sequential circuit. , And at least two shift registers formed by connecting between the adjacent buffer circuits and between the non-adjacent buffer circuits.

Further, it is preferable to have a switch circuit capable of selecting a series connection between the two or more shift registers and a connection to a bypass that logically skips one or more shift registers connected in series. Characterize.

[0011]

According to the above structure, since two or more shift registers are formed by connecting the adjacent buffer circuits and the non-adjacent buffer circuits, the input buffer circuit and the output buffer circuit are divided regardless of the positions of the terminals. And a shift register can be formed.

Alternatively, by selectively switching a series connection between a plurality of shift registers and a connection to a bypass that logically skips, it is possible to easily generate test data, reduce test data, and perform an inspection process for matching. It is possible to improve efficiency.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a logic integrated circuit according to a first embodiment of the present invention.

In the figure, in the internal logic circuit 1 on the integrated circuit 3, each input terminal x ₁ -x _n , output terminal y _1-.
The test circuit unit 4 having y _n is connected, and the test circuit units 4 of the input buffers of the internal logic circuit 1 are connected to each other at the input terminals x ₁ -x _n to form the shift register A6.

On the other hand, at the output terminals y ₁ -y _n , the test circuit portions 4 of the output buffer of the internal circuit 1 are connected to form a shift register B 5, and the shift register B 5 is connected to the control circuit 2 from the data input a and the data output b. It is configured to exchange data.

Next, the operation will be described.

A shift register A formed by connecting test circuit sections 4 of the input buffer at input terminals x ₁ -x _10.
6, the data input a- control circuit _{2-x 1 -x 2 ... x} 10 -
The connection path of the control circuit 2-data output b is taken.

On the other hand, the shift register B5 formed by connecting the test circuit sections 4 of the output buffers at the output terminals y ₁ -y ₆ includes a data input a-control circuit 2-y ₁ -y ₂ ... y.
₆ -Control circuit 2-A connection path of data output b is taken.

As described above, since the shift register A6 and the shift register B5 are separated from each other, when it is necessary to exchange data with the test circuit section 4 of the input buffer or the output buffer according to the content of the test, the shift register A6 and the shift register B5 are separated. A
6 or the shift register B5 can be selected to exchange data. Compared with the conventional example, the exchange of data with the shift register formed by connecting the test circuit units of all the input / output buffers in series is performed. For example, the amount of data may be as small as the number of the test circuit units 4 of the input buffer or the output buffer, and the input buffer and the output buffer are separately connected to generate data, so that the data can be generated independently.

The second embodiment of the present invention will be described below.

FIG. 2 is a circuit diagram of a logic integrated circuit according to a second embodiment of the present invention.

In this case, the same components as those in the previous embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 2, reference numeral 7 is a detour c connecting the shift register A6 and the control circuit 2, and 8 is a detour d connecting the shift register B5 and the control circuit 2. Reference numeral 9 denotes a switch circuit for switching the shift register A6 bypass circuit c7 and the shift register B5 bypass circuit d8.

Next, the operation will be described.

[0026] In this case are those by selectively using three connection path for exchanging data, the first First, a shift register A6 to form an input terminal x ₁ -x _10, the output terminal y ₁ -y ₆ in the case of forming a single shift register by connecting the shift register B5 to form, by connecting shift registers A6 and B5 by the switch circuit 9, a- control circuit _{2-x 1 -x 2 ... x} 10 -Switch 9-
y ₆ -y ₅ ... y ₁ - control circuit 2-b of the test data takes a connection path that exchanges are carried out.

The second is a case where the switch circuit 9 disconnects the shift registers A6 and B5, and data is exchanged only by the shift register A6. The shift register A6 is connected to the control circuit 2 by the detour c7. to, a- control circuit _{2-x 1 -x 2 ... x} 10 - switch 9-
Test data is exchanged with the shift register A6 through a connection path of the detour circuit c7-control circuit 2-b.

Thirdly, the switch circuit 9 separates the shift registers A6 and B5, the shift register B5 is connected to the control circuit 2 by the detour d8, and the test data is exchanged only with the shift register B5. The connection path is a-control circuit 2-detour circuit d8-switch 9-
y _6- y ₅ ... y ₁ -The control circuit 2-b is provided, and data is exchanged with the shift register B 5.

In this way, the shift registers A6 and B5 are set to 1
The shift register A6 of the input buffer unit or the output buffer unit is used because it is used as a book shift register or one of the shift registers A6 and B5 is used.
It is possible to omit one of the data exchanges of B5 and the data required for the inspection can be reduced accordingly, so that the inspection time can be shortened.

[0030] Although the embodiment has been described as a total of 16 terminal and _{x 1 -x 10, y 1 -y} 6 course x ₁ -x _n, y
_A similar combination of shift registers can be taken even if the number is increased like _1- y _n .

For example, if test data for inspection is created for an integrated circuit having 100 input terminals and 200 output terminals in total, the test data of the internal logic circuit 1 of the integrated circuit is input. If only the test circuit section 4 of the buffer needs the test data, in the conventional configuration, the data for all input buffers, that is, 200 patterns must be created. However, in the present invention, only the test circuit section 4 of the input buffer is accessed. Since it is possible, 100 patterns are enough.

Similarly, when the test data is required only in the output buffer, 100 patterns will suffice, and accordingly, the creation is easy and the number of data is considerably reduced.

[0033]

According to the present invention, the shift register in the test circuit portion formed inside the integrated circuit is divided into the input buffer and the output buffer to form the shift register regardless of the arrangement of the terminals. Can be considered separately for the input buffer section data and the output buffer section data at the time of creating, and there is an effect that the entire test data can be easily created.

Further, when the test data is required only for the test circuit section of the input buffer or the output buffer depending on the contents of the test, only the test circuit section of the input buffer or the output buffer can be accessed.
Compared to the conventional test circuit unit for all I / O buffers, the test data to be sent to the test circuit unit for output buffers or input buffers is no longer required, resulting in a reduction in the total number of test data and a reduction in inspection time. It has the effect of shortening.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a logic integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a logic integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional logic integrated circuit.

[Explanation of symbols]

1 internal circuit 2 control circuit 3 integrated circuit 4 test circuit section 5 shift register B 6 shift register A 7 detour c 8 detour d 9 changeover switch circuit x ₁ -x _n input terminal y ₁ -y _n output terminal a data input b Data output

Claims (2)

[Claims] 1. An integrated circuit having a plurality of buffer circuits for input and output on the periphery of a chip and each of the buffer circuits having a function of forming a sequential circuit, wherein the buffers between adjacent buffer circuits and the buffers not adjacent to each other. A logic integrated circuit having at least two shift registers formed by connecting circuits. 2. An integrated circuit having a plurality of buffer circuits for input and output on the periphery of a chip and each of the buffer circuits having a function capable of forming a sequential circuit, wherein the buffers between adjacent buffer circuits and the buffers not adjacent to each other. At least two or more shift registers formed by connecting circuits, a serial connection between the two or more shift registers, and a detour circuit logically skipped by one or more shift registers connected in series A logic integrated circuit having a switch circuit capable of selecting connection to and from.