JP2000046909A - Semiconductor integrated-circuit device and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To halve the test time of a semiconductor integrated-circuit device by a method wherein serial data is inputted at the rise and the fall of a clock. SOLUTION: Input data from a serial-data input terminal 2 is inputted to data holding registers 13 to 16 at the rise edge of a clock terminal 4, and it is inputted to test-data holding registers 17, 18 at its fall edge. Outputs of the respective registers are selected by selection circuits 9 to 12 so as to be connected to data buses 5 to 8. A test control signal 1 in a nontesting state is in a state 0, the respective selection circuits 9 to 12 connect respective outputs of the data holding registers 13 to 16 to the data buses 5 to 8. Consequently, since the input data is transmitted to the data buses 5 to 8, the required number of clocks which are inputted to the clock terminal 4 is four. When the test control signal 1 in a test state is in a state 1, the respective selection circuits 9 to 12 connect outputs of the test-data holding registers 17, 18 (the data holding registers 13 to 16) the data buses 5, 7 (6, 8). Consequently, the required number of clocks which are inputted to the clock terminal 4 is two.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique for testing a semiconductor integrated circuit device having a serial data input circuit.

[0002]

2. Description of the Related Art In a test of a semiconductor integrated circuit device having a conventional serial data input circuit, only one of the rising edge and the falling edge of a clock is used to input serial data.

[0003]

In a test of a semiconductor integrated circuit device by serial data input, one clock is required to input one data, so that the number of data and the number of clocks are increased, and the tester resources and the power consumption are increased. This has led to an increase in the test time of the semiconductor integrated circuit device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and a semiconductor integrated circuit device capable of performing serial data input at both rising and falling edges of a clock depending on the state of a certain signal during a test. The purpose is to provide.

[0005]

According to the present invention, there is provided a semiconductor integrated circuit circuit comprising: a) in a semiconductor integrated circuit device having a serial data input circuit, a rising edge of a clock for inputting serial data depending on a state of a certain signal during a test; The serial data is input by both the rising and falling edges of the clock during the test. The semiconductor integrated circuit device is tested using the function.

[0006]

Embodiments of the present invention will be described below.

FIG. 1 shows a diagram in which the present invention is applied to a serial data input circuit in a semiconductor integrated circuit. In FIG. 1, 2 is a serial data input signal, 13 to 16 are data holding registers, 17 to 18 are test data holding registers, 3 is a reset signal, and 4 is a clock signal. 5 to 8 are data bus signals in the semiconductor integrated circuit, 9 to 12 are selection circuits, and 1 is a control signal for the test.

Hereinafter, the operation will be described. Data input from the serial data input signal 2 is supplied to the data holding register 13 by the rising edge of the clock signal 4.
, And the test data holding registers 17 to 18 at the falling edge of the clock signal 4.
The output of each register is selected by selection circuits 9 to 12 and connected to data bus signals 5 to 8. When the test control signal 1 is set to the 0 state during the non-test time, the selection circuit 9
2 is a data bus signal 5 for the output of the data holding register 13, a data bus signal 6 for the output of the data holding register 14, a data bus signal 7 for the output of the data holding register 15, and a data bus signal 8 for the output of the data holding register 16.
Connect to In this state, the number of clocks input to the clock signal 4 required for transmitting data input from the serial data input signal 2 to the data bus signal is four. Assuming that the test is in the 1 state of the test control signal 1, the selection circuits 9 to 12 use the output of the test data holding register 17 as the data bus signal 5, the output of the data holding register 13 as the data bus signal 6, and the test data. The output of the holding register 18 is connected to the data bus signal 7, and the output of the data holding register 14 is connected to the data bus signal 8. In this state, the number of clocks input to the clock signal 4 required for transmitting the data input from the serial data input signal 2 to the data bus signal is two.

Although the test data holding register is provided in the present embodiment, it can be easily realized by configuring the normal data holding register to operate at both the rising and falling edges of the clock during the test. It is.
In this embodiment, the serial data input circuit is for 4 bits. However, the present invention can be easily realized with a circuit configuration of more bits.

[0010]

As described above, according to the present invention,
In a semiconductor integrated circuit device having a serial data input circuit, a function that allows serial data to be input by both rising and falling edges of a clock for inputting serial data depending on the state of a certain signal during a test During testing, serial data is input at both rising and falling edges of the clock, and by using that function,
The tester resources can be reduced and the test time of the semiconductor integrated circuit device can be halved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a serial data input circuit of a semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test control signal 2 Serial data input signal 3 Reset signal 4 Clock signal 5 Data bus signal 6 Data bus signal 7 Data bus signal 8 Data bus signal 9 Selection circuit 10 Selection circuit 11 Selection circuit 12 Selection circuit 13 Data holding register 14 Data Holding register 15 Data holding register 16 Data holding register 17 Test data holding register 18 Test data holding register

Claims (2)

[Claims] In a semiconductor integrated circuit device having a serial data input circuit, serial data is input by both rising and falling edges of a clock for inputting serial data depending on the state of a certain signal during a test. A semiconductor integrated circuit device having a function of enabling a semiconductor integrated circuit. 2. A semiconductor integrated circuit device according to claim 1, wherein serial data is input at both rising and falling edges of the clock, and the function is used to test the semiconductor integrated circuit device. Characteristic test method.