CN116454069A - Semiconductor chip and HTOL, delay and overall test method thereof - Google Patents

Semiconductor chip and HTOL, delay and overall test method thereof Download PDF

Info

Publication number
CN116454069A
CN116454069A CN202310703192.1A CN202310703192A CN116454069A CN 116454069 A CN116454069 A CN 116454069A CN 202310703192 A CN202310703192 A CN 202310703192A CN 116454069 A CN116454069 A CN 116454069A
Authority
CN
China
Prior art keywords
circuit
tested
circuits
multiplexer
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202310703192.1A
Other languages
Chinese (zh)
Other versions
CN116454069B (en
Inventor
王涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Zhongan Chenhong Technology Co ltd
Original Assignee
Shenzhen Zhongan Chenhong Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Zhongan Chenhong Technology Co ltd filed Critical Shenzhen Zhongan Chenhong Technology Co ltd
Priority to CN202310703192.1A priority Critical patent/CN116454069B/en
Publication of CN116454069A publication Critical patent/CN116454069A/en
Application granted granted Critical
Publication of CN116454069B publication Critical patent/CN116454069B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a semiconductor chip and an HTOL, time delay and integral test method thereof, wherein in the test process of the semiconductor chip, I/O circuits to be tested can be communicated through a selection circuit, so that signals can be transmitted in all the I/O circuits to be tested, and the HTOL test, the time delay test and the integral test are completed. In addition, in the HTOL test process of the semiconductor chip, the tester can provide test signals with target frequency, and the test signals can be flexibly matched with the I/O circuit working frequency of the semiconductor chip, so that the HTOL test requirement is met. In addition, the test of the semiconductor chip provided by the invention can select all I/O circuits as I/O circuits to be tested to achieve the purpose of testing all I/O circuits at one time, or select part of I/O circuits as I/O circuits to be tested to achieve the purpose of testing the I/O circuits in parts, so that the semiconductor chip is better tested, and the test effect is improved.

Description

Semiconductor chip and HTOL, delay and overall test method thereof
Technical Field
The present invention relates to the field of semiconductor chip testing, and more particularly, to a semiconductor chip and HTOL (High temperature operating life ) testing method, a delay testing method, and an overall testing method thereof.
Background
The HTOL test is a basic test mode for verifying the reliability of the semiconductor chip, and the service life of the semiconductor chip is tested through the HTOL test, so that the semiconductor chip can normally work in the service life period, and the performance degradation can meet the working requirements. During HTOL testing, logic to be tested is required to work so as to achieve the effect of HTOL testing. However, in the conventional HTOL test of the semiconductor chip, the HTOL test machine is required to provide test signals for the semiconductor chip, but the frequency of the test signals provided by the HTOL test machine is limited, and the test signals cannot be flexibly matched with the I/O circuit working frequency of the semiconductor chip, so that the test effect is poor.
Disclosure of Invention
In view of the above, the invention provides a semiconductor chip and an HTOL, delay and overall test method thereof, which effectively solve the existing technical problems, can perform better test on the semiconductor chip and improve the test effect.
In order to achieve the above purpose, the technical scheme provided by the invention is as follows:
a semiconductor chip, comprising:
the input ports of the I/O circuits are connected with signals, and the bidirectional ports of the I/O circuits output signals; when the bidirectional port of the I/O circuit is connected with a signal, the output port of the I/O circuit outputs the signal;
The output side of the selection circuit is electrically connected with the I/O circuit, the input side of the selection circuit is connected with a functional signal and is electrically connected with a tester, and the tester is used for outputting a test signal of target frequency;
the selection circuit is used for selectively controlling at least part of the I/O circuits, and the output port of the former I/O circuit is communicated with the input port of the latter I/O circuit; and the selection circuit is also used for selecting the test signal or the functional signal to be transmitted to the I/O circuit.
Correspondingly, the invention also provides an HTOL test method of the semiconductor chip, which is used for testing the semiconductor chip and comprises the following steps:
selecting a first I/O circuit to be tested from the plurality of I/O circuits;
sequentially dividing the first I/O circuit to be tested into a first circuit group to a first H circuit group to be tested, wherein any one of the first circuit group to the first H-1 circuit group to be tested comprises two first I/O circuits to be tested, the first H circuit group to be tested comprises one or two first I/O circuits to be tested, and H is an integer greater than 1;
Electrically connecting the two bidirectional ports of the two first I/O circuits to be tested in the first circuit group to be tested;
powering up the semiconductor chip under HTOL test conditions;
according to the sequence of dividing the first to-be-detected I/O circuit into first to-be-detected circuit groups, the selection circuit communicates an output port of the last first to-be-detected I/O circuit in the g first to-be-detected circuit group with an input port of the last first to-be-detected I/O circuit in the g+1th first to-be-detected circuit group, and g is a positive integer smaller than H;
the selection circuit selects the test signal to transmit to the first I/O circuit to be tested.
Correspondingly, the invention also provides a delay test method of the semiconductor chip, which is used for testing the semiconductor chip and comprises the following steps:
selecting a second I/O circuit to be tested from the plurality of I/O circuits;
selecting an initial second I/O circuit to be tested and a second I/O circuit to be tested at the tail end from the second I/O circuit to be tested, sequentially dividing the rest of the second I/O circuits to be tested into a first second circuit group to an L second circuit group to be tested along the direction from the initial second I/O circuit to the second I/O circuit to be tested at the tail end, wherein any one of the first second circuit group to the L second circuit group to be tested comprises two second I/O circuits to be tested, and L is an integer greater than 1;
Electrically connecting the two bidirectional ports of the two second I/O circuits to be tested in the second circuit group to be tested;
powering up the semiconductor chip;
according to the sequence of dividing the second to-be-detected I/O circuit groups by the second to-be-detected I/O circuit, the selection circuit is used for communicating an output port of the initial second to-be-detected I/O circuit with an input port of a previous second to-be-detected I/O circuit in a first second to-be-detected circuit group, communicating an output port of a next second to-be-detected I/O circuit in a t second to-be-detected circuit group with an input port of a previous second to-be-detected I/O circuit in a t+1th second to-be-detected circuit group, and communicating an output port of a next second to-be-detected I/O circuit in an L second to-be-detected circuit group with an input port of a second to-be-detected I/O circuit at the tail end, wherein t is a positive integer smaller than L;
and inputting a delay test signal to the bidirectional port of the initial second I/O circuit to be tested, and receiving a feedback delay test signal from the bidirectional port of the second I/O circuit to be tested at the tail end.
Correspondingly, the invention also provides a method for integrally testing the semiconductor chip, which comprises the following steps:
performing delay test on the semiconductor chip according to the delay test method;
Performing HTOL testing on the semiconductor chip according to the HTOL testing method;
and after HTOL testing, testing the semiconductor chip again according to the delay test method.
Compared with the prior art, the technical scheme provided by the invention has at least the following advantages:
the invention provides a semiconductor chip and HTOL, delay and overall test methods thereof, wherein the semiconductor chip comprises a selection circuit and a tester, and in the test process of the semiconductor chip, I/O circuits to be tested can be communicated through the selection circuit, so that signals can be transmitted in all the I/O circuits to be tested, and HTOL test, delay test and overall test processes are completed. In addition, in the HTOL test process of the semiconductor chip, the tester can provide test signals with target frequency, and the test signals can be flexibly matched with the I/O circuit working frequency of the semiconductor chip, so that the HTOL test requirement is met. In addition, the test of the semiconductor chip provided by the invention can select all I/O circuits as I/O circuits to be tested to achieve the purpose of testing all I/O circuits at one time, or select part of I/O circuits as I/O circuits to be tested to achieve the purpose of testing the I/O circuits in parts, so that the semiconductor chip is better tested, and the test effect is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an I/O circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another semiconductor chip according to an embodiment of the present invention;
fig. 4 is a flowchart of an HTOL testing method for a semiconductor chip according to an embodiment of the present invention;
fig. 5 is a schematic diagram of signal transmission of a semiconductor chip according to an embodiment of the present invention;
fig. 6 is a flowchart of a delay test method of a semiconductor chip according to an embodiment of the present invention;
fig. 7 is a schematic diagram of signal transmission of another semiconductor chip according to an embodiment of the present invention;
fig. 8 is a schematic diagram of signal transmission of another semiconductor chip according to an embodiment of the present invention;
Fig. 9 is a flowchart of an overall testing method of a semiconductor chip according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As described in the background art, the HTOL test is a basic test method for verifying the reliability of a semiconductor chip, and the service life of the semiconductor chip is tested by the HTOL test, so that the semiconductor chip can normally work in the service life period, and the performance degradation can meet the working requirements. During HTOL testing, logic to be tested is required to work so as to achieve the effect of HTOL testing. However, in the conventional HTOL test of the semiconductor chip, the HTOL test machine is required to provide test signals for the semiconductor chip, but the frequency of the test signals provided by the HTOL test machine is limited, and the test signals cannot be flexibly matched with the I/O circuit working frequency of the semiconductor chip, so that the test effect is poor.
Based on the above, the embodiment of the invention provides a semiconductor chip and an HTOL, time delay and overall test method thereof, which effectively solve the existing technical problems, can perform better test on the semiconductor chip and improve the test effect.
In order to achieve the above objective, the technical solutions provided by the embodiments of the present invention are described in detail below, with reference to fig. 1 to 9.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a semiconductor chip according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of an I/O circuit according to an embodiment of the present invention, where the semiconductor chip includes:
a plurality of I/O circuits 100, where the I/O circuits 100 include an input port I, an output port C, and a bidirectional port PAD, and when the input port I of the I/O circuit is connected to a signal, the bidirectional port PAD of the I/O circuit outputs the signal; and when the bidirectional port PAD of the I/O circuit is connected with a signal, the output port C of the I/O circuit outputs the signal.
And a selection circuit 200, wherein an output side of the selection circuit 200 is electrically connected with the I/O circuit 100, an input side of the selection circuit 200 is connected with a function signal Vg and is electrically connected with a tester 300, and the tester 300 is used for outputting a test signal Vc of a target frequency. The selection circuit 200 is configured to selectively control at least a part of the I/O circuits 100, where an output port C of a previous one of the I/O circuits 100 is in communication with an input port I of a next one of the I/O circuits 100; and, the selection circuit 200 is further configured to select the test signal Vc or the function signal Vg to be transmitted to the I/O circuit 100.
Referring to fig. 2, in the I/O circuit 100 provided in the embodiment of the present invention, I is an input port, C is an output port, and PAD is a bidirectional port, i.e., the bidirectional port PAD is both an output and an input. When the input port I has an input signal, signal transmission from the input port I to the bidirectional port PAD is realized according to control; and when the bidirectional port PAD has an input signal, realizing signal transmission from the bidirectional port PAD to the output port C according to control. It should be noted that the I/O circuit shown in fig. 2 illustrates a signal transmission process according to a port only, and is not limited to a specific circuit connection structure. And the function signal Vg is a signal with functions of driving, controlling and the like generated in the normal working process of the semiconductor chip.
It can be appreciated that in the technical scheme provided by the embodiment of the invention, the semiconductor chip comprises the selection circuit and the tester, and in the testing process of the semiconductor chip, the I/O circuits to be tested can be communicated through the selection circuit, so that signals can be transmitted in all the I/O circuits to be tested, and the processes of HTOL testing, time delay testing and overall testing are completed. In addition, in the HTOL test process of the semiconductor chip, the tester can provide test signals with target frequency, and the test signals can be flexibly matched with the I/O circuit working frequency of the semiconductor chip, so that the HTOL test requirement is met. In addition, the test of the semiconductor chip provided by the embodiment of the invention can select all I/O circuits as I/O circuits to be tested to achieve the purpose of testing all I/O circuits at one time, or select part of I/O circuits as I/O circuits to be tested to achieve the purpose of testing the I/O circuits in parts, so that the semiconductor chip is better tested, and the test effect is improved.
The test related circuit of the semiconductor chip provided by the embodiment of the invention is described in more detail below with reference to the accompanying drawings. Referring to fig. 3, a schematic structural diagram of another semiconductor chip according to an embodiment of the present invention is shown, wherein the plurality of I/O circuits are defined as a first I/O circuit 101 to an nth I/O circuit 10N, where N is an integer greater than or equal to 2.
The selection circuit includes: the first multiplexer 211 to the nth first multiplexer 21N, and the first second multiplexer 221 to the mth second multiplexer 22M, when N is an even number, then M is N/2; and M is (N+1)/2 when N is an odd number.
The output end of the kth first multiplexer is electrically connected with the input port I of the kth I/O circuit, and k is a positive integer less than or equal to N. I.e. the output of the first multiplexer 211 is electrically connected to the input port I of the first I/O circuit 101, the output of the second first multiplexer 212 is electrically connected to the input port I of the second I/O circuit 102, and so on, the output of the nth first multiplexer 21N is electrically connected to the input port I of the nth I/O circuit 10N.
The first input end of the ith first multiplexer is electrically connected with the output end of the (i+1)/2 second multiplexers, the second input end of the ith first multiplexer is connected with the functional signal, and i is an odd number less than or equal to N; i.e. the first input of the first multiplexer 211 is electrically connected to the output of the first second multiplexer 221, the first input of the third first multiplexer 213 is electrically connected to the output of the second multiplexer 222, and so on, until the first input of the last odd first multiplexer is electrically connected to the output of the mth second multiplexer 22M; when N is an even number as shown in fig. 3, the first input terminal of the N-1 th first multiplexer 21 (N-1) is electrically connected to the output terminal of the M-th second multiplexer 22M.
The first input end of the j-th first multiplexer is electrically connected with the output end of the j-1-th I/O circuit, the second input end of the j-th first multiplexer is connected with the functional signal, the output end of the j-th I/O circuit is electrically connected with the second input end of the j/2-th second multiplexer and the first input end of the j/2+1-th second multiplexer, the first input end of the first second multiplexer is electrically connected with the tester, and j is an even number less than or equal to N. I.e. the first input of the second first multiplexer 212 is electrically connected to the output port C of the first I/O circuit 101, the first input of the fourth first multiplexer 214 is electrically connected to the output port C of the third I/O circuit 103, and so on, when N is even as shown in fig. 3, the first input of the nth first multiplexer 21N is electrically connected to the output port C of the N-1 th I/O circuit 10 (N-1). And, the output port C of the second I/O circuit 102 is electrically connected to the second input terminal of the first second multiplexer 221 and the first input terminal of the second multiplexer 222, and so on, when N is an even number as shown in fig. 3, the output port C of the nth I/O circuit 10N is electrically connected to the second input terminal of the mth second multiplexer 22M.
It should be noted that, in the embodiment of the present invention, the semiconductor chip shown in fig. 3 is illustrated by taking N as an even number as an example; when N is an odd number, the connection manner described in the above embodiment is also identical, and redundant description is not made for this invention. The selection circuit provided in the embodiment of the present invention is not limited to the component devices and the connection modes shown in fig. 3, and in other embodiments of the present invention or the selection circuit provided in the present invention may be other component devices and connection modes, which is not particularly limited.
In an embodiment of the present invention, the tester provided by the present invention is a PLL (phase locked loop, phase-locked loop), and the present invention is not limited in particular to this type of tester.
According to the embodiment of the invention, the target frequency of the test signal is fixed, and the target frequency is the same as the working frequency of the I/O circuit, so that the target frequency of the test signal is matched with the working frequency of the I/O circuit, and a high-speed I/O circuit working at 200MHz, for example, can be tested more accurately. Or, the target frequency of the test signal provided by the embodiment of the invention is adjustable, and the adjustable range of the target frequency comprises the working frequency of the I/O circuit, so that the semiconductor chip can be tested more accurately; the semiconductor chip can be tested more flexibly by adjusting the frequency of the test signal.
Correspondingly, the embodiment of the invention also provides an HTOL testing method of the semiconductor chip, which is used for testing the semiconductor chip provided by any one of the embodiments. Referring to fig. 4, a flowchart of an HTOL testing method of a semiconductor chip according to an embodiment of the present invention is shown, where the HTOL testing method includes:
s11 an I/O circuit to be tested is selected.
The first I/O circuit to be tested is selected from the plurality of I/O circuits, where the first I/O circuit to be tested may be an I/O circuit adjacent to each other, or may be an I/O circuit spaced apart, which is not specifically limited in this invention.
S12, dividing the circuit group to be tested.
The first I/O circuit to be tested is divided into a first circuit group to a first H circuit group to be tested in sequence, any one of the first circuit group to the first H-1 circuit group to be tested comprises two first I/O circuits to be tested, the first H circuit group to be tested comprises one or two first I/O circuits to be tested, and H is an integer greater than 1.
It can be understood that the number of the first I/O circuits to be tested selected from the plurality of I/O circuits may be odd or even, and when the number of the first I/O circuits to be tested selected is odd, the H first circuit group to be tested includes a first I/O circuit to be tested; when the number of the selected first I/O circuits to be tested is even, the H first circuit group to be tested comprises two first I/O circuits to be tested.
S13, connecting the I/O circuit to be tested outside the semiconductor chip.
Electrically connecting the two bidirectional ports of the two first I/O circuits to be tested in the first circuit group to be tested, wherein the bidirectional ports of the I/O circuits are connected with epitaxial bonding pads, pins and the like in the semiconductor chip; according to the embodiment of the invention, the two bidirectional ports of the two first I/O circuits to be tested are electrically connected, namely, corresponding bonding pads, pins and the like of the semiconductor chip are connected outside the semiconductor chip through test circuits and the like.
S14, powering up the semiconductor chip under the HTOL test condition.
It should be noted that, the temperature, the voltage, etc. under the HTOL test conditions provided by the embodiments of the present invention are not particularly limited, and specific selection is required according to the actual test.
S15, selecting to communicate the output port and the input port in the semiconductor chip.
According to the sequence of dividing the first to-be-detected I/O circuit groups by the first to-be-detected I/O circuit, the selection circuit communicates the output port of the last to-be-detected I/O circuit in the g first to-be-detected circuit group with the input port of the last to-be-detected I/O circuit in the g+1th first to-be-detected circuit group, and g is a positive integer less than H. Therefore, through the two-way ports, the output ports and the input ports of different I/O circuits to be tested are communicated with each other in the mode, the sequence of the first circuit group to be tested is divided along the first I/O circuit to be tested, a signal transmission path from the initial first I/O circuit to the first I/O circuit to be tested at the tail end is formed, and signal transmission and chip test can be completed when signals are input.
S16, the selection circuit selects the test signal to transmit to the first I/O circuit to be tested.
It should be noted that, in the embodiment of the present invention, "the previous first I/O circuit to be tested" and "the next first I/O circuit to be tested" are defined before and after each other in the sequential direction from the first circuit group to the H circuit group to be tested.
In the above description, during the HTOL test of the semiconductor chip, the selection circuit is used to connect the I/O circuits to be tested, so that signals can be transmitted in all the I/O circuits to be tested, thereby completing the HTOL test. In addition, in the HTOL test process of the semiconductor chip, the tester can provide a test signal with a target frequency, flexibly match with the I/O circuit working frequency of the semiconductor chip, meet the HTOL test requirement and improve the test effect.
The HTOL test method provided by the embodiments of the present invention is described in more detail below in connection with the circuit structure of a specific semiconductor chip. Defining the plurality of I/O circuits as a first I/O circuit to an N-th I/O circuit, N being an integer greater than or equal to 2; the selection circuit includes: the first to the nth first multiplexers and the first to the mth second multiplexers, when N is even, then M is N/2; and M is (N+1)/2 when N is an odd number; the output end of the kth first multiplexer is electrically connected with the input port of the kth I/O circuit, and k is a positive integer less than or equal to N; the first input end of the ith first multiplexer is electrically connected with the output end of the (i+1)/2 second multiplexers, the second input end of the ith first multiplexer is connected with the functional signal, and i is an odd number less than or equal to N; the first input end of the j-th first multiplexer is electrically connected with the output end of the j-1-th I/O circuit, the second input end of the j-th first multiplexer is connected with the functional signal, the output end of the j-th I/O circuit is electrically connected with the second input end of the j/2-th second multiplexer and the first input end of the j/2+1-th second multiplexer, the first input end of the first second multiplexer is electrically connected with the tester, and j is an even number less than or equal to N.
The HTOL testing method comprises the following steps: selecting a first I/O circuit to be tested from the first I/O circuit to the Nth I/O circuit, wherein the first I/O circuit to be tested comprises the first I/O circuit. Dividing the first I/O circuit to be tested into a first I/O circuit group to a first H first I/O circuit group according to the sequence from the first I/O circuit to the N I/O circuit, wherein any one of the first I/O circuit group to the first H-1 first I/O circuit group comprises two first I/O circuits to be tested, the H first I/O circuit group comprises one or two first I/O circuits to be tested, and the latter one of the g first I/O circuits to be tested is adjacent to the former one of the g+1th I/O circuits to be tested. And electrically connecting the two bidirectional ports of the two first I/O circuits to be tested in the first circuit group to be tested. The semiconductor chip is powered up under HTOL test conditions. And controlling the first multiplexer and the second multiplexer which are correspondingly and electrically connected with the first I/O circuit to be tested to gate the first input end, and simultaneously, transmitting the test signal to the input port of the first I/O circuit by the first multiplexer and the first second multiplexer.
Referring specifically to fig. 5, a schematic signal transmission diagram of a semiconductor chip provided by an embodiment of the present invention is taken as an example, where N is 6 and six I/O circuits are all first I/O circuits to be tested, and signal trend (such as signal trend of dashed arrow in fig. 5) in the HTOL test process provided by the embodiment of the present invention is described in detail; wherein, in the order from the first I/O circuit 101 to the sixth I/O circuit 106, the first I/O circuit 101 and the second I/O circuit 102 form a first circuit group to be tested, the third I/O circuit 103 and the fourth I/O circuit 104 form a second first circuit group to be tested, and the fifth I/O circuit 105 and the sixth I/O circuit 106 form a third first circuit group to be tested; and includes first to sixth first multiplexers 211 to 216 and first to third second multiplexers 221 to 223.
Continuing to power up the semiconductor chip under HTOL test conditions, the tester 300 outputs test signals at a target frequency while both the first multiplexer and the second multiplexer gate the first input as shown in fig. 5; the test signal is transmitted to the first input terminal of the first second multiplexer 221, and then is output to the first input terminal of the first multiplexer 211 through the first second multiplexer 221, and the first multiplexer 211 transmits the test signal to the input port I of the first I/O circuit 101. The first I/O circuit 101 outputs the signal carrying the target frequency to the bi-directional port of the second I/O circuit 102 through its bi-directional port PAD, the second I/O circuit 102 outputs the signal carrying the target frequency to the first input of the second multiplexer 222, and so on until the signal carrying the target frequency is transmitted to the sixth I/O circuit 106, thereby completing the test of the semiconductor chip under the HTOL condition.
Correspondingly, the embodiment of the invention also provides a delay test method of the semiconductor chip, which is used for testing the semiconductor chip provided by any embodiment. Referring to fig. 6, a flowchart of a delay test method for a semiconductor chip according to an embodiment of the present invention is shown, where the delay test method includes:
s21, selecting an I/O circuit to be tested.
The second I/O circuit to be tested is selected from the plurality of I/O circuits, where the second I/O circuit to be tested may be an I/O circuit adjacent to each other, or may be an I/O circuit spaced apart, which is not particularly limited in the present invention.
S22, dividing the circuit group to be tested.
Selecting an initial second I/O circuit to be tested and a second I/O circuit to be tested at the tail end from the second I/O circuit to be tested, sequentially dividing the rest second I/O circuits to be tested into a first second circuit group to an L second circuit group to be tested along the direction from the initial second I/O circuit to the second I/O circuit to be tested at the tail end, wherein any one of the first second circuit group to the L second circuit group to be tested comprises two second I/O circuits to be tested, and L is an integer greater than 1.
It can be understood that when the delay test is performed on the semiconductor chip, the number of the selected second I/O circuits to be tested is an even number, and after the two circuits of the initial second I/O circuits to be tested and the second I/O circuits to be tested at the tail end are removed, the remaining even number of the second I/O circuits to be tested are divided into L second circuit groups to be tested, so that the rule that each second circuit group to be tested includes two second I/O circuits to be tested is satisfied.
S23, connecting the I/O circuit to be tested outside the semiconductor chip.
Electrically connecting the two bidirectional ports of the two second I/O circuits to be tested in the second circuit group to be tested, wherein the bidirectional ports of the I/O circuits are connected with epitaxial bonding pads, pins and the like in the semiconductor chip; according to the embodiment of the invention, the two bidirectional ports of the two first I/O circuits to be tested are electrically connected, namely, corresponding bonding pads, pins and the like of the semiconductor chip are connected outside the semiconductor chip through test circuits and the like.
S24, powering up the semiconductor chip.
It should be noted that, the delay test provided by the embodiment of the invention is performed under the parameter conditions of normal temperature, voltage and the like, the invention does not limit the specific numerical values of the parameters of the delay test, such as temperature, voltage and the like, and the specific selection is needed according to the actual test.
S25, selecting to communicate the output port and the input port in the semiconductor chip.
According to the sequence of dividing the second to-be-detected I/O circuit groups by the second to-be-detected I/O circuit, the selection circuit is used for communicating an output port of the initial second to-be-detected I/O circuit with an input port of a previous second to-be-detected I/O circuit in a first second to-be-detected circuit group, communicating an output port of a next second to-be-detected I/O circuit in a t second to-be-detected circuit group with an input port of a previous second to-be-detected I/O circuit in a t+1th second to-be-detected circuit group, and communicating an output port of a next second to-be-detected I/O circuit in an L second to-be-detected circuit group with an input port of a second to-be-detected I/O circuit at the tail end, wherein t is a positive integer smaller than L. Therefore, through the two-way ports, the output ports and the input ports of different I/O circuits to be tested are communicated with each other in the mode, the sequence of the second circuit group to be tested is divided along the second I/O circuits to be tested, a signal transmission path from the initial second I/O circuits to the second I/O circuits to be tested at the tail end is formed, and then signal transmission and chip test can be completed when signals are input.
S26, inputting a delay test signal to the bidirectional port of the initial second I/O circuit to be tested, and receiving a feedback delay test signal from the bidirectional port of the second I/O circuit to be tested at the tail end.
It can be understood that after receiving the feedback delay test signal through the bidirectional port of the second I/O circuit to be tested at the end, the degradation of the I/O circuit of the semiconductor chip is further determined whether to meet the requirement by comparing and analyzing the delay test signal with the feedback delay test signal.
In an embodiment of the present invention, the delay test of the semiconductor chip provided by the present invention may be performed by using ATE (automatic test equipment ), that is, the delay test signal is input to the test structure by the ATE, and after the feedback delay test signal is received by the ATE, the delay test signal and the feedback delay test signal are compared and analyzed, so as to determine whether the degradation of the I/O circuit of the semiconductor chip meets the requirement.
The delay test method of the semiconductor chip provided by the embodiment of the invention not only can carry out the transmission test of the delay test signals along the sequence of dividing the second circuit group to be tested along the second I/O circuit to be tested, but also can carry out the transmission test of the delay test signals further along the reverse sequence of dividing the second circuit group to be tested along the second I/O circuit to be tested on the basis of the test, thereby improving the test effect of the delay test. Namely, after receiving the feedback delay test signal from the bidirectional port of the second I/O circuit to be tested at the end, the delay test method further comprises the following steps:
According to the reverse sequence of the second to-be-detected I/O circuit dividing second to-be-detected circuit groups, the selection circuit is used for communicating an output port of the second to-be-detected I/O circuit at the tail end with an input port of a next second to-be-detected I/O circuit in an L-th second to-be-detected circuit group, communicating an output port of a previous second to-be-detected I/O circuit in a t+1th second to-be-detected circuit group with an input port of a next second to-be-detected I/O circuit in a t-th second to-be-detected circuit group, and communicating an output port of a previous second to-be-detected I/O circuit in a first second to-be-detected circuit group with an input port of the initial second to-be-detected I/O circuit; and inputting a delay test signal to the bidirectional port of the second I/O circuit to be tested at the tail end, and receiving a feedback delay test signal from the bidirectional port of the initial second I/O circuit to be tested.
It should be noted that, in the embodiment of the present invention, "the previous second I/O circuit to be tested" and "the next second I/O circuit to be tested" are defined before and after each other in the sequential directions of the first second circuit group to the L-th circuit group to be tested.
The delay test method provided by the embodiment of the invention is described in more detail below with reference to the circuit structure of a specific semiconductor chip. Defining the plurality of I/O circuits as a first I/O circuit to an N-th I/O circuit, N being an integer greater than or equal to 2; the selection circuit includes: the first to the nth first multiplexers and the first to the mth second multiplexers, when N is even, then M is N/2; n is in the case of an odd number of the number, M is (N+1)/2; the output end of the kth first multiplexer is electrically connected with the input port of the kth I/O circuit, and k is a positive integer less than or equal to N; the first input end of the ith first multiplexer is electrically connected with the output end of the (i+1)/2 second multiplexers, the second input end of the ith first multiplexer is connected with the functional signal, and i is an odd number less than or equal to N; the first input end of the j-th first multiplexer is electrically connected with the output end of the j-1-th I/O circuit, the second input end of the j-th first multiplexer is connected with the functional signal, the output end of the j-th I/O circuit is electrically connected with the second input end of the j/2-th second multiplexer and the first input end of the j/2+1-th second multiplexer, the first input end of the first second multiplexer is electrically connected with the tester, and j is an even number less than or equal to N.
The delay test method comprises the following steps: selecting a second I/O circuit to be tested from the first I/O circuit to the Nth I/O circuit; selecting an initial second I/O circuit to be tested and a second I/O circuit to be tested at the tail end from the second I/O circuit to be tested along the sequence from the first I/O circuit to the Nth I/O circuit, and dividing the rest of the second I/O circuits to be tested into a first second circuit group to an L second circuit group to be tested in sequence, wherein any one of the first second circuit group to the L second circuit group to be tested comprises two second I/O circuits to be tested; wherein, among the first to nth I/O circuits, a previous one of the first to second I/O circuits to be tested is adjacent to the initial second I/O circuit to be tested, a next one of the L second I/O circuits to be tested is adjacent to the terminal second I/O circuit to be tested, and a next one of the t second I/O circuits to be tested is adjacent to the previous one of the t+1th second I/O circuits to be tested; electrically connecting the two bidirectional ports of the two second I/O circuits to be tested in the second circuit group to be tested; powering up the semiconductor chip; controlling the first multiplexer and/or the second multiplexer which are correspondingly and electrically connected with the second I/O circuit to be tested to gate the first input end; and inputting a delay test signal to the bidirectional port of the initial second I/O circuit to be tested, and receiving a feedback delay test signal from the bidirectional port of the second I/O circuit to be tested at the tail end.
It should be noted that, when the initial second I/O circuit to be tested is an odd I/O circuit, only the first multiplexer corresponding to the second I/O circuit to be tested needs to be controlled to gate the first input terminal; or when the initial second I/O circuit to be tested is an even I/O circuit, the first input end is required to be gated by both the first multiplexer and the second multiplexer corresponding to the second I/O circuit to be tested.
Referring specifically to fig. 7, a schematic signal transmission diagram of another semiconductor chip provided by the embodiment of the present invention is taken as an example, where N is 6 and six I/O circuits are all second I/O circuits to be tested, and a signal trend (such as a signal trend of a dashed arrow in fig. 7) in a delay test process provided by the embodiment of the present invention is described in detail; wherein, in the order from the first I/O circuit 101 to the sixth I/O circuit 106, the first I/O circuit 101 is an initial second I/O circuit to be tested, the second I/O circuit 102 and the third I/O circuit 103 are formed into a first second circuit group to be tested, the fourth I/O circuit 104 and the fifth I/O circuit 105 are formed into a second circuit group to be tested, and the sixth I/O circuit 106 is a terminal second I/O circuit to be tested; and includes first to sixth first multiplexers 211 to 216 and first to third second multiplexers 221 to 223.
Continuing to power on the semiconductor chip during the delay test as shown in fig. 7, the first input terminal is gated by the first multiplexer corresponding to the second I/O circuit under test; the test device transmits the delay test signal to the bidirectional port PAD of the first I/O circuit 101, then the signal is transmitted from the output port C of the first I/O circuit 101 to the first input terminal of the second first multiplexer 212, the first multiplexer 211 outputs the signal to the input port I of the second I/O circuit 102, the bidirectional port PAD of the second I/O circuit 102 outputs the signal to the bidirectional port PAD of the third I/O circuit 103, then the output port C of the third I/O circuit 103 outputs the signal to the first input terminal of the fourth first multiplexer 214, and then the like, until the signal is transmitted to the first input terminal of the sixth first multiplexer 216, the sixth first multiplexer 216 outputs the signal to the input port I of the sixth I/O circuit 106, and the sixth I/O circuit 106 outputs the feedback delay test signal from the bidirectional port PAD thereof, thereby completing the test of the semiconductor chip by judging the delay test signal and the feedback delay test signal.
Further, the delay test provided in this embodiment of the present invention may further perform a test in a direction from a second I/O circuit to be tested at a terminal to an initial second I/O circuit to be tested, that is, in the first I/O circuit to an nth I/O circuit, the second I/O circuit to be tested at the terminal is an even I/O circuit, one of two second I/O circuits to be tested included in any one of the second circuit sets to be tested is an even I/O circuit, and the other is an odd I/O circuit, where after receiving a feedback delay test signal from a bidirectional port of the second I/O circuit to be tested at the terminal, the delay test method further includes: controlling the first multiplexer corresponding to the second I/O circuit to gate a first input end, and controlling the second multiplexer corresponding to the second I/O circuit to gate a second input end; and inputting a delay test signal to the bidirectional port of the second I/O circuit to be tested at the tail end, and receiving a feedback delay test signal from the bidirectional port of the initial second I/O circuit to be tested. As shown in particular in figure 8 of the drawings, a signal transmission schematic diagram of a semiconductor chip according to an embodiment of the present invention is provided, the circuit structure of the semiconductor chip shown in fig. 8 is the same as that of fig. 7, so redundant description is omitted; the difference is that the signal trend during the delay test shown in fig. 8 (e.g., the signal trend of the dashed arrow in fig. 8) is opposite to the trend shown in fig. 7.
Continuing to power on the semiconductor chip during the delay test as shown in fig. 8, the first input terminal is gated by the first multiplexer corresponding to the second I/O circuit to be tested, and the second input terminal is gated by the second multiplexer corresponding to the second I/O circuit to be tested; the test device transmits the delay test signal to the bidirectional port PAD of the sixth I/O circuit 106, then the signal is transmitted from the output port C of the sixth I/O circuit 106 to the second input terminal of the third second multiplexer 223, the third second multiplexer 223 outputs the signal to the first input terminal of the fifth first multiplexer 215, the fifth first multiplexer 215 outputs the signal to the input port I of the fifth I/O circuit 105, the bidirectional port PAD of the fifth I/O circuit 105 outputs the signal to the bidirectional port PAD of the fourth I/O circuit 104, then the output port C of the fourth I/O circuit 104 outputs the signal to the second input terminal of the second multiplexer 222, and so on, until the first I/O circuit 101 outputs the feedback delay test signal from the bidirectional port PAD thereof, and further the bidirectional delay test of the semiconductor chip is completed by judging the delay test signal and the feedback delay test signal.
Correspondingly, the embodiment of the invention also provides a method for integrally testing the semiconductor chip. As shown in fig. 9, a flowchart of an overall testing method of a semiconductor chip according to an embodiment of the present invention is shown, where the overall testing method includes:
s31, performing delay test on the semiconductor chip.
And carrying out delay test on the semiconductor chip according to the delay test method provided by any one of the embodiments.
S32, HTOL testing is conducted on the semiconductor chip.
And carrying out HTOL testing on the semiconductor chip according to the HTOL testing method provided by any one of the embodiments.
S33, performing delay test on the semiconductor chip again.
And after HTOL testing, testing the semiconductor chip again according to the delay test method provided by any one of the embodiments.
It can be appreciated that in the overall test method provided by the embodiment of the invention, delay tests are performed on the semiconductor chip before and after HTOL tests are performed on the semiconductor chip, so that delay test data before and after HTOL tests can be compared, the delay test effect can be further improved, and the situation that the HTOL test structure is inaccurate due to inaccurate delay tests can be avoided.
The embodiment of the invention provides a semiconductor chip and an HTOL (full-automatic test) method, a delay method and an integral test method thereof, wherein the semiconductor chip comprises a selection circuit and a tester, and in the test process of the semiconductor chip, I/O circuits to be tested can be communicated through the selection circuit, so that signals can be transmitted in all the I/O circuits to be tested, and the HTOL test, the delay test and the integral test are completed. In addition, in the HTOL test process of the semiconductor chip, the tester can provide test signals with target frequency, and the test signals can be flexibly matched with the I/O circuit working frequency of the semiconductor chip, so that the HTOL test requirement is met. In addition, the test of the semiconductor chip provided by the embodiment of the invention can select all I/O circuits as I/O circuits to be tested to achieve the purpose of testing all I/O circuits at one time, or select part of I/O circuits as I/O circuits to be tested to achieve the purpose of testing the I/O circuits in parts, so that the semiconductor chip is better tested, and the test effect is improved.
In the description of the present invention, it should be understood that the directions or positional relationships as indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., are based on the directions or positional relationships shown in the drawings are merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the invention.
Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, terms such as "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly attached, detachably attached, or integrally formed; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the present disclosure, the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (10)

1. A semiconductor chip, comprising:
The input ports of the I/O circuits are connected with signals, and the bidirectional ports of the I/O circuits output signals; when the bidirectional port of the I/O circuit is connected with a signal, the output port of the I/O circuit outputs the signal;
the output side of the selection circuit is electrically connected with the I/O circuit, the input side of the selection circuit is connected with a functional signal and is electrically connected with a tester, and the tester is used for outputting a test signal of target frequency;
the selection circuit is used for selectively controlling at least part of the I/O circuits, and the output port of the former I/O circuit is communicated with the input port of the latter I/O circuit; and the selection circuit is also used for selecting the test signal or the functional signal to be transmitted to the I/O circuit.
2. The semiconductor chip of claim 1, wherein the plurality of I/O circuits is defined as a first I/O circuit to an nth I/O circuit, N being an integer greater than or equal to 2;
the selection circuit includes: the first to the nth first multiplexers and the first to the mth second multiplexers, when N is even, then M is N/2; and M is (N+1)/2 when N is an odd number;
The output end of the kth first multiplexer is electrically connected with the input port of the kth I/O circuit, and k is a positive integer less than or equal to N;
the first input end of the ith first multiplexer is electrically connected with the output end of the (i+1)/2 second multiplexers, the second input end of the ith first multiplexer is connected with the functional signal, and i is an odd number less than or equal to N;
the first input end of the j-th first multiplexer is electrically connected with the output end of the j-1-th I/O circuit, the second input end of the j-th first multiplexer is connected with the functional signal, the output end of the j-th I/O circuit is electrically connected with the second input end of the j/2-th second multiplexer and the first input end of the j/2+1-th second multiplexer, the first input end of the first second multiplexer is electrically connected with the tester, and j is an even number less than or equal to N.
3. The semiconductor chip of claim 1, wherein a target frequency of the test signal is fixed and the target frequency is the same as an operating frequency of the I/O circuit;
alternatively, the target frequency of the test signal is adjustable, and the adjustable range of the target frequency includes the operating frequency of the I/O circuit.
4. A method of HTOL testing of a semiconductor chip, for testing a semiconductor chip according to any one of claims 1-3, the method comprising:
selecting a first I/O circuit to be tested from the plurality of I/O circuits;
sequentially dividing the first I/O circuit to be tested into a first circuit group to a first H circuit group to be tested, wherein any one of the first circuit group to the first H-1 circuit group to be tested comprises two first I/O circuits to be tested, the first H circuit group to be tested comprises one or two first I/O circuits to be tested, and H is an integer greater than 1;
electrically connecting the two bidirectional ports of the two first I/O circuits to be tested in the first circuit group to be tested;
powering up the semiconductor chip under HTOL test conditions;
according to the sequence of dividing the first to-be-detected I/O circuit into first to-be-detected circuit groups, the selection circuit communicates an output port of the last first to-be-detected I/O circuit in the g first to-be-detected circuit group with an input port of the last first to-be-detected I/O circuit in the g+1th first to-be-detected circuit group, and g is a positive integer smaller than H;
The selection circuit selects the test signal to transmit to the first I/O circuit to be tested.
5. The HTOL testing method of the semiconductor chip according to claim 4, wherein the plurality of I/O circuits are defined as a first I/O circuit to an nth I/O circuit, N being an integer greater than or equal to 2;
the selection circuit includes: the first to the nth first multiplexers and the first to the mth second multiplexers, when N is even, then M is N/2; and M is (N+1)/2 when N is an odd number;
the output end of the kth first multiplexer is electrically connected with the input port of the kth I/O circuit, and k is a positive integer less than or equal to N;
the first input end of the ith first multiplexer is electrically connected with the output end of the (i+1)/2 second multiplexers, the second input end of the ith first multiplexer is connected with the functional signal, and i is an odd number less than or equal to N;
the first input end of the j-th first multiplexer is electrically connected with the output port of the j-1-th I/O circuit, the second input end of the j-th first multiplexer is connected with the functional signal, the output port of the j-th I/O circuit is electrically connected with the second input end of the j/2-th second multiplexer and the first input end of the j/2+1-th second multiplexer, the first input end of the first second multiplexer is electrically connected with the tester, and j is an even number less than or equal to N;
The HTOL testing method comprises the following steps:
selecting a first I/O circuit to be tested from the first I/O circuit to the Nth I/O circuit, wherein the first I/O circuit to be tested comprises the first I/O circuit;
dividing the first I/O circuit to be tested into a first circuit group to a H first circuit group to be tested according to the sequence from the first I/O circuit to the N I/O circuit, wherein any one of the first circuit group to be tested to the H-1 first circuit group to be tested comprises two first I/O circuits to be tested, and the H first circuit group to be tested comprises one or two first I/O circuits to be tested; among the first to nth I/O circuits, the latter one of the g first to be tested circuit groups is adjacent to the former one of the g+1th first to be tested circuit groups;
electrically connecting the two bidirectional ports of the two first I/O circuits to be tested in the first circuit group to be tested;
powering up the semiconductor chip under HTOL test conditions;
and controlling the first multiplexer and the second multiplexer which are correspondingly and electrically connected with the first I/O circuit to be tested to gate a first input end, and simultaneously, transmitting the test signals to the input port of the first I/O circuit by the first multiplexer and the first second multiplexer.
6. A delay test method for a semiconductor chip, characterized in that it is used for testing the semiconductor chip according to any one of claims 1 to 3, and comprises:
selecting a second I/O circuit to be tested from the plurality of I/O circuits;
selecting an initial second I/O circuit to be tested and a second I/O circuit to be tested at the tail end from the second I/O circuit to be tested, sequentially dividing the rest of the second I/O circuits to be tested into a first second circuit group to an L second circuit group to be tested along the direction from the initial second I/O circuit to the second I/O circuit to be tested at the tail end, wherein any one of the first second circuit group to the L second circuit group to be tested comprises two second I/O circuits to be tested, and L is an integer greater than 1;
electrically connecting the two bidirectional ports of the two second I/O circuits to be tested in the second circuit group to be tested;
powering up the semiconductor chip;
according to the sequence of dividing the second to-be-detected I/O circuit groups by the second to-be-detected I/O circuit, the selection circuit is used for communicating an output port of the initial second to-be-detected I/O circuit with an input port of a previous second to-be-detected I/O circuit in a first second to-be-detected circuit group, communicating an output port of a next second to-be-detected I/O circuit in a t second to-be-detected circuit group with an input port of a previous second to-be-detected I/O circuit in a t+1th second to-be-detected circuit group, and communicating an output port of a next second to-be-detected I/O circuit in an L second to-be-detected circuit group with an input port of a second to-be-detected I/O circuit at the tail end, wherein t is a positive integer smaller than L;
And inputting a delay test signal to the bidirectional port of the initial second I/O circuit to be tested, and receiving a feedback delay test signal from the bidirectional port of the second I/O circuit to be tested at the tail end.
7. The method of claim 6, further comprising, after receiving a feedback delay test signal from a bi-directional port of the second I/O circuit under test at the end:
according to the reverse sequence of the second to-be-detected I/O circuit dividing second to-be-detected circuit groups, the selection circuit is used for communicating an output port of the second to-be-detected I/O circuit at the tail end with an input port of a next second to-be-detected I/O circuit in an L-th second to-be-detected circuit group, communicating an output port of a previous second to-be-detected I/O circuit in a t+1th second to-be-detected circuit group with an input port of a next second to-be-detected I/O circuit in a t-th second to-be-detected circuit group, and communicating an output port of a previous second to-be-detected I/O circuit in a first second to-be-detected circuit group with an input port of the initial second to-be-detected I/O circuit;
and inputting a delay test signal to the bidirectional port of the second I/O circuit to be tested at the tail end, and receiving a feedback delay test signal from the bidirectional port of the initial second I/O circuit to be tested.
8. The method according to claim 6, wherein the plurality of I/O circuits are defined as a first I/O circuit to an nth I/O circuit, N being an integer greater than or equal to 2;
the selection circuit includes: the first to the nth first multiplexers and the first to the mth second multiplexers, when N is even, then M is N/2; and M is (N+1)/2 when N is an odd number;
the output end of the kth first multiplexer is electrically connected with the input port of the kth I/O circuit, and k is a positive integer less than or equal to N;
the first input end of the ith first multiplexer is electrically connected with the output end of the (i+1)/2 second multiplexers, the second input end of the ith first multiplexer is connected with the functional signal, and i is an odd number less than or equal to N;
the first input end of the j-th first multiplexer is electrically connected with the output port of the j-1-th I/O circuit, the second input end of the j-th first multiplexer is connected with the functional signal, the output port of the j-th I/O circuit is electrically connected with the second input end of the j/2-th second multiplexer and the first input end of the j/2+1-th second multiplexer, the first input end of the first second multiplexer is electrically connected with the tester, and j is an even number less than or equal to N;
The delay test method comprises the following steps:
selecting a second I/O circuit to be tested from the first I/O circuit to the Nth I/O circuit;
selecting an initial second I/O circuit to be tested and a second I/O circuit to be tested at the tail end from the second I/O circuit to be tested along the sequence from the first I/O circuit to the Nth I/O circuit, and dividing the rest of the second I/O circuits to be tested into a first second circuit group to an L second circuit group to be tested in sequence, wherein any one of the first second circuit group to the L second circuit group to be tested comprises two second I/O circuits to be tested; wherein, among the first to nth I/O circuits, a previous one of the first to second I/O circuits to be tested is adjacent to the initial second I/O circuit to be tested, a next one of the L second I/O circuits to be tested is adjacent to the terminal second I/O circuit to be tested, and a next one of the t second I/O circuits to be tested is adjacent to the previous one of the t+1th second I/O circuits to be tested;
electrically connecting the two bidirectional ports of the two second I/O circuits to be tested in the second circuit group to be tested;
Powering up the semiconductor chip;
controlling the first multiplexer and/or the second multiplexer which are/is correspondingly and electrically connected with the second I/O circuit to be tested to gate a first input end;
and inputting a delay test signal to the bidirectional port of the initial second I/O circuit to be tested, and receiving a feedback delay test signal from the bidirectional port of the second I/O circuit to be tested at the tail end.
9. The method according to claim 8, wherein among the first to nth I/O circuits, the second I/O circuit to be tested at the end is an even I/O circuit, and one of the two second I/O circuits to be tested included in any one of the second circuit group to be tested is an even I/O circuit and the other is an odd I/O circuit, wherein after receiving the feedback delay test signal from the bidirectional port of the second I/O circuit to be tested at the end, the method further comprises:
controlling the first multiplexer corresponding to the second I/O circuit to gate a first input end, and controlling the second multiplexer corresponding to the second I/O circuit to gate a second input end;
And inputting a delay test signal to the bidirectional port of the second I/O circuit to be tested at the tail end, and receiving a feedback delay test signal from the bidirectional port of the initial second I/O circuit to be tested.
10. An overall test method of a semiconductor chip, the overall test method comprising:
performing delay test on the semiconductor chip according to the delay test method of any one of claims 6 to 9;
performing HTOL testing on the semiconductor chip according to the HTOL testing method of claim 4 or 5;
after the HTOL test has been performed, the semiconductor chip is tested again according to the time delay test method of any one of claims 6-9.
CN202310703192.1A 2023-06-14 2023-06-14 Semiconductor chip and HTOL, delay and overall test method thereof Active CN116454069B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310703192.1A CN116454069B (en) 2023-06-14 2023-06-14 Semiconductor chip and HTOL, delay and overall test method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310703192.1A CN116454069B (en) 2023-06-14 2023-06-14 Semiconductor chip and HTOL, delay and overall test method thereof

Publications (2)

Publication Number Publication Date
CN116454069A true CN116454069A (en) 2023-07-18
CN116454069B CN116454069B (en) 2023-09-15

Family

ID=87124064

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310703192.1A Active CN116454069B (en) 2023-06-14 2023-06-14 Semiconductor chip and HTOL, delay and overall test method thereof

Country Status (1)

Country Link
CN (1) CN116454069B (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000046909A (en) * 1998-07-23 2000-02-18 Seiko Epson Corp Semiconductor integrated-circuit device and its test method
JP2002373086A (en) * 2001-06-13 2002-12-26 Mitsubishi Electric Corp Semiconductor integrated circuit
US20040267480A1 (en) * 2003-06-30 2004-12-30 Day Daniel A Selective control of test-access ports in integrated circuits
US20090021279A1 (en) * 2007-07-18 2009-01-22 Matsushita Electric Industrial Co., Ltd. Semiconductor testing circuit and semiconductor testing method
KR20200029082A (en) * 2018-09-07 2020-03-18 삼성전자주식회사 System and method for measuring the working speed of a semiconductor chip and the semiconductor chip applying the method
CN113721131A (en) * 2021-09-02 2021-11-30 展讯通信（上海）有限公司 Input test circuit and chip
CN115267481A (en) * 2022-01-11 2022-11-01 天芯互联科技有限公司 Chip test circuit and chip test device
CN115312501A (en) * 2021-05-07 2022-11-08 华邦电子股份有限公司 Parallel testing method for semiconductor wafer and multiple chips
WO2023019545A1 (en) * 2021-08-20 2023-02-23 华为技术有限公司 Chip and device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000046909A (en) * 1998-07-23 2000-02-18 Seiko Epson Corp Semiconductor integrated-circuit device and its test method
JP2002373086A (en) * 2001-06-13 2002-12-26 Mitsubishi Electric Corp Semiconductor integrated circuit
US20040267480A1 (en) * 2003-06-30 2004-12-30 Day Daniel A Selective control of test-access ports in integrated circuits
US20090021279A1 (en) * 2007-07-18 2009-01-22 Matsushita Electric Industrial Co., Ltd. Semiconductor testing circuit and semiconductor testing method
KR20200029082A (en) * 2018-09-07 2020-03-18 삼성전자주식회사 System and method for measuring the working speed of a semiconductor chip and the semiconductor chip applying the method
CN115312501A (en) * 2021-05-07 2022-11-08 华邦电子股份有限公司 Parallel testing method for semiconductor wafer and multiple chips
WO2023019545A1 (en) * 2021-08-20 2023-02-23 华为技术有限公司 Chip and device
CN113721131A (en) * 2021-09-02 2021-11-30 展讯通信（上海）有限公司 Input test circuit and chip
CN115267481A (en) * 2022-01-11 2022-11-01 天芯互联科技有限公司 Chip test circuit and chip test device

Also Published As

Publication number Publication date
CN116454069B (en) 2023-09-15

Similar Documents

Publication Publication Date Title
US7900105B2 (en) Dynamically reconfigurable shared scan-in test architecture
US8856601B2 (en) Scan compression architecture with bypassable scan chains for low test mode power
WO1992005488A1 (en) Fault insertion
US9568549B2 (en) Managing redundancy repair using boundary scans
US8677201B2 (en) Semiconductor integrated circuit and method of retrieving signal to semiconductor integrated circuit
CN100545668C (en) The jtag test architecture that is used for the encapsulation of multicore sheet
JP2013526010A (en) Integrated circuit die test apparatus and method
US7293211B2 (en) Semiconductor integrated circuit
US7137053B2 (en) Bandwidth matching for scan architectures in an integrated circuit
CN116454069B (en) Semiconductor chip and HTOL, delay and overall test method thereof
CN111766505A (en) Scanning test device for integrated circuit
US8169230B2 (en) Semiconductor device and method of testing the same
US6862705B1 (en) System and method for testing high pin count electronic devices using a test board with test channels
WO2002029568A2 (en) A test access port (tap) controller system and method to debug internal intermediate scan test faults
US9304166B2 (en) Method and system for wafer level testing of semiconductor chips
CN114518524A (en) Chip test system and control method of chip test system
US6918073B2 (en) Differential self-test of input/output circuits
US5023875A (en) Interlaced scan fault detection system
KR20100009053A (en) Embedded flash memory test circuit
CN116741751A (en) Integrated circuit unit, integrated circuit and die testing method
US11073558B2 (en) Circuit having multiple scan modes for testing
US8935583B2 (en) Removing scan channel limitation on semiconductor devices
US7146549B2 (en) Scan-path flip-flop circuit for integrated circuit memory
US7733113B2 (en) Semiconductor test device
EP3029684B1 (en) Test circuit and method for controlling test circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant