CN114518524A - Chip test system and control method of chip test system - Google Patents
Chip test system and control method of chip test system Download PDFInfo
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- CN114518524A CN114518524A CN202210102731.1A CN202210102731A CN114518524A CN 114518524 A CN114518524 A CN 114518524A CN 202210102731 A CN202210102731 A CN 202210102731A CN 114518524 A CN114518524 A CN 114518524A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
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Abstract
The application provides a chip test system and a control method of the chip test system, wherein the chip test system comprises: the device comprises a chip and a tester, wherein the chip comprises a controller, pins, a data selector and a test register; the controller is used for receiving a mode switching instruction sent by the testing machine and controlling the data selector to be switched to a testing mode according to the mode switching instruction; the data selector is used for controlling the conduction of a first input end of the data selector and an output end of the data selector when the data selector is switched to a test mode; the controller is also used for receiving the test instruction sent by the tester and controlling the test register to output a test value according to the test instruction; and the testing machine is used for collecting the voltage output by the second end of the pin and generating a testing result of the first end of the pin according to the voltage and the testing instruction. Therefore, the pins of the chip can be tested, test logic can be introduced in the chip design stage, and the test speed and the test accuracy are improved.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a chip test system and a control method of the chip test system.
Background
The pins of the chip are devices connected with the chip and the outside and used for inputting and outputting data, wherein the input and the output are input low level, input high level, output low level and output high level. The judgment of high and low levels has certain standards, and the low level below a specific level value (for example: 0.3V) can be considered as the low level; above a certain level value (e.g., 1.5V), it can be considered a high level.
Because the number of pins of the chip is large, each pin is used for communication between the inside and the outside of the chip, and the reliability of the pins is very important. The related test technology cannot be unified with the functional design flow, and the test process is long in time consumption and not intuitive.
Disclosure of Invention
The embodiment of the application provides a chip test system and a control method of the chip test system, which can test pins of a chip, can introduce test logic in a chip design stage, and improve test speed and test accuracy.
The embodiment of the first aspect of the application provides a chip testing system, which comprises a chip and a testing machine, wherein the chip is connected with the testing machine, the chip comprises a controller, a pin, a data selector and a testing register, the controller is respectively connected with a control end of the data selector and a control end of the testing register, a first input end of the data selector is connected with an output end of the testing register, an output end of the data selector is connected with a first end of the pin, and a second end of the pin is connected with the testing machine; the controller is used for receiving a mode switching instruction sent by the testing machine and controlling the data selector to switch to a testing mode according to the mode switching instruction; the data selector is used for controlling the conduction of a first input end of the data selector and an output end of the data selector when the data selector is switched to a test mode; the controller is also used for receiving a test instruction sent by the tester and controlling the test register to output a test value according to the test instruction; the tester is used for collecting the voltage output by the second end of the pin and generating a test result of the first end of the pin according to the voltage and the test instruction.
The chip testing system of the embodiment of the application generates the testing result according to the output voltage and the testing value of the chip pin through the testing machine, so that the pin of the chip can be tested by verifying the output voltage of the chip pin, the testing logic can be introduced in the chip design stage, and the testing speed and the testing accuracy are improved.
In addition, the chip testing system according to the above embodiment of the present application may further have the following additional technical features:
in an embodiment of the application, the test instruction includes the test value, and the tester is specifically configured to: and collecting the voltage output by the second end of the pin, and generating the test result according to the voltage and the test value, wherein the test value is 0 or 1.
In an embodiment of the present application, the chip further includes a functional path, the functional path is connected to the second input terminal of the data selector, and the data selector is further configured to: and when the data selector is switched to the test mode, controlling the second input end of the data selector to be closed.
In an embodiment of the application, the data selector is further configured to: and when the chip is powered on, controlling the second input end of the data selector and the output end of the data selector to be conducted, and controlling the first input end of the data selector to be closed.
The embodiment of the second aspect of the present application provides another chip testing system, including a chip and a tester, where the chip is connected to the tester, where the chip includes a controller, a pin and a read-only register, where the controller is connected to a control end of the read-only register, a first end of the pin is connected to an input end of the read-only register, and a second end of the pin is connected to the tester; the tester is used for providing voltage for the second end of the pin; the read-only register is used for reading a test value corresponding to the voltage output by the first end of the pin and sending the test value to the controller; the controller is used for forwarding the test value to the tester; the tester is further configured to generate a test result of the second end of the pin according to the voltage and the test value.
According to the chip testing system, the testing result is generated through the testing machine according to the input voltage and the testing value of the pin, so that the pin of the chip can be tested through verifying the input voltage of the pin of the chip, the testing logic can be introduced in the chip design stage, and the testing speed and the testing accuracy are improved.
In addition, the chip testing system according to the above embodiment of the present application may further have the following additional technical features:
in one embodiment of the present application, the test value is 0 or 1.
An embodiment of a third aspect of the present application provides a method for controlling a chip testing system, including: receiving a mode switching instruction sent by the testing machine, and controlling the data selector to switch to a testing mode according to the mode switching instruction; when the data selector is switched to a test mode, controlling the first input end of the data selector and the output end of the data selector to be conducted; receiving a test instruction sent by the tester, and controlling the test register to output a test value according to the test instruction; and acquiring the voltage output by the second end of the pin, and generating a test result of the first end of the pin according to the voltage and the test instruction.
The control method of the chip test system in the embodiment of the application receives a mode switching instruction sent by a test machine, controls the data selector to be switched to the test mode according to the mode switching instruction, controls the first input end of the data selector to be conducted with the output end of the data selector when the data selector is switched to the test mode, receives the test instruction sent by the test machine, controls the test register to output a test value according to the test instruction, collects the voltage output by the second end of the pin, and generates a test result of the first end of the pin according to the voltage and the test instruction, so that the pin of the chip can be tested by verifying the output voltage of the pin of the chip, test logic can be introduced in the chip design stage, and the test speed and the test accuracy are improved.
In addition, the control method of the chip testing system according to the above embodiment of the present application may further have the following additional technical features:
in an embodiment of the application, the acquiring the voltage output by the second end of the pin and generating the test result of the first end of the pin according to the voltage and the test instruction includes: and collecting the voltage output by the second end of the pin, and generating the test result according to the voltage and the test value, wherein the test value is 0 or 1.
An embodiment of a fourth aspect of the present application provides a method for controlling a chip testing system, including: providing a voltage to a second end of the pin; reading a test value corresponding to the voltage output by the first end of the pin, and sending the test value to the controller; forwarding the test value to the tester; and generating a test result of the second end of the pin according to the voltage and the test value.
According to the control method of the chip test system, the voltage is provided for the second end of the pin, the test value corresponding to the voltage output by the first end of the pin is read, the test value is sent to the controller, the test value is forwarded to the test machine, and the test result of the second end of the pin is generated according to the voltage and the test value, so that the pin of the chip can be tested by verifying the input voltage of the pin of the chip, test logic can be introduced in the chip design stage, and the test speed and the test accuracy are improved.
In addition, the control method of the chip testing system according to the above embodiment of the present application may further have the following additional technical features:
in one embodiment of the present application, the test value is 0 or 1.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a chip test system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a chip test system according to another embodiment of the present application;
FIG. 3 is a schematic diagram of a chip test system according to another embodiment of the present application;
FIG. 4 is a flow chart illustrating a chip testing method according to an embodiment of the present application; and
fig. 5 is a flowchart illustrating a chip testing method according to another embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
A chip test system and a control method of the chip test system of the embodiments of the present application are described below with reference to the drawings.
Fig. 1 is a schematic structural diagram of a chip testing system according to an embodiment of the present application.
As shown in fig. 1, a chip test system 100 according to an embodiment of the present invention may include: chip 110 is connected to tester 120, and chip 110 is connected to tester 120. The chip 110 may include a controller 111, a pin 112, a data selector 113, and a test register 114, where the controller 111 is connected to a control terminal of the data selector 113 and a control terminal of the test register 114, respectively, a first input terminal of the data selector 113 is connected to an output terminal of the test register 114, an output terminal of the data selector 113 is connected to a first terminal of the pin 112, and a second terminal of the pin 112 is connected to the tester 120.
The controller 111 is configured to receive a mode switching instruction sent by the tester 120, and control the data selector 113 to switch to the test mode according to the mode switching instruction. The mode of the data selector 113 may include a working mode and a Test mode, and the tester 120 may be an Automatic Test Equipment (ATE) for integrated circuits.
In the embodiment of the present application, the testing machine 120 may send a mode switching instruction to the controller through the relevant protocol.
Specifically, when the chip testing system 100 tests the chip 110, the testing machine 120 may send a mode switching instruction to the controller 111, and after the controller 111 receives the mode switching instruction, the data selector 113 may be controlled to switch the current mode to the testing mode.
And a data selector 113 for controlling the first input terminal of the data selector 113 and the output terminal of the data selector 113 to be conducted when the data selector 113 switches to the test mode.
Specifically, when the data selector 113 is not in the test mode, the first input terminal of the data selector 113 is in an off state, and when the data selector 113 switches to the test mode, the first input terminal of the data selector 113 and the output terminal of the data selector 113 are controlled to be turned on.
The controller 111 is further configured to receive a test instruction sent by the tester 120, and control the test register 114 to output a test value according to the test instruction.
In the embodiment of the present application, the testing machine 120 may send the test instruction to the controller 111 through the relevant protocol.
Specifically, after the data selector 113 switches to the test mode, the tester 120 may send a test instruction to the controller 111 through the relevant protocol, and the controller 111 controls the test register 114 to output a test value according to the test instruction after receiving the test instruction.
The tester 120 is configured to collect a voltage output by the second end of the pin 112, and generate a test result of the first end of the pin 112 according to the voltage and the test instruction.
To illustrate the above embodiment, in an embodiment of the present application, the test instruction may include a test value, and the testing machine 120 is specifically configured to collect a voltage output from the second terminal of the pin 112 and generate a test result according to the voltage and the test value, where the test value is 0 or 1.
Among them, the voltage may include a high voltage, which may be a voltage higher than a specific voltage value (e.g., 1.5V), and a low voltage, which may be a voltage lower than a specific voltage value (e.g., 0.3V).
In the embodiment of the present application, when the chip testing system 100 tests the chip 110, a test result may be generated according to the voltage output by the second end of the pin 112 and the test value output by the test register 114, which are collected by the testing machine 120.
Specifically, if the test value output by the test register 114 is 0, the voltage output by the second terminal of the pin 112 collected by the tester 120 is low voltage, and the test value output by the test register 114 is 1, the voltage output by the second terminal of the pin 112 collected by the tester 120 is high voltage, which may indicate that the pin 112 may normally operate, but in this case, it may indicate that the pin 112 may not normally operate.
The chip testing system of the embodiment of the application generates the testing result according to the output voltage and the testing value of the chip pin through the testing machine, so that the pin of the chip can be tested by verifying the output voltage of the chip pin, the testing logic can be introduced in the chip design stage, and the testing speed and the testing accuracy are improved.
In an embodiment of the present application, as shown in fig. 2, the chip 110 may further include a functional path 115, the functional path 115 is connected to a second input terminal of the data selector 113, and the data selector 113 is further configured to control the second input terminal of the data selector 113 to be turned off when the data selector 113 is switched to the test mode. The functional path 115 may be a functional circuit inside the chip 110, and is used for transmitting a functional signal when the chip 110 normally operates.
In the embodiment of the present application, when the data selector 113 is not in the test mode, the second input terminal of the data selector 113 is turned on, the first input terminal is turned off, and the data selector 113 can receive and output the signal transmitted by the functional path 115, and does not receive the signal transmitted by the test register 114; when the data selector 113 switches to the test mode, the controller 111 may control the second input terminal of the data selector 113 to be turned off, not to receive the signal transmitted by the functional path 115, and may control the first input terminal of the data selector 113 to be turned on, so as to receive and output the signal (i.e., the test value) transmitted by the test register 114, thereby testing the chip 110.
In an embodiment of the present application, the data selector 113 is further configured to control the second input terminal of the data selector 113 and the output terminal of the data selector 113 to be turned on, and control the first input terminal of the data selector 113 to be turned off when the chip 110 is powered on.
Specifically, when the chip 110 is powered on, the chip 110 may be initialized, and the controller 111 controls the second input terminal of the data selector 113 and the output terminal of the data selector 113 to be turned on, and controls the first input terminal of the data selector 113 to be turned off, so that the controller exits from the test mode and restores to the initial state.
Fig. 3 is a schematic structural diagram of a chip test system according to another embodiment of the present application.
As shown in fig. 3, a chip test system 300 according to an embodiment of the present disclosure may include a chip 310 and a tester 320, where the chip 310 is connected to the tester 320. The chip 310 may include a controller 311, a pin 312, and a read only register 313, where the controller 311 is connected to a control terminal of the read only register 313, a first terminal of the pin 312 is connected to an input terminal of the read only register 313, and a second terminal of the pin 312 is connected to the tester 320. Tester 320 may be ATE, among others.
The tester 320 is used for providing a voltage to the second end of the pin 312.
Among them, the voltage may include a high voltage, which may be a voltage higher than a specific voltage value (e.g., 1.5V), and a low voltage, which may be a voltage lower than a specific voltage value (e.g., 0.3V).
Specifically, when the chip testing system 300 tests the chip 310, the tester 320 may provide a high voltage or a low voltage to the second end of the pin 312.
The read-only register 313 is configured to read a test value corresponding to the voltage output by the first end of the pin 312, and send the test value to the controller 311. Wherein the test value may be 0 or 1.
In the embodiment of the present application, the test value corresponding to the high voltage is 1, the test value corresponding to the low voltage is 0, when the voltage output by the first end of the pin 312 is the high voltage, the test value read by the rom 313 is 1, and when the voltage output by the first end of the pin 312 is the low voltage, the test value read by the rom 313 is 0.
Specifically, after the tester 320 provides the high voltage or the low voltage to the second end of the pin 312, the read only register 313 may read a test value corresponding to the voltage output from the first end of the pin 312 and send the test value to the controller 311.
Specifically, controller 311, upon receiving the test value sent by read only register 313, may forward the test value to tester 320.
The tester 320 is further configured to generate a test result of the second end of the pin 312 according to the voltage and the test value.
In this embodiment, after the tester 320 receives the test value forwarded by the controller 111, a test result of the second end of the pin 312 may be generated according to the test value and the voltage provided by the tester 320 to the second end of the pin 312.
Specifically, if the voltage provided by the tester 320 to the second end of the pin 312 is a high voltage, the test value forwarded by the tester 320 receiving the controller 111 is 1, and if the voltage provided by the tester 320 to the second end of the pin 312 is a low voltage, the test value forwarded by the tester 320 receiving the controller 111 is 0, which indicates that the pin 312 can normally operate, except that, the pin 312 cannot normally operate.
According to the chip testing system, the testing result is generated through the testing machine according to the input voltage and the testing value of the pin, so that the pin of the chip can be tested through verifying the input voltage of the pin of the chip, the testing logic can be introduced in the chip design stage, and the testing speed and the testing accuracy are improved.
Fig. 4 is a flowchart illustrating a control method of a chip test system according to an embodiment of the present application.
The control method of the chip testing system of the embodiment of the present application can be executed by the chip testing system provided in the embodiment of the first aspect of the present application, so as to receive the mode switching instruction sent by the testing machine, and control the data selector to switch to the testing mode according to the mode switching instruction, then when the data selector is switched to the test mode, the first input end of the data selector and the output end of the data selector are controlled to be conducted, receiving the test instruction sent by the tester, controlling the test register to output the test value according to the test instruction, and collecting the voltage output by the second end of the pin, and generating the test result of the first end of the pin according to the voltage and the test instruction, so that the output voltage of the pin of the chip can be verified, the pins of the chip are tested, and test logic can be introduced in the chip design stage, so that the test speed and the test accuracy are improved.
As shown in fig. 4, the control method of the chip test system may include the steps of:
In the embodiment of the application, the tester can send a mode switching instruction to the controller through the relevant protocol.
Specifically, when the chip testing system tests the chip, the testing machine may send a mode switching instruction to the controller, and after receiving the mode switching instruction, the controller may control the data selector to switch the current mode to the testing mode according to the mode switching instruction.
Specifically, when the data selector is not in the test mode, the first input end of the data selector and the output end of the data selector are in an off state, and when the data selector is switched to the test mode, the first input end of the data selector and the output end of the data selector are controlled to be conducted.
In the embodiment of the application, the tester may send the test instruction to the tester through the relevant protocol.
Specifically, after the data selector is switched to the test mode, the tester can send a test instruction to the controller through the relevant protocol, and after the controller receives the test instruction, the controller controls the test register to output a test value according to the test instruction.
For clarity of the above embodiment, in an embodiment of the present application, the test instruction may include a test value, and the step of acquiring a voltage output by the second terminal of the pin and generating a test result of the first terminal of the pin according to the voltage and the test instruction includes acquiring a voltage output by the second terminal of the pin and generating a test result according to the voltage and the test value, where the test value is 0 or 1.
Among them, the voltage may include a high voltage, which may be a voltage higher than a specific voltage value (e.g., 1.5V), and a low voltage, which may be a voltage lower than a specific voltage value (e.g., 0.3V).
In the embodiment of the application, when the chip testing system tests the chip, a test result can be generated according to the voltage output by the second end of the pin and the test value output by the test register, which are collected by the testing machine.
Specifically, if the test value output by the test register is 0, the voltage output by the second end of the pin collected by the tester is low voltage, and if the test value output by the test register is yes, the voltage output by the second end of the pin collected by the tester is high voltage, which can indicate that the pin can normally operate.
It should be noted that the foregoing explanation of the chip testing system provided in the embodiment of the first aspect of the present application is also applicable to the control method of the chip testing system of the embodiment, and details are not described here.
In the embodiment of the application, a mode switching instruction sent by a testing machine is received, the data selector is controlled to be switched to a testing mode according to the mode switching instruction, then when the data selector is switched to the testing mode, the first input end of the data selector and the output end of the data selector are controlled to be conducted, the testing instruction sent by the testing machine is received, a testing register is controlled to output a testing value according to the testing instruction, voltage output by the second end of the pin is collected, and a testing result of the first end of the pin is generated according to the voltage and the testing instruction. Therefore, the pins of the chip can be tested by verifying the output voltage of the pins of the chip, and test logic can be introduced in the chip design stage, so that the test speed and the test accuracy are improved.
Fig. 5 is a flowchart illustrating a control method of a chip test system according to another embodiment of the present application.
The control method of the chip testing system of the embodiment of the application can be executed by the chip testing system provided by the embodiment of the second aspect of the application, so as to receive the mode switching instruction sent by the testing machine, and control the data selector to switch to the testing mode according to the mode switching instruction, then when the data selector is switched to the test mode, the first input end of the data selector and the output end of the data selector are controlled to be conducted, receiving the test instruction sent by the tester, controlling the test register to output the test value according to the test instruction, and collecting the voltage output by the second end of the pin, and generating the test result of the first end of the pin according to the voltage and the test instruction, so that the input voltage of the pin of the chip can be verified, the pins of the chip are tested, and test logic can be introduced in the chip design stage, so that the test speed and the test accuracy are improved.
As shown in fig. 5, the control method of the chip test system may include the steps of:
Among them, the voltage may include a high voltage, which may be a voltage higher than a specific voltage value (e.g., 1.5V), and a low voltage, which may be a voltage lower than a specific voltage value (e.g., 0.3V).
Specifically, when the chip testing system tests the chip, the tester may provide a high voltage or a low voltage to the second end of the pin.
In the embodiment of the present application, the test value corresponding to the high voltage is 1, the test value corresponding to the low voltage is 0, when the voltage output from the first end of the pin 312 is the high voltage, the test value read by the rom 313 is 1, and when the voltage output from the first end of the pin 312 is the low voltage, the test value read by the rom 313 is 0.
Specifically, after the tester provides a high voltage or a low voltage to the second end of the pin, the rom may read a test value corresponding to the voltage output by the first end of the pin and send the test value to the controller.
Specifically, after receiving the test value sent by the read-only register, the controller may forward the test value to the tester.
In this embodiment, after receiving the test value forwarded by the controller, the tester may generate a test result of the second end of the pin according to the test value and the voltage provided by the tester to the second end of the pin.
Specifically, if the test machine provides a high voltage to the second end of the pin, the test machine receives a test value forwarded by the controller as 1, that is, the test value corresponding to the voltage output by the first end of the pin is 1, and the test machine provides a low voltage to the second end of the pin, the test machine receives a test value forwarded by the controller as 0, that is, the test value corresponding to the voltage output by the first end of the pin is 0, the pin can normally operate.
It should be noted that the foregoing explanation of the chip testing system provided in the second aspect of the present application is also applicable to the control method of the chip testing system in this embodiment, and is not repeated here.
In the embodiment of the application, a mode switching instruction sent by a testing machine is received, the data selector is controlled to be switched to a testing mode according to the mode switching instruction, then when the data selector is switched to the testing mode, the first input end of the data selector and the output end of the data selector are controlled to be conducted, the testing instruction sent by the testing machine is received, a testing register is controlled to output a testing value according to the testing instruction, voltage output by the second end of the pin is collected, and a testing result of the first end of the pin is generated according to the voltage and the testing instruction. Therefore, the pins of the chip can be tested by verifying the input voltage of the pins of the chip, and test logic can be introduced in the chip design stage, so that the test speed and the test accuracy are improved.
In the description of the present specification, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (10)
1. A chip testing system is characterized by comprising a chip and a tester, wherein the chip is connected with the tester,
the chip comprises a controller, a pin, a data selector and a test register, wherein the controller is respectively connected with a control end of the data selector and a control end of the test register, a first input end of the data selector is connected with an output end of the test register, an output end of the data selector is connected with a first end of the pin, and a second end of the pin is connected with the tester;
the controller is used for receiving a mode switching instruction sent by the testing machine and controlling the data selector to be switched to a testing mode according to the mode switching instruction;
the data selector is used for controlling the conduction of a first input end of the data selector and an output end of the data selector when the data selector is switched to a test mode;
the controller is also used for receiving a test instruction sent by the tester and controlling the test register to output a test value according to the test instruction;
the tester is used for collecting the voltage output by the second end of the pin and generating a test result of the first end of the pin according to the voltage and the test instruction.
2. The chip test system according to claim 1, wherein the test instructions include the test values, and the tester is specifically configured to:
and collecting the voltage output by the second end of the pin, and generating the test result according to the voltage and the test value, wherein the test value is 0 or 1.
3. The chip test system of claim 1, wherein the chip further comprises a functional path, the functional path coupled to the second input of the data selector, the data selector further configured to:
and when the data selector is switched to the test mode, controlling the second input end of the data selector to be closed.
4. The chip test system according to claim 3, wherein the data selector is further configured to:
and when the chip is powered on, controlling the second input end of the data selector and the output end of the data selector to be conducted, and controlling the first input end of the data selector to be closed.
5. A chip testing system is characterized by comprising a chip and a tester, wherein the chip is connected with the tester,
the chip comprises a controller, a pin and a read-only register, wherein the controller is connected with a control end of the read-only register, a first end of the pin is connected with an input end of the read-only register, and a second end of the pin is connected with the tester;
the tester is used for providing voltage for the second end of the pin;
the read-only register is used for reading a test value corresponding to the voltage output by the first end of the pin and sending the test value to the controller;
the controller is used for forwarding the test value to the tester;
the tester is further configured to generate a test result of the second end of the pin according to the voltage and the test value.
6. The chip test system according to claim 5, wherein the test value is 0 or 1.
7. A control method based on the chip test system of any one of claims 1 to 4, comprising:
receiving a mode switching instruction sent by the testing machine, and controlling the data selector to switch to a testing mode according to the mode switching instruction;
when the data selector is switched to a test mode, controlling the first input end of the data selector and the output end of the data selector to be conducted;
receiving a test instruction sent by the tester, and controlling the test register to output a test value according to the test instruction;
and acquiring the voltage output by the second end of the pin, and generating a test result of the first end of the pin according to the voltage and the test instruction.
8. The method of claim 7, wherein the test instruction includes the test value, and the collecting the voltage output by the second terminal of the pin and generating the test result of the first terminal of the pin according to the voltage and the test instruction comprises:
and collecting the voltage output by the second end of the pin, and generating the test result according to the voltage and the test value, wherein the test value is 0 or 1.
9. A control method based on the chip test system of any one of claims 5-6, comprising:
providing a voltage to a second end of the pin;
reading a test value corresponding to the voltage output by the first end of the pin, and sending the test value to the controller;
forwarding the test value to the tester;
and generating a test result of the second end of the pin according to the voltage and the test value.
10. The method for controlling a chip test system according to claim 9, wherein the test value is 0 or 1.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115902595A (en) * | 2023-02-20 | 2023-04-04 | 之江实验室 | Chip testing system and chip testing method |
| CN117031256A (en) * | 2023-10-07 | 2023-11-10 | 紫光同芯微电子有限公司 | Chip testing system and method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115902595A (en) * | 2023-02-20 | 2023-04-04 | 之江实验室 | Chip testing system and chip testing method |
| CN117031256A (en) * | 2023-10-07 | 2023-11-10 | 紫光同芯微电子有限公司 | Chip testing system and method |
| CN117031256B (en) * | 2023-10-07 | 2024-03-01 | 紫光同芯微电子有限公司 | Chip testing system and method |
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