CN115267481A - Chip test circuit and chip test device - Google Patents
Chip test circuit and chip test device Download PDFInfo
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- CN115267481A CN115267481A CN202210028156.5A CN202210028156A CN115267481A CN 115267481 A CN115267481 A CN 115267481A CN 202210028156 A CN202210028156 A CN 202210028156A CN 115267481 A CN115267481 A CN 115267481A
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- circuit
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- chip test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
Abstract
The application discloses chip test circuit and chip testing arrangement, wherein, this chip test circuit includes: the gating circuit is connected with external chip test equipment to receive the control signal sent by the chip test equipment and generate a gating signal based on the control signal; the at least two relays are connected with the gating circuit and respectively connected with the external chip to be tested so as to receive the gating signal sent by the gating circuit and selectively conduct one or more of the at least two relays under the action of the gating signal, so that the corresponding one or more chips to be tested are connected with the chip testing equipment. In this way, the chip test circuit of this application can increase relay control channel's quantity, carries on a plurality of relays to satisfy the test demand of more with surveying chip quantity, and promote the efficiency of chip test, can not additionally increase too many realization cost simultaneously again.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a chip testing circuit and a chip testing device.
Background
With the rapid development of the integrated circuit industry, the semiconductor testing and service industry is becoming more and more important within the entire semiconductor industry chain. Before the production of chips, tests are required to detect whether an IC (Integrated Circuit Chip) is defective or not during the manufacturing process, whether the electrical performance is normal or not, and the like. At present, an Automatic Test Equipment (ATE) is mainly used in the industry to Test an IC, and specifically, an IC Test board is used to carry a chip to be tested, and then the IC Test board is butted with an ATE Test machine to complete the whole Test.
At present, the ATE itself is very expensive, and the ATE is also very precious when testing machines in a test factory, usually charging for hours or minutes, and as the chip design becomes more and more complex, the test cost of the chip accounts for the total cost more and more. In order to effectively reduce the cost of chip testing, the design trend of IC Test boards is gradually changing from the beginning of only mounting 1 DUT (Device Under Test) to simultaneously testing 4, 8, 16 or even 32 DUTs.
However, when the number of chips under test increases, the number of relays needed to be used by the DUT auxiliary circuit in the IC test board increases, and thus the number of relay control signals from the machine is correspondingly increased, but the number of relay control signals in the basic configuration of ATE is limited, and the space on the IC test board is also limited, so that too many relays cannot be placed, thereby greatly limiting the number of chips under test by the ATE test machine, and having to perform testing of multiple chips in batches, thereby greatly increasing the cost of testing multiple chips.
Disclosure of Invention
The application provides a chip test circuit and chip testing arrangement, this chip test circuit can solve the synchronous test that the chip test circuit among the prior art can't effectively realize more chips to when having a plurality of chips to test, need go on in batches, so that the higher problem of test cost.
In order to solve the technical problem, the application adopts a technical scheme that: a chip test circuit is provided, wherein the chip test circuit includes: the gating circuit is connected with external chip test equipment to receive the control signal sent by the chip test equipment and generate a gating signal based on the control signal; the at least two relays are connected with the gating circuit and respectively connected with the external chip to be tested so as to receive the gating signal sent by the gating circuit and selectively conduct one or more of the at least two relays under the action of the gating signal, so that the corresponding one or more chips to be tested are connected with the chip testing equipment.
The gating circuit comprises an amplifying sub-circuit, wherein the amplifying sub-circuit is connected with the chip testing equipment and the at least two relays, so that when the control signals sent by the chip testing equipment are received, the number of the relays which are currently to be conducted is determined, and the control signals are amplified based on the number of the relays which are currently to be conducted, so that the gating signals are generated.
The gating circuit comprises at least two driving chips which are cascaded with each other, each driving chip is correspondingly connected with at least two relays, one driving chip is connected with the chip testing equipment to receive the control signal sent by the chip testing equipment and forward the control signal to other driving chips, and each driving chip generates a gating signal based on the control signal.
The chip test circuit further comprises a power supply circuit, and the power supply circuit is connected with the gating circuit and the at least two relays to provide working power for the gating circuit and the at least two relays.
The gating circuit receives the relay power supply provided by the chip testing equipment and provides the relay power supply to one or more of the at least two relays which are currently aimed to be conducted based on the control signal.
The chip testing circuit further comprises a connecting circuit, the connecting circuit is connected with the chip testing equipment, the gating circuit and the at least two relays, and the gating circuit is connected with the chip testing equipment and the at least two relays through the connecting circuit.
The chip test circuit further comprises a chip test substrate, the chip test substrate is connected with the gating circuit and the at least two relays, and the at least two relays are vertically arranged on one side face of the chip test substrate.
The chip testing circuit further comprises a connector, the connector is connected with the chip testing substrate, the gating circuit and the at least two relays, and the at least two relays are vertically arranged on one side face of the chip testing substrate through the connector.
The number of the chips to be tested, which are correspondingly connected with each relay, is one or more.
In order to solve the above technical problem, the present application adopts another technical solution: providing a chip testing device, wherein the chip testing device comprises a mounting base plate and a chip testing circuit arranged on the mounting base plate; wherein the chip test circuit is the chip test circuit as described in any one of the above.
The beneficial effect of this application is: different from the prior art, the gating circuit in the chip test circuit in the application is connected with the external chip test equipment to receive the control signal sent by the chip test equipment, and the gating signal is generated based on the control signal, so that the gating signal can be sent to the at least two relays, so that the at least two relays are selectively conducted one or more of the relays under the action of the gating signal, so that the corresponding one or more chips to be tested are connected with the chip test equipment, and the chip test equipment performs synchronous test.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of a first embodiment of a chip test circuit according to the present application;
FIG. 2 is a schematic structural diagram of a second embodiment of a chip test circuit according to the present application;
FIG. 3 is a schematic structural diagram of a third embodiment of a chip test circuit according to the present application;
FIG. 4 is a detailed structural diagram of an embodiment of a driver chip in the chip testing circuit of FIG. 3;
FIG. 5 is a schematic structural diagram of a fourth embodiment of a chip test circuit according to the present application;
FIG. 6 is a schematic structural diagram of a fifth embodiment of the chip test circuit of the present application;
FIG. 7 is a schematic structural diagram of a sixth embodiment of a chip test circuit according to the present application;
FIG. 8 is a schematic structural diagram of a seventh embodiment of a chip test circuit according to the present application;
FIG. 9 is a schematic structural diagram of an eighth embodiment of a chip test circuit according to the present application;
FIG. 10 is a schematic structural diagram of an embodiment of a chip testing apparatus according to the present application.
Detailed Description
In order to make the technical problems, the adopted technical solutions, and the achieved technical effects of the present application clearer, the technical solutions of the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip test circuit according to a first embodiment of the present application. In the present embodiment, the chip test circuit 10 includes: a gating circuit 11 and at least two relays 12.
For example, at least one chip 3 to be tested can be connected to the chip test circuit 10 to be connected with the automatic test equipment through the chip test circuit 10 and the chip test equipment 2, so that various chip test items are correspondingly completed by the chip test equipment 2, and the chip test circuit 10 therein can be used for forwarding and adjusting corresponding control signals and power signals, and connection between the chip 3 to be tested and the chip test equipment 2 and gating control of a corresponding test channel thereof. Of course, in other embodiments, the chip test circuit 10 can also be used for testing any other reasonable electronic device to be tested, and the embodiment does not limit this.
Specifically, the gating circuit 11 in the chip test circuit 10 may specifically include any reasonable program processing Unit such as an MCU (Micro Control Unit), a single chip or a processor, so as to generate the gating signal correspondingly based on the program data pre-loaded by the gating circuit or the Control signal sent by the chip test device 2. In other embodiments, the gating circuit 11 may also be a functional circuit that includes a plurality of switching tubes, and the switching tubes have a specific connection relationship, so that when receiving the control signal sent by the chip testing apparatus 2, at least one of the paths can be selectively turned on to correspondingly generate the gating signal, which is not limited in this application.
Furthermore, the gating circuit 11 is also correspondingly connected with at least two relays 12, and each relay 12 is further correspondingly connected with at least one chip 3 to be tested. It can be understood that the gating circuit 11 can send corresponding gating signals to the at least two relays 12 respectively to enable the at least two relays 12 to selectively conduct one or more of the relays 12 under the action of the gating signals, so that the one or more chips 3 to be tested connected to the currently conducted relays 12 can be correspondingly connected with the chip testing equipment 2. And the chip test equipment 2 can further perform various functional tests on one or more chips 3 to be tested connected with the chip test equipment.
The relay 12 (english name: relay) is an electric control device, and is an electric appliance that generates a predetermined step change in the controlled amount in an electric output circuit when a change in the input amount (excitation amount) meets a predetermined requirement. It has an interactive relationship between a control system (also called an input loop) and a controlled system (also called an output loop). It is commonly used in automated control circuits, which are actually a "recloser" that uses low current to control high current operation. Therefore, the circuit plays the roles of automatic regulation, safety protection, circuit conversion and the like.
Optionally, the number of the relays 12 in the chip test circuit 10 may specifically be any reasonable number, such as 2, 4, 8, 16, or 32, which is not limited in this application.
Optionally, the number of the chips 3 to be tested, which are correspondingly connected to each relay 12, may be any reasonable number, such as 1, 2, or 4, which is not limited in this application.
Above-mentioned scheme, through carrying on a plurality of relays 12 in chip test circuit 10, and carry out gating control to a plurality of relays 12 based on gating circuit 11, the quantity of the relay 12 control channel who is used for the chip test in can effectively increasing chip test circuit 10, with the test demand that can satisfy more with surveying the chip quantity, and effectively promote the efficiency of chip test, and still need not reequip chip test equipment 2 simultaneously, the framework of the chip test circuit 10 that corresponds is also simpler, easy to design, expansibility is strong, consequently, can not additionally increase too many realization cost yet.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip test circuit according to a second embodiment of the present application. In this embodiment, on the basis of the first embodiment of the chip test circuit provided in this application, the gating circuit 21 in the chip test circuit 20 further includes an amplifying sub-circuit 211.
It can be understood that, in different test scenarios, the number of the chips 3 to be tested, which are usually intended to be tested synchronously, may also be different, the number of the corresponding chips 3 to be tested, which are connected to the chip test device 2, and the number of the relays 22 corresponding to the chips 3 to be tested are also different, and the voltage and the current corresponding to the control signal, which is usually output to the gating circuit 21 by the chip test device 2, are usually constant, and the constant control signal obviously has a requirement that the synchronous test cannot be performed by matching with the different number of chips 3 to be tested, that is, when the number of the chips 3 to be tested, which need to be tested simultaneously, is too large, there are many test paths for dividing and shunting the corresponding control signal and the gating signal, so that the voltage and the current corresponding to each of the test paths, for example, the current value of the gating signal may not be able to perform an effective test on the chip 3 to be tested because of being too small.
In this embodiment, the amplifying sub-circuit 211 is specifically connected to the chip testing device 2 and the at least two relays 22, so that when the control signal sent by the chip testing device 2 is received, the number of the relays 22 currently intended to be turned on can be determined, and then the control signal can be correspondingly amplified based on the number of the relays 22 currently intended to be turned on, so as to generate an effective gating signal, and then the connection and signal interaction between the chip 3 to be tested and the chip testing device 2 in a specific number can be correspondingly realized.
It is understood that, in the present embodiment, the gating circuit 21 and the relay 22 are the same as the gating circuit 11 and the relay 12, respectively, and specific reference is made to fig. 1 and related text, which are not repeated herein.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of a chip test circuit according to the present application. In this embodiment, on the basis of the first embodiment of the chip test circuit provided in the present application, the gating circuit 31 in the chip test circuit 30 further includes at least two driving chips 312 cascaded with each other.
Specifically, each driving chip 312 in the gating circuit 31 is correspondingly connected with at least two relays 32, and one of the driving chips 312 is used for connecting the chip testing device 2 to receive the control signal sent by the chip testing device 2, and can correspondingly forward the control signal to other driving chips 312, so that each of the driving chips 312 can correspondingly generate a gating signal based on the control signal to selectively turn on one or more of the at least two relays 32 connected to the corresponding driving chip 312, and further, the corresponding one or more chips 3 to be tested are connected with the chip testing device 2 to complete the chip test of this time.
In a specific embodiment, as shown in fig. 4, fig. 4 is a detailed structural schematic diagram of an embodiment of the driving chip 312 in the chip testing circuit 30 in fig. 3, wherein, taking an example that the chip testing circuit 30 specifically includes two driving chips 312, the two driving chips 312 specifically have two operating modes, one is that a single driving chip 312 is used alone, at this time, the single driving chip 312 can realize output of 8 relay control signals by receiving input of one relay control signal, so as to correspondingly realize gating control of 8 relays 32; one is that two driver chips 312 are cascaded, and a DOUT (output) pin of a first driver chip 312 is connected to a DIN (input) pin of a second driver chip 312, so that 16 relay control signals can be directly and simultaneously output only by receiving the input of one relay control signal, thereby correspondingly realizing the gating control of 16 relays 32. In other embodiments, the number of the driving chips 312 in the chip test circuit 30 may be any reasonable number, such as 1, 3, 5, or 6, which is not limited in this application.
It is understood that, in the present embodiment, the gating circuit 31 and the relay 32 are respectively the same as the gating circuit 11 and the relay 12, and please refer to fig. 1 and the related text, which are not repeated herein.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a fourth embodiment of the chip test circuit of the present application. In this embodiment, on the basis of the first embodiment of the chip test circuit provided in the present application, the chip test circuit 40 further includes a power supply circuit 43.
It is understood that, in order to effectively drive the gating circuit 41 and the at least two relays 42 to operate, the working power supply needs to be provided to the gating circuit.
Specifically, the power circuit 43 connects the gate circuit 41 and the at least two relays 42, respectively, to provide the gate circuit 41 and the at least two relays 42 with operating power.
In another embodiment, the gating circuit 41 may specifically further receive a power supply of the relay 42 provided by the chip testing device 2, and provide the power supply of the relay 42 to one or more of the at least two relays 42 that are currently intended to be turned on based on the control signal, so as to provide an operating power supply for the relay 42 that is currently required to be turned on.
It is understood that, in the present embodiment, the gating circuit 41 and the relay 42 are respectively the same as the gating circuit 11 and the relay 12, and please refer to fig. 1 and the related text, which are not repeated herein.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a fifth embodiment of a chip test circuit according to the present application. In this embodiment, on the basis of the first embodiment of the chip test circuit provided in the present application, the chip test circuit 50 further includes a connection circuit 54.
It can be understood that, since the chip testing device 2, the gating circuit 51 and the at least two relays 52 usually have different electrical characteristics, for example, different terminals for external connection, the chip testing device 2 usually uses interfaces and data lines to connect with other electronic devices, and the relays 52 are specifically plugged by pins, so that an appropriate connection circuit 54 is required to be correspondingly provided for effective electrical connection of the three devices.
Specifically, the connection circuits 54 are respectively connected to the chip testing device 2, the gate circuit 51, and the at least two relays 52, so that the gate circuit 51 can be connected to the chip testing device 2 and the at least two relays 52 through the connection circuits 54.
It is understood that, in the present embodiment, the gating circuit 51 and the relay 52 are respectively the same as the gating circuit 11 and the relay 12, and please refer to fig. 1 and the related text, which are not repeated herein.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a sixth embodiment of a chip test circuit according to the present application. In this embodiment, on the basis of the first embodiment of the chip test circuit provided in the present application, the chip test circuit 60 further includes a chip test substrate 65.
It can be understood that the chip test substrate 65 can be specifically understood as various existing functional circuit boards for implementing chip testing, and the chip test circuit 60 corresponds to an extension circuit for implementing function extension of the chip test substrate 65, and specifically, the number of the relays 62 that can be simultaneously mounted on the chip test substrate 65 is extended, so as to effectively increase the number of chips that can be simultaneously tested and correspondingly implemented by the chip test substrate 65.
Specifically, the chip test substrate 65 connects the gate circuit 61 and the at least two relays 62, and the at least two relays 62 are vertically mounted on one side of the chip test substrate 65.
Therefore, the chip test circuit 60 can be directly copied and applied to other various types of chip test substrates 65, so that the upper limit of the number of chips to be simultaneously tested by the chip test substrates 65 can be expanded, and the expansibility is strong, and the application range is wide.
By vertically mounting at least two relays 62 on one side of the chip test substrate 65, it is not necessary to occupy too much area on the test motherboard, and thus a wider range of applications of the chip test substrate 65 can be realized by mounting a plurality of chip test circuits 60 or a greater number of relays 62.
It is understood that, in the present embodiment, the gating circuit 61 and the relay 62 are the same as the gating circuit 11 and the relay 12, respectively, and specific reference is made to fig. 1 and related text, which are not repeated herein.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a seventh embodiment of a chip test circuit according to the present application. In this embodiment, on the basis of the sixth embodiment of the chip test circuit provided in the present application, the chip test circuit 70 further includes a connector 76.
It will be appreciated that the relay 72 is typically connected to other electronic devices or devices through its pins, and thus requires a specific plug port.
Specifically, the connector 76 connects the chip test substrate 75 and the gating circuit 71, and has a plug port corresponding to the relay 72 to enable connection with at least two relays 72, so that at least two relays 72 can be vertically mounted on one side of the chip test substrate 75 through the connector 76 without occupying too much area on the test motherboard, and a larger range of extended applications of the chip test substrate 75 can be realized by mounting a larger number of relays 72.
It is understood that, in the present embodiment, the gating circuit 71, the relay 72 and the chip testing substrate 75 are the same as the gating circuit 61, the relay 62 and the chip testing substrate 65, respectively, please refer to fig. 7 and related text, which are not repeated herein.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an eighth embodiment of a dual-server adaptive circuit chip test circuit according to the present application.
In this embodiment, the chip testing circuit 80 specifically includes a Relay expansion circuit 81 and a chip testing substrate 82 connected to each other, and the Relay expansion circuit 81 further includes a control signal expansion sub-circuit 811, a connector 812 and at least two relays 813 (relays) connected to each other, and the connector 812 is used to connect an ATE testing machine, that is, an external chip testing device 2 and at least two chips 3 to be tested (DUTs), and the at least two chips 3 to be tested are specifically disposed on the chip testing substrate 82.
Wherein, generally use chip test base plate 82 as the ATE test board during chip testing and await measuring the interface channel between the chip 3, chip test base plate 82 will carry a plurality of chips 3 that await measuring simultaneously generally, and the chip 3 that await measuring need use a large amount of relays 813 for testing each signal channel. In this embodiment, the relay expansion circuit 81 is specifically vertically mounted on the chip test substrate 82 through the connector 812, and the relay control signal, the relay power supply, the switching signal (power supply) and the switching signal (digital) provided by the ATE tester reach the relay expansion circuit 81 through the connector 812, and are amplified by the control signal expansion sub-circuit 811, so as to control the plurality of relays 813 simultaneously.
The power supply and the switching signal required by the relay 813 on the relay expansion circuit 81 are transmitted from the connector 812 or transmitted to the chip test substrate 82 through the connector 812. By using the relay expansion circuit 81, on one hand, the plurality of relays 813 can be controlled to be turned off simultaneously, and on the other hand, more relays 813 can be carried on the chip test substrate 82, so that the requirement of more DUTs to be tested simultaneously can be met.
The relay control signal provided by the ATE tester is specifically amplified by the control signal expansion sub-circuit 811 to output a control signal for the plurality of relays 813 to use simultaneously. The switching signal (power or digital) reaches the corresponding relay 813 through the connector 812, is returned to the connector 812 after being subjected to channel switching by the relay 813, and reaches the chip test substrate 82 through the connector 812 again to be supplied to each chip 3 to be tested.
Fig. 10 shows a schematic structural diagram of an embodiment of the chip testing apparatus according to the present application, where fig. 10 is a schematic structural diagram.
In the present embodiment, the chip test apparatus 91 includes a mounting substrate 911 and a chip test circuit 912 provided on the mounting substrate 911; the chip test circuit 912 is any one of the chip test circuits 10 to 80, and please refer to fig. 1 to 9 and related text for details, which are not repeated herein.
It will be appreciated that the mounting substrate 911 may specifically be a mounting structure housing the chip test circuitry 912, and that the chip test circuitry 912 is mounted on or within the mounting substrate 911 to provide strength support and protection to the chip test circuitry 912 through the mounting substrate 911.
Different from the prior art, the gating circuit in the chip test circuit in the application is connected with the external chip test equipment to receive the control signal sent by the chip test equipment, and the gating signal is generated based on the control signal, so that the gating signal can be sent to the at least two relays, one or more of the at least two relays can be selectively switched on under the action of the gating signal, and further, the corresponding one or more chips to be tested are connected with the chip test equipment, so that the chip test equipment can carry out synchronous test.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (10)
1. A chip test circuit, comprising:
the gating circuit is connected with external chip test equipment to receive the control signal sent by the chip test equipment and generate a gating signal based on the control signal;
and the at least two relays are connected with the gating circuit and respectively connected with an external chip to be tested so as to receive the gating signal sent by the gating circuit and selectively conduct one or more of the at least two relays under the action of the gating signal, so that the corresponding one or more chips to be tested are connected with the chip test equipment.
2. The chip test circuit according to claim 1,
the gating circuit comprises an amplifying sub-circuit, wherein the amplifying sub-circuit is connected with the chip testing equipment and at least two relays, so that when the control signal sent by the chip testing equipment is received, the number of the relays which are currently to be conducted is determined, and the control signal is amplified based on the number of the relays which are currently to be conducted, so that the gating signal is generated.
3. The chip test circuit of claim 1,
the gating circuit comprises at least two driving chips which are cascaded with each other, each driving chip is correspondingly connected with at least two relays, one driving chip is connected with the chip testing equipment to receive the control signal sent by the chip testing equipment and forward the control signal to other driving chips, and each driving chip generates the gating signal based on the control signal.
4. The chip test circuit of claim 1,
the chip test circuit further comprises a power supply circuit, and the power supply circuit is connected with the gating circuit and the at least two relays to provide working power for the gating circuit and the at least two relays.
5. The chip test circuit of claim 1,
the gating circuit receives the relay power supply provided by the chip testing equipment and provides the relay power supply to one or more of at least two relays which are currently aimed to be conducted based on the control signal.
6. The chip test circuit of claim 1,
the chip test circuit further comprises a connecting circuit, the connecting circuit is connected with the chip test equipment, the gating circuit and the at least two relays, and the gating circuit is connected with the chip test equipment and the at least two relays through the connecting circuit.
7. The chip test circuit according to claim 1,
the chip test circuit further comprises a chip test substrate, the chip test substrate is connected with the gating circuit and the at least two relays, and the at least two relays are vertically arranged on one side face of the chip test substrate.
8. The chip test circuit of claim 7,
the chip test circuit further comprises a connector, wherein the connector is connected with the chip test substrate, the gating circuit and the at least two relays, and the at least two relays are vertically arranged on one side face of the chip test substrate through the connector.
9. The chip test circuit according to any one of claims 1 to 8, wherein the number of the chips to be tested, which are correspondingly connected to each relay, is one or more.
10. The chip testing device is characterized by comprising an installation bottom plate and a chip testing circuit arranged on the installation bottom plate;
wherein the chip test circuit is as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210028156.5A CN115267481A (en) | 2022-01-11 | 2022-01-11 | Chip test circuit and chip test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210028156.5A CN115267481A (en) | 2022-01-11 | 2022-01-11 | Chip test circuit and chip test device |
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| CN115267481A true CN115267481A (en) | 2022-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210028156.5A Pending CN115267481A (en) | 2022-01-11 | 2022-01-11 | Chip test circuit and chip test device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115856588A (en) * | 2023-02-22 | 2023-03-28 | 长鑫存储技术有限公司 | Chip test board and test method |
| CN116454069A (en) * | 2023-06-14 | 2023-07-18 | 深圳中安辰鸿技术有限公司 | Semiconductor chip and HTOL, delay and overall test method thereof |
-
2022
- 2022-01-11 CN CN202210028156.5A patent/CN115267481A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115856588A (en) * | 2023-02-22 | 2023-03-28 | 长鑫存储技术有限公司 | Chip test board and test method |
| CN116454069A (en) * | 2023-06-14 | 2023-07-18 | 深圳中安辰鸿技术有限公司 | Semiconductor chip and HTOL, delay and overall test method thereof |
| CN116454069B (en) * | 2023-06-14 | 2023-09-15 | 深圳中安辰鸿技术有限公司 | Semiconductor chip and HTOL, delay and overall test method thereof |
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