CN106771987A - A kind of IC chip ageing tester and method of testing based on mother baby plate - Google Patents
A kind of IC chip ageing tester and method of testing based on mother baby plate Download PDFInfo
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- CN106771987A CN106771987A CN201710135630.3A CN201710135630A CN106771987A CN 106771987 A CN106771987 A CN 106771987A CN 201710135630 A CN201710135630 A CN 201710135630A CN 106771987 A CN106771987 A CN 106771987A
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- chip
- aging
- daughter board
- tested
- motherboard
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to a kind of IC chip ageing tester based on mother baby plate and method of testing, the device includes universal burn-in motherboard and multiple aging daughter boards；Universal burn-in motherboard is provided with multiple stations, and the multiple spring needles arranged in array are provided with station；Aging daughter board is mountable on a station of universal burn-in motherboard, and its front is provided with chip installation portion and is integrated with peripheral applications circuit；The multiple hard contacts arranged in array are installed on the back side of aging daughter board, wherein, a part for multiple hard contacts is connected with the pin of chip to be tested, and another part is connected with peripheral applications circuit；Contact pin on station matches and is in contact with the hard contact at the aging daughter board back side, so as to aging daughter board is accessed into universal burn-in motherboard；Additionally provide a kind of method of testing.The present invention can be applied to polytype IC chip carry out degradation and it is aging after performance test, effectively save testing cost, reduce test period.
Description
Technical field
The present invention relates to the degradation technical field of IC products, and in particular to a kind of based on the integrated of mother baby plate
Circuit chip ageing tester and method of testing.
Background technology
IC chip, typically will be by burn-in test before being produced in batches（Ensure the use longevity of chip
Life and reliability）And performance test（The batch production test of the function and performance of chip）, by the integrated of both the above test
Circuit chip can just be defined as non-defective unit.Traditional burn-in board is usually the aging PCB of multistation with least 77 stations
Plate, each station is provided with special chip socket, the pin of chip to be tested is introduced into aging pcb board, to multiple cores to be tested
Piece carries out the powered degradation of HTHP.
However, the species of chip under test is various, the arrangement of its encapsulation pattern and pin is different, therefore for different types of
Chip under test is, it is necessary to customized different burn-in board.The design and manufacture cost of current burn-in board is higher, brings very high
Testing cost, for those univalent relatively low and measurement circuit more difficult receiving of simple product.Additionally, customized burn-in board
The early-stage preparations time is more long, increases test period, reduces testing efficiency.
The content of the invention
For the shortcoming or deficiency of above-mentioned prior art, the technical problem to be solved in the present invention is to provide a kind of based on primary and secondary
The IC chip ageing tester and method of testing of plate, on the premise of test accuracy is ensured, can be applied to many
The IC chip of type carry out degradation and it is aging after performance test, so as to effectively save testing cost,
Reduce test period.
In order to solve the above technical problems, the present invention has following composition：
A kind of IC chip ageing tester based on mother baby plate, the device includes that universal burn-in motherboard and multiple are aging
Daughter board；Universal burn-in motherboard is provided with multiple stations, golden finger interface and power interface, is provided with what is arranged in array on station
Multiple contact pins, golden finger interface is used to be connected with degradation board；Aging daughter board is mountable to the one of universal burn-in motherboard
On station, its front is provided with chip installation portion and is integrated with peripheral applications circuit, and chip to be tested is installed on chip installation
Portion, peripheral applications circuit matches with the chip to be tested that chip installation portion is installed；It is provided with the back side of aging daughter board and is in
Multiple hard contacts of array arrangement, wherein, a part and the chip installation portion of multiple hard contacts install chip to be tested
Pin be electrically connected with, the peripheral applications circuit on another part and aging daughter board front is electrically connected with；Contact pin on station with
The hard contact at the aging daughter board back side matches and is in contact, so as to aging daughter board is accessed into universal burn-in motherboard.
The contact pin is spring needle.
Chip to be tested is installed on the chip installation portion on aging daughter board in paster mode.
Chip to be tested is installed on the chip installation portion on aging daughter board with inserting mode, and the chip installation portion is provided with
One chip carrier socket for being used for grafting chip to be tested.
Between the chip to be tested that all of peripheral applications circuit and chip installation portion are installed on the aging daughter board,
It is electrically connected with by 0 Ohmic resistance.
The device also includes that a chip connects socket, and chip connection socket includes a socket, survey is provided with socket
Test plate (panel), test board is provided with the multiple spring needles arranged in array, spring needle matches with the hard contact at the aging daughter board back side,
And be in contact, so that the chip access performance tester after just aging.
The aging daughter board is fixed on universal burn-in motherboard by bolt, nut, and aging daughter board is provided with and is passed through for bolt
Through hole.
A kind of IC chip ageing testing method based on mother baby plate, comprises the following steps：
（1）For the chip to be tested of different types, matched peripheral applications circuit is being integrated in aging daughter board just
Face；And hard contact array is installed at the back side of aging daughter board；
（2）Chip to be tested is installed on the chip installation portion of aging daughter board, and by the pin and peripheral applications of chip to be tested
Circuit is connected with corresponding hard contact respectively；
（3）The aging daughter board with chip to be tested is installed on the station of universal burn-in motherboard；
（4）Universal burn-in motherboard is connected with degradation board, the old of degradation board is introduced with by aging daughter board
Change drive signal, carry out hot and humid dynamic aging test；
（5）After degradation terminates, aging daughter board is removed from universal burn-in motherboard, and by the peripheral applications on aging daughter board
Circuit with it is aging after chip disconnect；
（6）Aging daughter board with aging rear chip is connected with performance testing apparatus, with by the gold at the aging daughter board back side
Category contact introduces the test signal of performance testing apparatus, carries out performance test.
Between the chip to be tested that all of peripheral applications circuit and chip installation portion are installed on the aging daughter board,
It is electrically connected with by 0 Ohmic resistance；Through the step（4）After degradation, 0 Ohmic resistance is removed using high temperature flatiron tip-off,
Peripheral applications circuit is set to be disconnected with chip.
The step（6）In, the aging daughter board with aging rear chip connects socket and ability meter by a chip
Device is connected；Chip connection socket includes a socket, and test board is provided with socket, and test board is provided with to be arranged in array
Multiple spring needles, spring needle matches and is in contact with the hard contact at the aging daughter board back side, so as to the chip after will be aging
Access performance tester.
Compared with prior art, the advantage of the invention is that：
（1）Using the mother baby plate structure being made up of universal burn-in motherboard and aging daughter board, boss's daughter board is mountable to universal burn-in
On one station of motherboard, chip to be tested is installed on the chip installation portion on aging daughter board；It is mountable to using change general old
The aging daughter board changed on motherboard change in the prior art whole burn-in board to substitute, it is no longer necessary to according to different encapsulation patterns
Product subscription specific whole burn-in board, considerably reduce testing cost, reduce test period, improve test
Efficiency, is highly suitable for the burn-in test of various different encapsulating products.
（2）The back side of aging daughter board is provided with multiple hard contacts, and a portion hard contact is to be measured with what is installed
The pin for trying chip is connected, and another part is connected with the peripheral applications circuit on aging daughter board front；On the one hand, setting
Hard contact is easy to be connected with the contact pin on universal burn-in motherboard station；On the other hand, after degradation terminates, periphery is made
Application circuit is disconnected with chip, and the aging daughter board access performance tester with aging rear chip is rapidly carried out aging
The performance test of chip afterwards.
Brief description of the drawings
Fig. 1：The structural representation of universal burn-in mother matrix in the present invention.
Fig. 2：The positive structure schematic of aging daughter board in the present invention.
Fig. 3：The structure schematic diagram of aging daughter board in the present invention.
Fig. 4：The cooperation schematic diagram of chip to be tested and aging daughter board in the present invention.
Fig. 5：The decomposing schematic representation of aging daughter board and universal burn-in motherboard in the present invention with chip to be tested.
Fig. 6：The structural representation that chip to be tested in the aging daughter board of the present invention is connected with peripheral applications circuit.
Fig. 7：Chips of the present invention connect the structural representation of socket.
Fig. 8：The structural representation of test board in chip connection socket of the present invention.
Specific embodiment
The technique effect of design of the invention, concrete structure and generation is described further below with reference to accompanying drawing, with
It is fully understood from the purpose of the present invention, feature and effect.
As shown in Figures 1 to 8, a kind of IC chip ageing tester based on mother baby plate, including universal burn-in
Motherboard 10 and multiple aging daughter boards 20.
Universal burn-in motherboard 10 be provided with multiple stations 11 for installing aging daughter board 20, for degradation board
Golden finger interface 12, power interface 13 and the LED light being connected, are provided with the multiple contact pins arranged in array on station 11
111；Wherein, golden finger 12, power interface 13 and LED light, to realize drive module, power supply and the work of degradation board
The functions such as the access that work is indicated.In specific embodiment, universal burn-in motherboard 10 is by epoxide resin material（FR5）What sheet material was made
Pcb board, epoxide resin material has service life high, it is ensured that universal burn-in motherboard can repeatedly be multiplexed.
Aging daughter board 20 is the pcb board of certain specification size, is mountable on a station 11 of universal burn-in motherboard 10, and
It is fixed on universal burn-in motherboard 10 using bolt, nut in surrounding, the surrounding of boss's daughter board 20 is provided with what is passed through for bolt
Through hole 24.
The front of aging daughter board 20 is provided with chip installation portion 21 and is integrated with peripheral applications circuit, chip to be tested 30
It is installed on chip installation portion 21；Peripheral applications circuit matches with the chip to be tested 30 that chip installation portion 21 is installed, specifically
For：Collect the periphery that paired chip carries out degradation according to the encapsulation pattern and pin arrangements of the chip to be tested installed
Application circuit.It is the state of the art for the integrated approach of peripheral applications circuit, will not be repeated here.
In the present invention, chip to be tested 30 can be installed on the core on aging daughter board 20 by paster mode or inserting mode
Piece installation portion 21；When being installed using inserting mode, chip installation portion 21 is provided with one is used for the core of grafting chip 30 to be tested
Piece socket.For with paster mode and the method with inserting mode chip, being well-known in the art, no longer go to live in the household of one's in-laws on getting married herein
State.
The multiple hard contacts 22 arranged in array are installed on the back side of aging daughter board 20, wherein, multiple hard contacts
The pin 31 that 22 part installs chip to be tested 30 with chip installation portion 21 is electrically connected with, another part and aging daughter board
Peripheral applications circuit on 20 fronts is electrically connected with；Fig. 4 and Fig. 5 shown when installing chip to be tested in paster mode, metal
Contact 22 and the pin 31 of chip to be tested 30 and the connection of peripheral applications circuit.In the present embodiment, hard contact 22
Be made up of the good metal alloy compositions of contact performance, such as craft of gilding nickel billon or other be difficult oxide alloy material.
Aging daughter board 20 is installed on when on the station 11 of universal burn-in motherboard 10, the contact pin 111 on station 11 with it is aging
The hard contact 22 at the back side of daughter board 20 matches and is in contact, so as to aging daughter board 20 is accessed into universal burn-in motherboard 10.Specifically
In embodiment, contact pin 111 is adopted as spring needle；Advantage using spring needle is：Both an oxidation can have been avoided contact with and has caused to connect
Touching bad, the spring needle of this single-point can be rapidly changed, so that the use of universal burn-in motherboard when there is single-point damage again
Life-span is significantly increased, and maintenance cost is greatly reduced.
As shown in fig. 6, all of peripheral applications circuit is to be tested with what chip installation portion 21 was installed on aging daughter board 20
Between chip 30, it is electrically connected with by 0 Ohmic resistance 23.After degradation terminates, it is possible to use high temperature flatiron tip-off goes
Fall 0 Ohmic resistance, realize being disconnected quickly, without damage by the peripheral applications circuit on aging daughter board 20 and chip to be tested 30.
Test device of the invention also includes that a chip connects socket 40, and the aging daughter board 20 for grafting after aging is with general
Chip access performance tester after aging carries out performance test；As shown in Figure 7 and Figure 8, chip connection socket 40 include with
Socket 41 and socket cover 42 that performance testing apparatus are connected, are provided with test board 411, on test board 411 on socket 41
Be provided with array arrange multiple spring needles 412, will be aging after aging daughter board 20 be installed on chip connection socket 40 when, test
Spring needle 412 on plate 411 matches and is in contact with the hard contact 22 at the back side of aging daughter board 20, after will be aging
Chip access performance tester.When aging daughter board 20 is plugged in into chip connection socket 40, by the back side of aging daughter board 20
Be input into for the test signal of performance testing apparatus by the hard contact 22 being connected with chip, and performance survey is carried out to the chip after aging
Examination, without developing a set of testing scheme again again, directly tests journey using the existing volume production of performance testing apparatus general at present
Sequence, it is to avoid the waste of huge financial resources, material resources and manpower.
Correspondingly, a kind of IC chip dynamic aging method of testing based on mother baby plate, comprises the following steps：
（1）For the chip to be tested of different types, matched peripheral applications circuit is being integrated in aging daughter board just
Face；And hard contact array is installed at the back side of aging daughter board；
（2）Chip to be tested is installed on the chip installation portion of aging daughter board, and by the pin and peripheral applications of chip to be tested
Circuit is electrically connected with corresponding hard contact respectively；
（3）The aging daughter board with chip to be tested is installed on the station of universal burn-in motherboard；
（4）Universal burn-in motherboard is connected with degradation board, the old of degradation board is introduced with by aging daughter board
Change drive signal, carry out hot and humid dynamic aging test；
（5）After degradation terminates, aging daughter board is removed from universal burn-in motherboard, and by the peripheral applications on aging daughter board
Circuit with it is aging after chip disconnect；
（6）Aging daughter board with aging rear chip is connected with performance testing apparatus, with by the gold at the aging daughter board back side
Category contact introduces the test signal of performance testing apparatus, carries out performance test.
According to the teaching of the present embodiment, those skilled in the art are capable of achieving in other scope of the present invention completely
Technical scheme.
Claims (10)
1. a kind of IC chip ageing tester based on mother baby plate, it is characterised in that the device includes universal burn-in
Motherboard（10）With multiple aging daughter boards（20）；
Universal burn-in motherboard（10）It is provided with multiple stations（11）, golden finger interface（12）And power interface（13）, station（11）
On be provided with array arrange multiple contact pins（111）, golden finger interface（12）For being connected with degradation board；
Aging daughter board（20）It is mountable to universal burn-in motherboard（10）A station（11）On, its front is provided with chip installation portion
（21）And peripheral applications circuit is integrated with, chip to be tested is installed on chip installation portion（21）, peripheral applications circuit and chip are pacified
Dress portion（21）The chip to be tested installed matches；
Aging daughter board（20）The back side on be provided with array arrange multiple hard contacts（22）, wherein, multiple hard contacts
（22）A part and chip installation portion（21）The pin electric connection of chip to be tested, another part and aging daughter board are installed
（20）Peripheral applications circuit on front is electrically connected with；
Station（11）On contact pin（111）With aging daughter board（20）The hard contact at the back side（22）Match and be in contact, so that
By aging daughter board（20）Access universal burn-in motherboard（10）.
2. test device according to claim 1, it is characterised in that：The contact pin（111）It is spring needle.
3. test device according to any one of claim 1 to 3, it is characterised in that：Chip to be tested is in paster mode
It is installed on aging daughter board（20）On chip installation portion（21）.
4. test device according to any one of claim 1 to 3, it is characterised in that：Chip to be tested is with inserting mode
It is installed on aging daughter board（20）On chip installation portion（21）, the chip installation portion（21）It is provided with one to be tested for grafting
The chip carrier socket of chip.
5. test device according to any one of claim 1 to 3, it is characterised in that：The aging daughter board（20）Upper institute
Some peripheral applications circuits and chip installation portion（21）Between the chip to be tested installed, electrically connected by 0 Ohmic resistance
Connect.
6. test device according to any one of claim 1 to 3, it is characterised in that：The device also connects including a chip
Combination hub（40）, chip connection socket（40）Including a socket（41）, socket（41）On test board is installed（411）, survey
Test plate (panel)（411）It is provided with the multiple spring needles arranged in array（412）, spring needle（412）With aging daughter board（20）The gold at the back side
Category contact（22）Match and be in contact, so that the chip access performance tester after just aging.
7. test device according to claim 1, it is characterised in that：The aging daughter board（20）It is solid by bolt, nut
Due to universal burn-in motherboard（10）, aging daughter board（20）It is provided with the through hole passed through for bolt（24）.
8. a kind of IC chip ageing testing method based on mother baby plate, comprises the following steps：
（1）For the chip to be tested of different types, matched peripheral applications circuit is being integrated in aging daughter board just
Face；And hard contact array is installed at the back side of aging daughter board；
（2）Chip to be tested is installed on the chip installation portion of aging daughter board, and by the pin and peripheral applications of chip to be tested
Circuit is connected with corresponding hard contact respectively；
（3）The aging daughter board with chip to be tested is installed on the station of universal burn-in motherboard；
（4）Universal burn-in motherboard is connected with degradation board, the old of degradation board is introduced with by aging daughter board
Change drive signal, carry out hot and humid dynamic aging test；
（5）After degradation terminates, aging daughter board is removed from universal burn-in motherboard, and by the peripheral applications on aging daughter board
Circuit with it is aging after chip disconnect；
（6）Aging daughter board with aging rear chip is connected with performance testing apparatus, with by the gold at the aging daughter board back side
Category contact introduces the test signal of performance testing apparatus, carries out performance test.
9. method of testing according to claim 8, it is characterised in that：All of peripheral applications circuit on the aging daughter board
Between the chip to be tested installed with chip installation portion, it is electrically connected with by 0 Ohmic resistance；Through the step（4）It is aging
After experiment, 0 Ohmic resistance is removed using high temperature flatiron tip-off, peripheral applications circuit is disconnected with chip.
10. method of testing according to claim 8, it is characterised in that：The step（6）In, with aging rear chip
Aging daughter board connects socket and is connected with performance testing apparatus by a chip；Chip connection socket includes a socket, socket
Test board is installed, test board is provided with the multiple spring needles arranged in array on body, the gold at spring needle and the aging daughter board back side
Category contact matches and is in contact, so that the chip access performance tester after will be aging.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710135630.3A CN106771987B (en) | 2017-03-08 | 2017-03-08 | Integrated circuit chip burn-in test device and test method based on sub-mother board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710135630.3A CN106771987B (en) | 2017-03-08 | 2017-03-08 | Integrated circuit chip burn-in test device and test method based on sub-mother board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106771987A true CN106771987A (en) | 2017-05-31 |
| CN106771987B CN106771987B (en) | 2023-08-22 |
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| CN201710135630.3A Active CN106771987B (en) | 2017-03-08 | 2017-03-08 | Integrated circuit chip burn-in test device and test method based on sub-mother board |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107328962A (en) * | 2017-08-16 | 2017-11-07 | 常州市武进区半导体照明应用技术研究院 | A kind of LED β types metal clips combined type aging clamp |
| CN109765481A (en) * | 2018-12-29 | 2019-05-17 | 西安智多晶微电子有限公司 | A kind of test board of the CPLD chip based on FPGA/MCU |
| CN109782161A (en) * | 2018-12-26 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | The debugging circuit board and its adjustment method of anti-fuse FPGA |
| CN109975691A (en) * | 2019-03-29 | 2019-07-05 | 成都天奥技术发展有限公司 | Integrated circuit universal burn-in experimental rig |
| CN110058146A (en) * | 2019-05-22 | 2019-07-26 | 西安太乙电子有限公司 | It is a kind of to change the mold general aging test device and its operating method |
| CN112666223A (en) * | 2019-12-19 | 2021-04-16 | 深圳硅基仿生科技有限公司 | Electrode aging test device |
| CN112798825A (en) * | 2020-12-29 | 2021-05-14 | 北京无线电计量测试研究所 | Aging performance test fixture for ultrahigh fundamental frequency crystal oscillator |
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| CN113438799A (en) * | 2021-06-28 | 2021-09-24 | 海光信息技术股份有限公司 | Aging circuit board, aging test structure and aging test method |
| CN113918495A (en) * | 2021-10-11 | 2022-01-11 | 北京小米移动软件有限公司 | Power supply daughter board |
| CN114076859A (en) * | 2020-08-18 | 2022-02-22 | 中国科学院国家空间科学中心 | Full-temperature aging test system and method for core components for aerospace |
| CN114323379A (en) * | 2020-09-30 | 2022-04-12 | 矽磐微电子(重庆)有限公司 | Thrust test fixture and chip mounting thrust test method |
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| CN115932536A (en) * | 2022-11-17 | 2023-04-07 | 珠海妙存科技有限公司 | Chip switching test device, circuit board and method |
| CN117590206A (en) * | 2024-01-19 | 2024-02-23 | 北京芯可鉴科技有限公司 | Adjustable chip test board and chip test method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5534786A (en) * | 1994-10-14 | 1996-07-09 | Co-Operative Facility For Aging Tester Development | Burn-in and test method of semiconductor wafers and burn-in boards for use in semiconductor wafer burn-in tests |
| CN102539984A (en) * | 2012-01-13 | 2012-07-04 | 深圳市江波龙电子有限公司 | Mass production tester and mass production aging test system |
| CN204495961U (en) * | 2015-03-02 | 2015-07-22 | 山东盛品电子技术有限公司 | A kind of aging board chip testing plate |
| CN206546416U (en) * | 2017-03-08 | 2017-10-10 | 上海鑫匀源科技有限公司 | A kind of IC chip ageing tester based on mother baby plate |
-
2017
- 2017-03-08 CN CN201710135630.3A patent/CN106771987B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5534786A (en) * | 1994-10-14 | 1996-07-09 | Co-Operative Facility For Aging Tester Development | Burn-in and test method of semiconductor wafers and burn-in boards for use in semiconductor wafer burn-in tests |
| CN102539984A (en) * | 2012-01-13 | 2012-07-04 | 深圳市江波龙电子有限公司 | Mass production tester and mass production aging test system |
| CN204495961U (en) * | 2015-03-02 | 2015-07-22 | 山东盛品电子技术有限公司 | A kind of aging board chip testing plate |
| CN206546416U (en) * | 2017-03-08 | 2017-10-10 | 上海鑫匀源科技有限公司 | A kind of IC chip ageing tester based on mother baby plate |
Non-Patent Citations (1)
| Title |
|---|
| 朱卫良;: "集成电路动态老化新技术的实施" * |
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| CN107328962A (en) * | 2017-08-16 | 2017-11-07 | 常州市武进区半导体照明应用技术研究院 | A kind of LED β types metal clips combined type aging clamp |
| CN107328962B (en) * | 2017-08-16 | 2019-11-19 | 常州市武进区半导体照明应用技术研究院 | A kind of LED β type metal clips combined type aging clamp |
| CN109782161A (en) * | 2018-12-26 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | The debugging circuit board and its adjustment method of anti-fuse FPGA |
| CN109765481A (en) * | 2018-12-29 | 2019-05-17 | 西安智多晶微电子有限公司 | A kind of test board of the CPLD chip based on FPGA/MCU |
| CN109975691A (en) * | 2019-03-29 | 2019-07-05 | 成都天奥技术发展有限公司 | Integrated circuit universal burn-in experimental rig |
| CN110058146A (en) * | 2019-05-22 | 2019-07-26 | 西安太乙电子有限公司 | It is a kind of to change the mold general aging test device and its operating method |
| CN112666223A (en) * | 2019-12-19 | 2021-04-16 | 深圳硅基仿生科技有限公司 | Electrode aging test device |
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| CN113438799B (en) * | 2021-06-28 | 2022-10-25 | 海光信息技术股份有限公司 | Aging circuit board, aging test structure and aging test method |
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| CN117590206A (en) * | 2024-01-19 | 2024-02-23 | 北京芯可鉴科技有限公司 | Adjustable chip test board and chip test method |
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