CN109782161A - The debugging circuit board and its adjustment method of anti-fuse FPGA - Google Patents
The debugging circuit board and its adjustment method of anti-fuse FPGA Download PDFInfo
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- CN109782161A CN109782161A CN201811598706.7A CN201811598706A CN109782161A CN 109782161 A CN109782161 A CN 109782161A CN 201811598706 A CN201811598706 A CN 201811598706A CN 109782161 A CN109782161 A CN 109782161A
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Abstract
The invention discloses a kind of debugging circuit board of anti-fuse FPGA and its adjustment methods, wherein the debugging circuit board of the anti-fuse FPGA, comprising: anti-fuse FPGA application extension plate is welded with multiple double contact pins thereon；Anti-fuse FPGA expansion board, bottom surface is welded with multiple double sockets corresponding with multiple double contact pins, and top surface is welded with antifuse extension seat, and antifuse extension seat is for shelving anti-fuse FPGA to be debugged.The present invention is realized by double contact pin and double socket connect and debug before the debugging of anti-fuse FPGA application extension plate and anti-fuse FPGA expansion board between the two after separate, therefore, both it is not necessarily to tip-off anti-fuse FPGA expansion board, without using mother daughter board connector, to both improve the quality of anti-fuse FPGA application extension plate after debugging rate and debugging, also the volume of anti-fuse FPGA application extension plate after debugging is caused more to minimize, to meet the development trend that space loading development increasingly minimizes.
Description
Technical field
The present invention relates to the debugging circuit boards and its debugging of technical field of integrated circuits more particularly to a kind of anti-fuse FPGA
Method.
Background technique
In the development process of space loading, for the reliability for guaranteeing design circuit, prevent Space Radiation Effects to execution
Task impacts, in the control circuit of certain crucial load, frequently with anti-fuse FPGA (Field-Programmable
Gate Array) it is used as programmable logic device, realize required combinational logic and sequential logic.
Anti-fuse FPGA is CQFP encapsulation, and pin makes in the surrounding of chip frequently with anti-fuse FPGA is welded on circuit
With the mode of the corresponding antifuse extension seat of model, the anti-fuse FPGA of the different editions of programming is put into antifuse extension seat
It is tested.After program validation final version, the antifuse extension seat of welding is subjected to tip-off, then by the final version of programming success
This anti-fuse FPGA carries out falling weldering processing.
But due to welding FPGA extension seat on FPGA pad, the later period needs to carry out tip-off dismounting processing, has damage
A possibility that FPGA pad.In order to solve the technical problem, existing mode are as follows: will be controlled to all relevant IO of anti-fuse FPGA
Signal processed is individually drawn, and space layout mother daughter board connector is found outside FPGA pad, then connect antifuse by mother daughter board connector
Expansion board welds antifuse extension seat in antifuse expansion board, only needs tip-off mother daughter board connector after the completion of debugging final in this way,
FPGA pad will not be damaged.
But with the development trend that space loading development increasingly minimizes, density of the space flight circuit in design is got over
Come it is higher, on FPGA pad extend mother daughter board connector be no longer satisfied miniature requirement.
Summary of the invention
The purpose of the present invention is to provide a kind of debugging circuit board of anti-fuse FPGA and its adjustment methods, direct to solve
Tip-off antifuse extension seat, damages anti-fuse FPGA application extension plate and space loading is developed miniature requirement and is not able to satisfy
The technical issues of.
To solve the above-mentioned problems, the present invention provides a kind of debugging circuit boards of anti-fuse FPGA comprising:
Anti-fuse FPGA application extension plate is welded with multiple double contact pins thereon；
Anti-fuse FPGA expansion board, bottom surface are welded with multiple double sockets corresponding with multiple double contact pins, and top surface
It is welded with antifuse extension seat, antifuse extension seat is for shelving anti-fuse FPGA to be debugged.
As a further improvement of the present invention, multiple double contact pins expand according to default be arranged in anti-fuse FPGA application
In the default rectangular area of panel；Multiple double sockets are according to the default default rectangle being arranged in anti-fuse FPGA expansion board
In region.
As a further improvement of the present invention, the number of multiple double contact pins is 8, and 8 double contact pins are according to " rice " word
Type is arranged in the default rectangular area of anti-fuse FPGA application extension plate；The number of multiple double sockets is 8,8
Double socket is arranged according to " rice " font in the default rectangular area of anti-fuse FPGA expansion board.
As a further improvement of the present invention, the spacing between the successive pins of each double contact pin is 1.20-
1.30mm；Spacing between the adjacent outlet of each double socket is 1.20-1.30mm.
To solve the above-mentioned problems, the present invention also provides a kind of adjustment methods of anti-fuse FPGA comprising following step
It is rapid:
By the double socket of the double contact pin insertion anti-fuse FPGA expansion board of anti-fuse FPGA application extension plate；
The anti-fuse FPGA to be debugged of different editions is successively held on to the antifuse extension seat of anti-fuse FPGA expansion board
It is interior, and the anti-fuse FPGA to be debugged of each version is tested；
Confirm the anti-fuse FPGA of final version, and by the double contact pin of anti-fuse FPGA application extension plate from antifuse
It is extracted in the double socket of FPGA expansion board；
The anti-fuse FPGA of final version is soldered on anti-fuse FPGA application extension plate.
As a further improvement of the present invention, the double contact pin of anti-fuse FPGA application extension plate is inserted into anti-fuse FPGA
The double socket of expansion board, before step, further includes:
In welding multiple double contact pins on anti-fuse FPGA application extension plate；
In the welding of the bottom surface of anti-fuse FPGA expansion board and multiple double matched multiple double sockets of contact pin, and Yu Fanrong
Weld an antifuse extension seat in the top surface of silk FPGA expansion board.
As a further improvement of the present invention, multiple double contact pins expand according to default be arranged in anti-fuse FPGA application
In the default rectangular area of panel；Multiple double sockets are according to the default default rectangle being arranged in anti-fuse FPGA expansion board
In region.
As a further improvement of the present invention, the number of multiple double contact pins is 8, and 8 double contact pins are according to " rice " word
Type is arranged in the default rectangular area of anti-fuse FPGA application extension plate；The number of multiple double sockets is 8,8
Double socket is arranged according to " rice " font in the default rectangular area of anti-fuse FPGA expansion board.
As a further improvement of the present invention, the spacing between the successive pins of each double contact pin is 1.20-
1.30mm；Spacing between the adjacent outlet of each double socket is 1.20-1.30mm.
As a further improvement of the present invention, the anti-fuse FPGA of final version is soldered to anti-fuse FPGA application extension
On plate, before step, further includes:
Double contact pin under the conditions of insulating protection, on tip-off anti-fuse FPGA application extension plate.
Compared with prior art, the present invention by double contact pin and double socket realize anti-fuse FPGA application extension plate with
It separates after connecting and debug before the debugging of anti-fuse FPGA expansion board between the two, therefore, both expanded without tip-off anti-fuse FPGA
Panel, without mother daughter board connector is used, to both improve anti-fuse FPGA application extension plate after debugging rate and debugging
Quality, also cause the volume of anti-fuse FPGA application extension plate after debugging more to minimize, got over meeting space loading development
Come the development trend more minimized.
Detailed description of the invention
Fig. 1 is the debugging overall structure diagram of debugging circuit board one embodiment of anti-fuse FPGA of the present invention；
Fig. 2 is the electricity of anti-fuse FPGA application extension plate one embodiment in the debugging circuit board of anti-fuse FPGA of the present invention
Road schematic illustration；
Fig. 3 is that the circuit of anti-fuse FPGA expansion board one embodiment in the debugging circuit board of anti-fuse FPGA of the present invention is former
Manage schematic diagram；
Fig. 4 is the flow diagram of adjustment method one embodiment of anti-fuse FPGA of the present invention；
Fig. 5 is the flow diagram of second embodiment of adjustment method of anti-fuse FPGA of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, is clearly and completely retouched to the technical solution in embodiment
It states, similar reference numerals represent similar component in attached drawing.Obviously, will be described below embodiment is only the present invention one
Divide embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making
Every other embodiment obtained, shall fall within the protection scope of the present invention under the premise of creative work.
Fig. 1 illustrates one embodiment of the debugging circuit board of anti-fuse FPGA of the present invention.In the present embodiment, such as Fig. 1
Shown, the debugging circuit board of the anti-fuse FPGA includes anti-fuse FPGA application extension plate 1 and anti-fuse FPGA expansion board 2.
Wherein, multiple double contact pins 10 are welded on anti-fuse FPGA application extension plate 1.2 bottom of anti-fuse FPGA expansion board
Face is welded with multiple double socket (not shown)s corresponding with multiple double contact pins 10, and top surface is welded with antifuse extension
Seat 20, antifuse extension seat 20 is for shelving anti-fuse FPGA 21 to be debugged.
It should be noted that the anti-fuse FPGA to be debugged 21 in the present embodiment can be the antifuse of ACLEL company
A54SX72A-PQ208。
The present embodiment realizes that anti-fuse FPGA application extension plate and anti-fuse FPGA expand by double contact pin and double socket
It is separated after connecting and debug before the debugging of panel between the two, therefore, tip-off anti-fuse FPGA expansion board is both not necessarily to, without making
Also caused with mother daughter board connector to both improve the quality of anti-fuse FPGA application extension plate after debugging rate and debugging
The volume of anti-fuse FPGA application extension plate more minimizes after debugging, to meet the hair that space loading development increasingly minimizes
Exhibition trend.
On the basis of the above embodiments, in other embodiments, referring to fig. 2, multiple double contact pins 10 are according to default arrangement
It is set in the default rectangle region 100 of anti-fuse FPGA application extension plate 1；Referring to Fig. 3, multiple double sockets are according to default arrangement
It is set in the default rectangular area 200 of anti-fuse FPGA expansion board 2.
Further, the spacing between the successive pins of each double contact pin 10 is 1.20-1.30mm, it is preferable that every
Spacing between the successive pins of one double contact pin 10 is 1.27mm；Spacing between the adjacent outlet of each double socket
For 1.20-1.30mm, the spacing between the adjacent outlet of each double socket is 1.27mm.
It should be noted that determining that addition is double according to the extension IO number of the required anti-fuse FPGA of application in the present embodiment
The number of contact pin.The double contact pin of different numbers uses different arrangement modes, for technology of the invention detailed further
Scheme illustrates this case by taking 6 double contact pins and 8 double contact pins as an example.
If 1, the number of multiple double contact pins 10 is 6, Yu Fanrong is arranged according to " * " font in 6 double contact pins 10
In the default rectangular area 100 of silk FPGA application extension plate 1；The number of multiple double sockets be 8,8 double sockets according to
" * " font is arranged in the default rectangular area 200 of anti-fuse FPGA expansion board 2.
2, the number of multiple double contact pins 10 is 8, and 8 double contact pins 10 are arranged according to " rice " font in antifuse
In the default rectangular area of FPGA application extension plate 1；The number of multiple double sockets is 8, and 8 double sockets are according to " rice " word
Type is arranged in the default rectangular area of anti-fuse FPGA expansion board 2.
It should be noted that if be anti-fuse FPGA application extension plate 1, it is double when anti-fuse FPGA application extension plate 1 is routed
The wiring of the outer other electronic component connection signals of socket needle, it should be noted that avoid default rectangular area 100, the default rectangle region
Domain 100 is for completing double contact pin wiring.
Further, the network label of double contact pin distribution can have serious crossing instances, therefore need to be to double contact pin
Network label be adjusted；According to 1 installation scenarios of anti-fuse FPGA application extension plate, according to anti-fuse FPGA application extension plate
1 I/O signal determines the connection number of pins of double contact pin, then after changing in Fig. 2 the contact for being correspondingly connected with device, carries out more to netlist
Newly.After adjusting netlist, the crossing instances of signal are resolved between double contact pin, at this time achievable anti-fuse FPGA application extension plate
The wiring of 1 double contact pin.
If anti-fuse FPGA expansion board 2, when anti-fuse FPGA expansion board 2 is routed, the outer other electronics members of double socket
The wiring of device connection signal, it should be noted that avoid default rectangular area 200, the default rectangular area 200 is for completing double insert
Seat wiring.
Further, since anti-fuse FPGA expansion board 2 is corresponding with anti-fuse FPGA application extension 1 signal of plate consistent, no
Need to adjust netlist again, and signal will not intersect, signal routing situation is similar with anti-fuse FPGA application extension plate 1, herein not
It repeats again.
Fig. 4 illustrates one embodiment of the adjustment method of anti-fuse FPGA of the present invention.In the present embodiment, such as Fig. 4 institute
Show, the adjustment method of the anti-fuse FPGA includes the following steps:
S1, by the double socket of the double contact pin insertion anti-fuse FPGA expansion board of anti-fuse FPGA application extension plate.
On the basis of the present embodiment, in other embodiments, referring to Fig. 5, before step S1, further includes:
S10, in welding multiple double contact pins on anti-fuse FPGA application extension plate.
In the present embodiment, multiple double contact pins are arranged according to default in the default of anti-fuse FPGA application extension plate
In rectangular area.
It should be noted that determining that addition is double according to the extension IO number of the required anti-fuse FPGA of application in the present embodiment
The number of contact pin.The double contact pin of different numbers uses different arrangement modes.The best illustration of the present embodiment are as follows: multiple double
The number of contact pin is 8, and 8 double contact pins are arranged according to " rice " font in the default square of anti-fuse FPGA application extension plate
In shape region.
Further, the spacing between the successive pins of each double contact pin is 1.20-1.30mm；Preferably, each
Spacing between the successive pins of a double contact pin is 1.27mm.
S11, in the welding of the bottom surface of anti-fuse FPGA expansion board and multiple double matched multiple double sockets of contact pin, and in
Weld an antifuse extension seat in the top surface of anti-fuse FPGA expansion board.
In the present embodiment, multiple double sockets are according to the default default rectangle being arranged in anti-fuse FPGA expansion board
In region.
It should be noted that determining that addition is double according to the extension IO number of the required anti-fuse FPGA of application in the present embodiment
The number of socket.The double socket of different numbers uses different arrangement modes.The best illustration of the present embodiment are as follows: multiple double
The number of socket is 8, and the default rectangle region in anti-fuse FPGA expansion board is arranged according to " rice " font for 8 double sockets
In domain.
Further, the spacing between the adjacent outlet of each double socket is 1.20-1.30mm, it is preferable that each
Spacing between the adjacent outlet of a double socket is 1.27mm.
S2 extends the antifuse that the anti-fuse FPGA to be debugged of different editions is successively held on anti-fuse FPGA expansion board
In seat, and the anti-fuse FPGA to be debugged of each version is tested.
S3 confirms the anti-fuse FPGA of final version, and the double contact pin of anti-fuse FPGA application extension plate is melted from anti-
It is extracted in the double socket of silk FPGA expansion board.
The anti-fuse FPGA of final version is soldered on anti-fuse FPGA application extension plate by S4.
On the basis of the present embodiment, in other embodiments, referring to fig. 4, before step S4, further includes:
Step S30, double contact pin under the conditions of insulating protection, on tip-off anti-fuse FPGA application extension plate.
For the present embodiment under the conditions of insulating protection, the double contact pin of tip-off will not damage anti-fuse FPGA application extension plate.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present application constitutes any limit
It is fixed.
The specific embodiment of invention is described in detail above, but it is only used as example, the present invention is not intended to limit
With specific embodiments described above.For a person skilled in the art, any equivalent modifications that the invention is carried out
Or substitute also all among scope of the invention, therefore, the made equalization in the case where not departing from the spirit and principles in the present invention range
Transformation and modification, improvement etc., all should be contained within the scope of the invention.
Claims (10)
1. a kind of debugging circuit board of anti-fuse FPGA, characterized in that it comprises:
Anti-fuse FPGA application extension plate is welded with multiple double contact pins thereon；
Anti-fuse FPGA expansion board, bottom surface are welded with multiple double sockets corresponding with the multiple double contact pin, and top surface
It is welded with antifuse extension seat, the antifuse extension seat is for shelving anti-fuse FPGA to be debugged.
2. the debugging circuit board of anti-fuse FPGA according to claim 1, which is characterized in that the multiple double contact pin is pressed
It is arranged according to default in the default rectangular area of the anti-fuse FPGA application extension plate；The multiple double socket according to
Described preset is arranged in the default rectangular area of the anti-fuse FPGA expansion board.
3. the debugging circuit board of anti-fuse FPGA according to claim 2, which is characterized in that the multiple double contact pin
Number is 8, and 8 double contact pins are arranged according to " rice " font in the default rectangle of the anti-fuse FPGA application extension plate
In region；The number of the multiple double socket is 8, and 8 double sockets are arranged according to " rice " font in described anti-molten
In the default rectangular area of silk FPGA expansion board.
4. the debugging circuit board of anti-fuse FPGA according to claim 1, which is characterized in that the phase of each double contact pin
Spacing between adjacent contact pin is 1.20-1.30mm；Spacing between the adjacent outlet of each double socket is 1.20-
1.30mm。
5. a kind of adjustment method of anti-fuse FPGA, which is characterized in that it includes the following steps:
By the double socket of the double contact pin insertion anti-fuse FPGA expansion board of anti-fuse FPGA application extension plate；
The anti-fuse FPGA to be debugged of different editions is successively held on to the antifuse extension seat of the anti-fuse FPGA expansion board
It is interior, and the anti-fuse FPGA to be debugged of each version is tested；
Confirm the anti-fuse FPGA of final version, and the double contact pin of the anti-fuse FPGA application extension plate is instead melted from described
It is extracted in the double socket of silk FPGA expansion board；
The anti-fuse FPGA of the final version is soldered on the anti-fuse FPGA application extension plate.
6. the adjustment method of anti-fuse FPGA according to claim 5, which is characterized in that described by anti-fuse FPGA application
The double socket of the double contact pin insertion anti-fuse FPGA expansion board of expansion board, before step, further includes:
In welding multiple double contact pins on the anti-fuse FPGA application extension plate；
In the welding of the bottom surface of the anti-fuse FPGA expansion board and the multiple double matched multiple double sockets of contact pin, and in
Weld an antifuse extension seat in the top surface of the anti-fuse FPGA expansion board.
7. the adjustment method of anti-fuse FPGA according to claim 6, which is characterized in that the multiple double contact pin according to
It is default to be arranged in the default rectangular area of the anti-fuse FPGA application extension plate；The multiple double socket is according to institute
State default be arranged in the default rectangular area of the anti-fuse FPGA expansion board.
8. the adjustment method of anti-fuse FPGA according to claim 7, which is characterized in that of the multiple double contact pin
Number is 8, and 8 double contact pins are arranged according to " rice " font in the default rectangle region of the anti-fuse FPGA application extension plate
In domain；The number of the multiple double socket is 8, and 8 double sockets are arranged according to " rice " font in the antifuse
In the default rectangular area of FPGA expansion board.
9. the adjustment method of anti-fuse FPGA according to claim 5, which is characterized in that each double contact pin it is adjacent
Spacing between contact pin is 1.20-1.30mm；Spacing between the adjacent outlet of each double socket is 1.20-1.30mm.
10. the adjustment method of anti-fuse FPGA according to claim 5, which is characterized in that described by the final version
Anti-fuse FPGA be soldered on the anti-fuse FPGA application extension plate, before step, further includes:
Double contact pin under the conditions of insulating protection, on anti-fuse FPGA application extension plate described in tip-off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811598706.7A CN109782161A (en) | 2018-12-26 | 2018-12-26 | The debugging circuit board and its adjustment method of anti-fuse FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811598706.7A CN109782161A (en) | 2018-12-26 | 2018-12-26 | The debugging circuit board and its adjustment method of anti-fuse FPGA |
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| Publication Number | Publication Date |
|---|---|
| CN109782161A true CN109782161A (en) | 2019-05-21 |
Family
ID=66498378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811598706.7A Pending CN109782161A (en) | 2018-12-26 | 2018-12-26 | The debugging circuit board and its adjustment method of anti-fuse FPGA |
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| CN (1) | CN109782161A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111123082A (en) * | 2019-10-30 | 2020-05-08 | 北京空间机电研究所 | Small-size three-dimensional antifuse Field Programmable Gate Array (FPGA) online debugging and verifying method |
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Application publication date: 20190521 |
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