CN202352954U - Central processing unit (CPU) socket based structure for achieving detachability of field programmable gata array (FPGA) - Google Patents
Central processing unit (CPU) socket based structure for achieving detachability of field programmable gata array (FPGA) Download PDFInfo
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- CN202352954U CN202352954U CN2011205150971U CN201120515097U CN202352954U CN 202352954 U CN202352954 U CN 202352954U CN 2011205150971 U CN2011205150971 U CN 2011205150971U CN 201120515097 U CN201120515097 U CN 201120515097U CN 202352954 U CN202352954 U CN 202352954U
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- fpga
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- cpu
- detachability
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- 238000000034 method Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
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Abstract
The utility model provides a CPU socket based structure for achieving detachability of FPGA. The structure comprises an FPGA chip which is soldered on the front surface of a printed circuit board (PCB) plug board. The PCB plug board is adjustably plugged into the CPU socket, a pin pad corresponding to pins of the FPGA chip is disposed on the front surface of the PCB plug board. Pin contacts are positioned on the back surface of the PCB plug board. The pin contacts correspond to pins of the CUP socket. Compared with the prior art, the CPU socket based structure for achieving detachability of FPGA has the advantages of reasonable design, simple structure, skillful conception, convenience in utilization, mounting and dismounting, easiness to implement and capabilities of effectively improving market competitiveness of products and reducing production cost of products.
Description
Technical field
The utility model relates to a kind of locate mode of fpga chip, a kind of specifically simple in structure, realize the dismountable structure of FPGA based on the CPU slot.
Background technology
In design of computer hardware, often use fpga chip.The method that fpga chip is installed at present is that fpga chip directly is welded on the hardware platform.A very big shortcoming---fpga chip and platform are integrated inseparable in this method existence.This means no matter be fpga chip or platform, only have a side to be damaged, the opposing party also can not reuse.Can know that according to engineering practice the impaired probability of platform is big more a lot of than fpga chip.So for some expensive large-scale fpga chips, we need try every possible means itself and hardware platform are separated, it is dismountable to let its installation become, and can significantly lower the R&D costs based on this type chip like this.
Summary of the invention
The technical assignment of the utility model is the deficiency that solves prior art, provide a kind of simple in structure, realize the dismountable structure of FPGA based on the CPU slot.
The technical scheme of the utility model realizes by following mode; This is a kind of, and its structure comprises fpga chip based on the dismountable structure of CPU slot realization FPGA, and said fpga chip is welded on the front of PCB keyset; This PCB keyset is active to be plugged in the CPU slot; The front of above-mentioned PCB keyset is provided with and the corresponding contact pin pad of fpga chip pin, and the back side of said PCB keyset is provided with pin contact, and this pin contact is corresponding with the pin pin of CPU slot.
Said CPU slot is welded on the system platform.
The utility model beneficial effect is:
The utility model a kind of based on the CPU slot realize the dismountable structure of FPGA have simple in structure, easy to use, characteristics such as be skillfully constructed; The utility model can be used for about FPGA validation test field; Increase the reusability of fpga chip, thereby reduce the chip risk cost; The fpga chip easy installation and removal of the utility model is easy to realize, can effectively strengthen the competitiveness of product in market, reduces production cost of products.
Description of drawings
Accompanying drawing 1 is the structural representation of the utility model.
Accompanying drawing 2 is keyset side structure sketch mapes of the utility model.
Mark in the accompanying drawing is represented respectively:
1, fpga chip, 2, the PCB keyset, 3, system platform, 4, the CPU slot, 5, the contact pin pad, 6, pin contact.
Embodiment
Below in conjunction with accompanying drawing a kind of of the utility model realized that based on the CPU slot the dismountable structure of FPGA specifies below doing.
Like accompanying drawing 1, shown in Figure 2; This is a kind of, and its structure comprises fpga chip 1 based on the dismountable structure of CPU slot realization FPGA, and said fpga chip 1 is welded on the front of PCB keyset 2; These PCB keyset 2 active being plugged in the CPU slot 4; The front of above-mentioned PCB keyset 2 is provided with and the corresponding contact pin pad 5 of fpga chip 1 pin, and the back side of said PCB keyset 2 is provided with pin contact 6, and this pin contact 6 is corresponding with the pin pin of CPU slot 4.
Said CPU slot 4 is welded on the system platform 3.
PCB keyset 2 connects one to one front pad and b contact through inner cabling, guarantees the proper communication between CPU slot 4 and the fpga chip 1.
Wherein for the following requirement of being designed with of keyset:
Circuit design must satisfy the design requirement of relevant FPGA chip, requires signal isometric for differential signal, clock signal etc., long process such as must do; In order to guarantee well to contact between contact and the Pin pin, PCB keyset 2 b contacts must be done consent and handle; The physical structure of PCB keyset 2 requires to satisfy CPU slot 4 constraintss, guarantees that PCB keyset 2 can successfully be placed in the CPU slot 4, and each contact can well contact with the Pin pin.
In actual use, the pressure that the deadweight of PCB keyset 2 and fpga chip 1 adds CPU slot 4 lids must satisfy the requirement of Pin pin stress, and the center point coordinate of PCB keyset 2 need align with CPU slot 4 center point coordinates in addition; Each contact, PCB keyset 2 back sides must be directed against neat with the Pin of CPU slot 4.
Claims (2)
1. realize the dismountable structure of FPGA based on the CPU slot for one kind; Its structure comprises fpga chip; It is characterized in that said fpga chip is welded on the front of PCB keyset, this PCB keyset is active to be plugged in the CPU slot, and the front of above-mentioned PCB keyset is provided with and the corresponding contact pin pad of fpga chip pin; The back side of said PCB keyset is provided with pin contact, and this pin contact is corresponding with the pin pin of CPU slot.
2. according to claim 1 a kind of based on the dismountable structure of CPU slot realization FPGA, it is characterized in that said CPU slot is welded on the system platform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205150971U CN202352954U (en) | 2011-12-12 | 2011-12-12 | Central processing unit (CPU) socket based structure for achieving detachability of field programmable gata array (FPGA) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205150971U CN202352954U (en) | 2011-12-12 | 2011-12-12 | Central processing unit (CPU) socket based structure for achieving detachability of field programmable gata array (FPGA) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202352954U true CN202352954U (en) | 2012-07-25 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205150971U Expired - Fee Related CN202352954U (en) | 2011-12-12 | 2011-12-12 | Central processing unit (CPU) socket based structure for achieving detachability of field programmable gata array (FPGA) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202352954U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616574A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | FPGA (field programmable gate array) removable high-speed operation verification development board |
| CN109782161A (en) * | 2018-12-26 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | The debugging circuit board and its adjustment method of anti-fuse FPGA |
| CN114637081A (en) * | 2020-12-16 | 2022-06-17 | 青岛海信宽带多媒体技术有限公司 | Optical module |
-
2011
- 2011-12-12 CN CN2011205150971U patent/CN202352954U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616574A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | FPGA (field programmable gate array) removable high-speed operation verification development board |
| CN109782161A (en) * | 2018-12-26 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | The debugging circuit board and its adjustment method of anti-fuse FPGA |
| CN114637081A (en) * | 2020-12-16 | 2022-06-17 | 青岛海信宽带多媒体技术有限公司 | Optical module |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120725 Termination date: 20141212 |
|
| EXPY | Termination of patent right or utility model |