CN106771987B - Integrated circuit chip burn-in test device and test method based on sub-mother board - Google Patents
Integrated circuit chip burn-in test device and test method based on sub-mother board Download PDFInfo
- Publication number
- CN106771987B CN106771987B CN201710135630.3A CN201710135630A CN106771987B CN 106771987 B CN106771987 B CN 106771987B CN 201710135630 A CN201710135630 A CN 201710135630A CN 106771987 B CN106771987 B CN 106771987B
- Authority
- CN
- China
- Prior art keywords
- chip
- aging
- burn
- test
- daughter board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 92
- 238000010998 test method Methods 0.000 title claims abstract description 8
- 230000032683 aging Effects 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 230000002093 peripheral effect Effects 0.000 claims abstract description 34
- 238000011056 performance test Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- 238000009434 installation Methods 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 4
- 229910052742 iron Inorganic materials 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002431 foraging effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to an integrated circuit chip burn-in test device and method based on a sub-motherboard, wherein the device comprises a universal burn-in motherboard and a plurality of burn-in sub-boards; the universal aging mother board is provided with a plurality of stations, and the stations are provided with a plurality of spring pins which are arranged in an array; the aging daughter board can be arranged on a station of the universal aging mother board, and the front surface of the aging daughter board is provided with a chip mounting part and is integrated with a peripheral application circuit; the back of the burn-in daughter board is provided with a plurality of metal contacts arranged in an array, wherein one part of the metal contacts is connected with pins of a chip to be tested, and the other part of the metal contacts is connected with a peripheral application circuit; the contact pin on the station is matched with and contacted with the metal contact on the back of the aging daughter board, so that the aging daughter board is connected to the universal aging mother board; a test method is also provided. The invention is suitable for the aging test and the performance test after aging of various integrated circuit chips, effectively saves the test cost and reduces the test period.
Description
Technical Field
The invention relates to the technical field of burn-in test of integrated circuit products, in particular to an integrated circuit chip burn-in test device and method based on a sub-motherboard.
Background
Before mass production, the integrated circuit chip is generally subjected to burn-in test (to ensure the service life and reliability of the chip) and performance test (mass production test of the function and performance of the chip), and the integrated circuit chip passing the above two tests can be defined as a good product. The conventional burn-in board is generally a multi-station burn-in PCB board with at least 77 stations, each station is provided with a dedicated chip socket, pins of chips to be tested are led into the burn-in PCB board, and burn-in tests with high temperature and high voltage are performed on a plurality of chips to be tested.
However, the tested chips are various, and the package types and the arrangement of the pins are different, so different burn-in boards need to be customized for different types of tested chips. The design and manufacturing cost of the existing burn-in board is high, so that the burn-in board brings high testing cost, and is more unacceptable for products with low unit price and simple testing circuit. In addition, the pre-preparation time of the customized aging test board is longer, the test period is prolonged, and the test efficiency is reduced.
Disclosure of Invention
Aiming at the defects or shortcomings of the prior art, the invention aims to provide the integrated circuit chip aging test device and the test method based on the sub-mother board, which can be suitable for carrying out aging tests and performance tests after aging on various types of integrated circuit chips on the premise of ensuring the test accuracy, thereby effectively saving the test cost and reducing the test period.
In order to solve the technical problems, the invention comprises the following components:
an integrated circuit chip burn-in test device based on a sub-motherboard comprises a universal burn-in motherboard and a plurality of burn-in sub-boards; the universal aging mother board is provided with a plurality of stations, a golden finger interface and a power interface, wherein the stations are provided with a plurality of contact pins arranged in an array, and the golden finger interface is used for being connected with an aging test machine; the burn-in daughter board can be arranged on a station of the universal burn-in motherboard, a chip mounting part is arranged on the front surface of the burn-in daughter board, a peripheral application circuit is integrated, a chip to be tested is mounted on the chip mounting part, and the peripheral application circuit is matched with the chip to be tested mounted on the chip mounting part; a plurality of metal contacts arranged in an array are arranged on the back surface of the burn-in daughter board, wherein one part of the plurality of metal contacts is electrically connected with pins of a chip to be tested which is arranged on the chip mounting part, and the other part of the plurality of metal contacts is electrically connected with a peripheral application circuit on the front surface of the burn-in daughter board; the pins on the station are matched with and contacted with the metal contacts on the back of the aging daughter board, so that the aging daughter board is connected to the universal aging mother board.
The contact pin is a spring pin.
The chip to be tested is mounted on the chip mounting part on the burn-in daughter board in a surface-mount manner.
The chip to be tested is arranged on the chip mounting part on the burn-in daughter board in a plugging manner, and a chip socket for plugging the chip to be tested is arranged on the chip mounting part.
All peripheral application circuits on the burn-in daughter board are electrically connected with the chip to be tested which is installed by the chip installation part through a resistor of 0 ohm.
The device also comprises a chip connecting socket, the chip connecting socket comprises a socket body, a test board is arranged on the socket body, a plurality of spring pins which are arranged in an array are arranged on the test board, and the spring pins are matched with and contacted with the metal contacts on the back of the aging sub-board, so that the aged chip is connected into the performance test instrument.
The aging daughter board is fixed on the universal aging mother board through bolts and nuts, and through holes for the bolts to pass through are formed in the aging daughter board.
An integrated circuit chip burn-in test method based on a sub-motherboard comprises the following steps:
(1) For different types of chips to be tested, peripheral application circuits matched with the chips to be tested are integrated on the front surface of the aging daughter board; mounting a metal contact array on the back of the aged daughter board;
(2) Mounting the chip to be tested on the chip mounting part of the burn-in daughter board, and respectively connecting pins of the chip to be tested and a peripheral application circuit with corresponding metal contacts;
(3) Mounting an aging daughter board with a chip to be tested on a station of a universal aging mother board;
(4) Connecting the universal aging motherboard with an aging test machine to introduce an aging driving signal of the aging test machine through the aging daughter board for high-temperature high-humidity dynamic aging test;
(5) After the burn-in test is finished, the burn-in daughter board is taken down from the universal burn-in motherboard, and the peripheral application circuit on the burn-in daughter board is disconnected from the burn-in chip;
(6) And connecting the aged daughter board with the aged chip with a performance testing instrument to introduce testing signals of the performance testing instrument through metal contacts on the back of the aged daughter board for performance testing.
All peripheral application circuits on the aging daughter board are electrically connected with the chip to be tested which is installed by the chip installation part through a 0 ohm resistor; after the ageing test in the step (4), the high-temperature soldering iron is used for desoldering to remove the 0 ohm resistor, so that the peripheral application circuit is disconnected from the chip.
In the step (6), the aged daughter board with the aged chip is connected with the performance testing instrument through a chip connecting socket; the chip connecting socket comprises a socket body, a test board is arranged on the socket body, a plurality of spring pins which are arranged in an array are arranged on the test board, and the spring pins are matched with and contacted with the metal contacts on the back of the aging sub-board, so that the aged chip is connected into the performance test instrument.
Compared with the prior art, the invention has the advantages that:
(1) The method comprises the steps that a child mother board structure consisting of a universal aging mother board and an aging child board is adopted, the aging child board can be installed on a station of the universal aging mother board, and a chip installation part for installing a chip to be tested on the aging child board is adopted; the aging daughter board capable of being mounted on the universal aging motherboard is changed to replace the whole aging test board in the prior art, the whole aging test board special for customizing products according to different packaging types is not needed, the test cost is greatly reduced, the test period is shortened, the test efficiency is improved, and the aging test board is very suitable for aging tests of various packaging products.
(2) The back of the burn-in daughter board is provided with a plurality of metal contacts, wherein one part of the metal contacts are connected with pins of the mounted chip to be tested, and the other part of the metal contacts are connected with a peripheral application circuit on the front of the burn-in daughter board; on one hand, the arranged metal contact is convenient to connect with the contact pin on the universal aging motherboard station; on the other hand, after the burn-in test is finished, the peripheral application circuit is disconnected from the chip, and the burn-in daughter board with the burn-in chip is connected to a performance testing instrument to rapidly test the performance of the burn-in chip.
Drawings
Fig. 1: the invention discloses a general aging master plate structure schematic diagram.
Fig. 2: the front structure of the aging daughter board in the invention is schematically shown.
Fig. 3: the back structure of the burn-in daughter board in the present invention is schematically shown.
Fig. 4: in the invention, the matching diagram of the chip to be tested and the aging daughter board is shown.
Fig. 5: the invention provides an exploded schematic diagram of an burn-in daughter board with a chip to be tested and a universal burn-in motherboard.
Fig. 6: the invention discloses a structure schematic diagram for connecting a chip to be tested in an aging daughter board with a peripheral application circuit.
Fig. 7: the structure of the chip connecting socket is schematically shown in the invention.
Fig. 8: the structure of the test board in the chip connecting socket is schematically shown.
Detailed Description
The conception, specific structure, and technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, features, and effects of the present invention.
As shown in fig. 1 to 8, a daughter-motherboard-based integrated circuit chip burn-in apparatus includes a universal burn-in motherboard 10 and a plurality of burn-in daughter boards 20.
The universal aging motherboard 10 is provided with a plurality of stations 11 for installing the aging daughter board 20, a golden finger interface 12 for connecting with an aging test machine, a power interface 13 and an LED indicator lamp, and the stations 11 are provided with a plurality of contact pins 111 arranged in an array; the golden finger 12, the power interface 13 and the LED indicator lamp are used for realizing functions of a driving module, a power supply, access of work instructions and the like of the aging test machine. In a specific embodiment, the universal burn-in motherboard 10 is a PCB board made of an epoxy material (FR 5) board that has a high service life, ensuring that the universal burn-in motherboard can be reused multiple times.
The burn-in daughter board 20 is a PCB board with a certain specification and size, and can be mounted on a station 11 of the universal burn-in motherboard 10, and is fixed on the universal burn-in motherboard 10 by bolts and nuts at the periphery, and through holes 24 for the bolts to pass through are arranged at the periphery of the burn-in daughter board 20.
The front surface of the burn-in daughter board 20 is provided with a chip mounting part 21, and is integrated with a peripheral application circuit, and a chip 30 to be tested is mounted on the chip mounting part 21; the peripheral application circuit is matched with the chip 30 to be tested mounted by the chip mounting portion 21, specifically: and integrating a peripheral application circuit for performing burn-in test on the chip according to the packaging type and pin arrangement of the mounted chip to be tested. The method for integrating the peripheral application circuit is a prior art in the field, and is not described herein.
In the invention, the chip 30 to be tested can be mounted on the chip mounting part 21 on the burn-in daughter board 20 in a surface mount mode or an inserting mode; when mounted in a plugging manner, the chip mounting portion 21 is provided with a chip socket for plugging the chip 30 to be tested. Methods for mounting chips in a patch manner and in a socket manner are well known in the art and will not be described in detail herein.
A plurality of metal contacts 22 are arranged in an array on the back of the burn-in daughter board 20, wherein one part of the plurality of metal contacts 22 is electrically connected with pins 31 of a chip 30 to be tested mounted on the chip mounting part 21, and the other part of the plurality of metal contacts is electrically connected with peripheral application circuits on the front of the burn-in daughter board 20; fig. 4 and 5 show the connection of the metal contacts 22 to the pins 31 of the chip 30 to be tested and to the peripheral application circuits when the chip to be tested is mounted in a patch-like manner. In this embodiment, the metal contacts 22 are made of a metal alloy material with good contact performance, such as nickel-gold alloy or other non-oxidizable alloy material with gold plating process.
When the burn-in daughter board 20 is mounted on the station 11 of the universal burn-in motherboard 10, the pins 111 on the station 11 mate with and contact the metal contacts 22 on the back side of the burn-in daughter board 20, thereby connecting the burn-in daughter board 20 to the universal burn-in motherboard 10. In a specific embodiment, the pin 111 is a spring pin; the advantage of using a spring needle is that: the spring needle of the single point can be quickly replaced when the single point is damaged, so that the service life of the universal aging motherboard is greatly prolonged, and the maintenance cost is greatly reduced.
As shown in fig. 6, all the peripheral application circuits on the burn-in daughter board 20 are electrically connected to the chip to be tested 30 mounted on the chip mounting portion 21 through the 0 ohm resistor 23. After the burn-in test is completed, the 0 ohm resistor can be removed by soldering with a high temperature soldering iron, so as to rapidly disconnect the peripheral application circuit on the burn-in daughter board 20 from the chip 30 to be tested without damage.
The testing device of the present invention further comprises a chip connection socket 40 for plugging the aged daughter board 20 to connect the aged chip to the performance testing instrument for performance testing; as shown in fig. 7 and 8, the chip connection socket 40 includes a socket body 41 and a socket cover 42 connected with the performance test apparatus, a test board 411 is mounted on the socket body 41, a plurality of spring pins 412 are arranged in an array on the test board 411, and when the aged daughter board 20 is mounted on the chip connection socket 40, the spring pins 412 on the test board 411 are matched with and contacted with the metal contacts 22 on the back of the aged daughter board 20, so that the aged chip is connected to the performance test apparatus. When the aging daughter board 20 is plugged into the chip connection socket 40, the test signal of the performance test instrument is input through the metal contact 22 connected with the chip on the back of the aging daughter board 20, the performance test is carried out on the aged chip, a set of test scheme is not required to be developed again, the existing mass production test program of the conventional performance test instrument is directly used, and huge financial resources, material resources and manpower waste are avoided.
Correspondingly, the dynamic burn-in test method for the integrated circuit chip based on the sub-mother board comprises the following steps:
(1) For different types of chips to be tested, peripheral application circuits matched with the chips to be tested are integrated on the front surface of the aging daughter board; mounting a metal contact array on the back of the aged daughter board;
(2) Mounting the chip to be tested on the chip mounting part of the burn-in daughter board, and electrically connecting pins of the chip to be tested and a peripheral application circuit with corresponding metal contacts respectively;
(3) Mounting an aging daughter board with a chip to be tested on a station of a universal aging mother board;
(4) Connecting the universal aging motherboard with an aging test machine to introduce an aging driving signal of the aging test machine through the aging daughter board for high-temperature high-humidity dynamic aging test;
(5) After the burn-in test is finished, the burn-in daughter board is taken down from the universal burn-in motherboard, and the peripheral application circuit on the burn-in daughter board is disconnected from the burn-in chip;
(6) And connecting the aged daughter board with the aged chip with a performance testing instrument to introduce testing signals of the performance testing instrument through metal contacts on the back of the aged daughter board for performance testing.
Other technical solutions within the scope of the present invention can be fully realized by those skilled in the art according to the teachings of the present embodiment.
Claims (10)
1. An integrated circuit chip burn-in apparatus based on a daughter motherboard, the apparatus comprising a universal burn-in motherboard (10) and a plurality of burn-in daughter boards (20); a plurality of stations (11), golden finger interfaces (12) and power interfaces (13) are arranged on the universal aging motherboard (10), a plurality of contact pins (111) which are arranged in an array are arranged on the stations (11), and the golden finger interfaces (12) are used for being connected with an aging test machine; the burn-in daughter board (20) can be arranged on a station (11) of the universal burn-in motherboard (10), a chip mounting part (21) is arranged on the front surface of the burn-in daughter board, and a peripheral application circuit is integrated, a chip to be tested is mounted on the chip mounting part (21), and the peripheral application circuit is matched with the chip to be tested mounted on the chip mounting part (21); a plurality of metal contacts (22) arranged in an array are arranged on the back of the aging sub-board (20), wherein one part of the metal contacts (22) is electrically connected with pins of a chip to be tested, which is arranged on the chip mounting part (21), and the other part of the metal contacts is electrically connected with peripheral application circuits on the front of the aging sub-board (20); pins (111) on the station (11) are matched with and contact with metal contacts (22) on the back of the burn-in daughter board (20), so that the burn-in daughter board (20) is connected to the universal burn-in motherboard (10).
2. The test device of claim 1, wherein: the contact pin (111) is a spring pin.
3. The test device according to any one of claims 1 to 2, wherein: a chip to be tested is mounted on a chip mounting portion (21) on the burn-in daughter board (20) in a chip mounting manner.
4. A test device according to any one of claims 1 to 3, wherein: the chip to be tested is arranged on the chip mounting part (21) on the burn-in daughter board (20) in a plugging manner, and a chip socket for plugging the chip to be tested is arranged on the chip mounting part (21).
5. A test device according to any one of claims 1 to 3, wherein: all peripheral application circuits on the aging daughter board (20) are electrically connected with the chip to be tested, which is mounted by the chip mounting part (21), through a resistor of 0 ohm.
6. A test device according to any one of claims 1 to 3, wherein: the device also comprises a chip connecting socket (40), wherein the chip connecting socket (40) comprises a socket body (41), a test board (411) is arranged on the socket body (41), a plurality of spring pins (412) which are arranged in an array are arranged on the test board (411), and the spring pins (412) are matched with and contacted with the metal contacts (22) on the back of the aging sub-board (20), so that the aged chip is connected into the performance testing instrument.
7. The test device of claim 1, wherein: the aging daughter board (20) is fixed on the universal aging mother board (10) through bolts and nuts, and through holes (24) for the bolts to pass through are formed in the aging daughter board (20).
8. The method for burn-in testing of a daughter-motherboard based integrated circuit chip of claim 1 comprising the steps of:
(1) For different types of chips to be tested, peripheral application circuits matched with the chips to be tested are integrated on the front surface of the aging daughter board; mounting a metal contact array on the back of the aged daughter board;
(2) Mounting the chip to be tested on the chip mounting part of the burn-in daughter board, and respectively connecting pins of the chip to be tested and a peripheral application circuit with corresponding metal contacts;
(3) Mounting an aging daughter board with a chip to be tested on a station of a universal aging mother board;
(4) Connecting the universal aging motherboard with an aging test machine to introduce an aging driving signal of the aging test machine through the aging daughter board for high-temperature high-humidity dynamic aging test;
(5) After the burn-in test is finished, the burn-in daughter board is taken down from the universal burn-in motherboard, and the peripheral application circuit on the burn-in daughter board is disconnected from the burn-in chip;
(6) And connecting the aged daughter board with the aged chip with a performance testing instrument to introduce testing signals of the performance testing instrument through metal contacts on the back of the aged daughter board for performance testing.
9. The test method according to claim 8, wherein: all peripheral application circuits on the aging daughter board are electrically connected with the chip to be tested which is installed by the chip installation part through a 0 ohm resistor; after the ageing test in the step (4), the high-temperature soldering iron is used for desoldering to remove the 0 ohm resistor, so that the peripheral application circuit is disconnected from the chip.
10. The test method according to claim 8, wherein: in the step (6), the aged daughter board with the aged chip is connected with the performance testing instrument through a chip connecting socket; the chip connecting socket comprises a socket body, a test board is arranged on the socket body, a plurality of spring pins which are arranged in an array are arranged on the test board, and the spring pins are matched with and contacted with the metal contacts on the back of the aging sub-board, so that the aged chip is connected into the performance test instrument.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710135630.3A CN106771987B (en) | 2017-03-08 | 2017-03-08 | Integrated circuit chip burn-in test device and test method based on sub-mother board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710135630.3A CN106771987B (en) | 2017-03-08 | 2017-03-08 | Integrated circuit chip burn-in test device and test method based on sub-mother board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106771987A CN106771987A (en) | 2017-05-31 |
| CN106771987B true CN106771987B (en) | 2023-08-22 |
Family
ID=58961161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710135630.3A Active CN106771987B (en) | 2017-03-08 | 2017-03-08 | Integrated circuit chip burn-in test device and test method based on sub-mother board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106771987B (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107328962B (en) * | 2017-08-16 | 2019-11-19 | 常州市武进区半导体照明应用技术研究院 | A kind of LED β type metal clips combined type aging clamp |
| CN109782161A (en) * | 2018-12-26 | 2019-05-21 | 中国科学院长春光学精密机械与物理研究所 | Anti-fuse FPGA debugging circuit board and debugging method |
| CN109765481A (en) * | 2018-12-29 | 2019-05-17 | 西安智多晶微电子有限公司 | A kind of test board of the CPLD chip based on FPGA/MCU |
| CN109975691A (en) * | 2019-03-29 | 2019-07-05 | 成都天奥技术发展有限公司 | Integrated circuit universal burn-in experimental rig |
| CN110058146A (en) * | 2019-05-22 | 2019-07-26 | 西安太乙电子有限公司 | It is a kind of to change the mold general aging test device and its operating method |
| CN116577587A (en) * | 2019-12-19 | 2023-08-11 | 深圳硅基仿生科技股份有限公司 | Electrode Aging Test Method |
| CN114076859A (en) * | 2020-08-18 | 2022-02-22 | 中国科学院国家空间科学中心 | Full-temperature aging test system and method for core components for aerospace |
| CN114323379B (en) * | 2020-09-30 | 2024-05-24 | 矽磐微电子(重庆)有限公司 | Thrust test fixture and chip mounting thrust test method |
| CN112798825A (en) * | 2020-12-29 | 2021-05-14 | 北京无线电计量测试研究所 | Aging performance test fixture for ultrahigh fundamental frequency crystal oscillator |
| CN113125936A (en) * | 2021-03-04 | 2021-07-16 | 杭州长川科技股份有限公司 | Aging test device |
| CN113438799B (en) * | 2021-06-28 | 2022-10-25 | 海光信息技术股份有限公司 | Aging circuit board, aging test structure and aging test method |
| CN113918495A (en) * | 2021-10-11 | 2022-01-11 | 北京小米移动软件有限公司 | Power supply daughter board |
| CN113933689A (en) * | 2021-11-18 | 2022-01-14 | 东莞记忆存储科技有限公司 | A chip test tray |
| CN115267480B (en) * | 2021-12-27 | 2025-11-28 | 天芯互联科技有限公司 | Test device |
| TW202332923A (en) * | 2022-02-14 | 2023-08-16 | 神煜電子股份有限公司 | Reliability test assembly of ICs |
| CN114839401A (en) * | 2022-03-12 | 2022-08-02 | 江苏宝浦莱半导体有限公司 | Accelerated life test experiment High-density layout aging board with gold finger plug-in structure |
| CN117250373A (en) * | 2022-06-10 | 2023-12-19 | 久元电子股份有限公司 | Test suites and test equipment |
| CN115359745B (en) * | 2022-08-19 | 2025-02-11 | 苏州华兴源创科技股份有限公司 | Display panel testing equipment and mainboard and subboard used in the testing equipment |
| CN115932536A (en) * | 2022-11-17 | 2023-04-07 | 珠海妙存科技有限公司 | A chip transfer test device, circuit board and method |
| CN116047273A (en) * | 2023-02-15 | 2023-05-02 | 优普士电子(深圳)有限公司 | An IC aging test board |
| CN116203399A (en) * | 2023-04-03 | 2023-06-02 | 无锡中微腾芯电子有限公司 | A general burn-in test device and method for a vehicle-level voltage regulation circuit |
| CN116660719A (en) * | 2023-05-15 | 2023-08-29 | 上海精密计量测试研究所 | A general ATE interface sub-motherboard test method based on FLEX test system |
| CN117590206B (en) * | 2024-01-19 | 2024-04-02 | 北京芯可鉴科技有限公司 | Adjustable chip test board and chip test method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5534786A (en) * | 1994-10-14 | 1996-07-09 | Co-Operative Facility For Aging Tester Development | Burn-in and test method of semiconductor wafers and burn-in boards for use in semiconductor wafer burn-in tests |
| CN102539984A (en) * | 2012-01-13 | 2012-07-04 | 深圳市江波龙电子有限公司 | Mass production tester and mass production aging test system |
| CN204495961U (en) * | 2015-03-02 | 2015-07-22 | 山东盛品电子技术有限公司 | A kind of aging board chip testing plate |
| CN206546416U (en) * | 2017-03-08 | 2017-10-10 | 上海鑫匀源科技有限公司 | A kind of IC chip ageing tester based on mother baby plate |
-
2017
- 2017-03-08 CN CN201710135630.3A patent/CN106771987B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5534786A (en) * | 1994-10-14 | 1996-07-09 | Co-Operative Facility For Aging Tester Development | Burn-in and test method of semiconductor wafers and burn-in boards for use in semiconductor wafer burn-in tests |
| CN102539984A (en) * | 2012-01-13 | 2012-07-04 | 深圳市江波龙电子有限公司 | Mass production tester and mass production aging test system |
| CN204495961U (en) * | 2015-03-02 | 2015-07-22 | 山东盛品电子技术有限公司 | A kind of aging board chip testing plate |
| CN206546416U (en) * | 2017-03-08 | 2017-10-10 | 上海鑫匀源科技有限公司 | A kind of IC chip ageing tester based on mother baby plate |
Non-Patent Citations (1)
| Title |
|---|
| 朱卫良 ; .集成电路动态老化新技术的实施.电子与封装.2008,(11),第12-15、42页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106771987A (en) | 2017-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106771987B (en) | Integrated circuit chip burn-in test device and test method based on sub-mother board | |
| CN206546416U (en) | A kind of IC chip ageing tester based on mother baby plate | |
| CN104316859A (en) | Chip testing equipment with high universality | |
| CN101750578A (en) | Automatic test system for integrated circuit board electrodes | |
| CN109425810B (en) | Semiconductor testing apparatus, semiconductor testing system, and semiconductor testing method | |
| CN218782312U (en) | A test fixture adapted to multi-standard stamp hole PCB boards | |
| CN205067680U (en) | Bga chip testing system | |
| CN201732104U (en) | Testing plug board | |
| CN205725770U (en) | The multi-channel test system of wireless communication module and multipath testing equipment thereof | |
| CN217085118U (en) | Novel aging board | |
| CN215641651U (en) | Three-dimensional test board and multistation three-dimensional test board for chip testing | |
| CN201859200U (en) | Plug and play relay test device | |
| CN206223929U (en) | A kind of microwave chip screening plant | |
| CN211905591U (en) | High-temperature aging test device for integrated circuit | |
| CN106597251B (en) | Microwave chip screening device and screening method thereof | |
| CN105301516A (en) | A fixture and method for power supply testing of BGA chips | |
| CN101975921A (en) | Chip test board and test method, and DFN packaging device test board and test method | |
| CN212723204U (en) | A test circuit board and test system | |
| CN211236170U (en) | Circuit board | |
| CN218974419U (en) | IC electronic element test fixture with sub-mother board structure | |
| CN223217615U (en) | Integrated circuit chip aging test device | |
| CN116203399A (en) | A general burn-in test device and method for a vehicle-level voltage regulation circuit | |
| CN110716121A (en) | Soft board and connector full-page testing method | |
| CN100443901C (en) | Test switching card and test equipment thereof | |
| CN112540251A (en) | Intelligent power module testing device and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |