CN102129026A

CN102129026A - Failure positioning method of chip

Info

Publication number: CN102129026A
Application number: CN2011100002569A
Authority: CN
Inventors: 叶本银
Original assignee: Suzhou Pixcir Microelectronics Co Ltd
Current assignee: Suzhou Pixcir Microelectronics Co Ltd
Priority date: 2011-01-04
Filing date: 2011-01-04
Publication date: 2011-07-20

Abstract

The invention relates to a failure positioning method of a chip, comprising the following steps of: ensuring a failure electric testing item; then editing corresponding codes in an MCU (Microprogrammed Control Unit); and finally, sending a corresponding signal mode to the to-be-analyzed chip via the MCU. The failure positioning method of the chip is simple and faster in speed; the accuracy and the speed are greatly improved when operation; as the MCU is used as a signal generator, the MCU can send any needed signals and can simulate each state of the chip during working, thereby testing any failure item of the chip.

Description

The method of a kind of chip failure location

Technical field

The present invention relates to the chip failure analysis technical field, the method for particularly a kind of chip failure location.

Background technology

Because integrated circuit lost efficacy in development, production and use unavoidably, along with people's improving constantly to product quality and reliability requirement, it is more and more important that failure analysis work also seems, by the chip failure analysis, can help the integrated circuit (IC) design personnel to find not matching of defective in the design, technological parameter or design and operate in problem such as improper, so also performance particularly important just of the meaning of failure analysis.At first, failure analysis is a necessary means of determining chip failure mechanism; Secondly, failure analysis provides necessary information for effective fault diagnosis; Then, the design of chip is updated or is repaired in failure analysis for the design engineer, makes it and the identical more feedback information that necessity is provided of design specifications; At last, failure analysis can be assessed the validity of different test vectors, for production test provides necessary replenishing, is the validation test process optimization basis of submitting necessary information.

The above-mentioned main cause of just enumerating failure analysis, present stage, general inefficacy location technology mainly was utilization " probe test " method.So-called " probe test " is meant and uses a kind of probe station, and described probe station includes probe, when chip being lost efficacy the location, a termination of probe need be contacted on the inside pin of chip, and the other end is drawn lead.In practical operation when if a lot of probes are worked simultaneously, the user just is difficult to operation.For example when four signal inputs of needs, add power supply signal and ground signalling that chip itself has, amount to need six probes to be aligned on the respective pins on the chip, chip itself is just very little, need just can see each position of pin by microscope clearly, and the user use simultaneously six probe operations get up should be just difficulty more.

Therefore need solve above problem for users provide a kind of easier method.

Summary of the invention

The actual technical matters to be solved of the present invention is the method how a kind of chip failure location that can increase work efficiency and can be user-friendly to is provided.

In order to realize above-mentioned purpose of the present invention, the invention provides a kind of chip failure localization method, its step is as follows: at first, determine the testing electrical property project that lost efficacy; Secondly, at the corresponding code of MCU inediting; At last, send corresponding signal mode to chip to be analyzed by MCU.

The method of chip failure of the present invention location, not only simple, and speed is faster, accuracy when the user operates and speed all improve greatly, owing to utilize MCU as signal generator, so can send any desired signal, each state in analog chip when work, thereby any inefficacy project that can the test analysis chip.

Description of drawings

Fig. 1 is the present invention's localization method process flow diagram that lost efficacy;

Fig. 2 is the connection diagram of microprocessor of the present invention and chip.

Embodiment

The present invention is further illustrated below in conjunction with drawings and Examples.

What is called lost efficacy to locate to chip and was meant the focus of observing normal chip and chip failing under low-light microscope (EmmisionMicroscope is called for short EMMI) respectively, found out abnormity point by contrast, and the basic reason of further analysis chip fault.So when chip is carried out failure analysis, at first need to determine the testing electrical property project of inefficacy, because a lot of projects on the chip can be tested, as the pin on the chip whether leak electricity, quiescent dissipation and dynamic power consumption etc., so before the location of losing efficacy, need clear and definite test event.And chip itself contains plurality of modules, different function on the different module controls chips.So when the signal of input end is the same, the chip module after the inefficacy just and the module under the normal condition variant, utilize specific chip testing anchor clamps should just can find out discrepancy analysis at the low-light microscopically.

Following mask body is discussed the chip failure localization method:

Please refer to and Figure 1 shows that the present invention analyzes the method flow diagram of chip failing, at first need to determine the testing electrical property project of inefficacy; Secondly,, be recorded in after the burning in the MCU, form corresponding signal mode, and described respective code is each inefficacy project of judging corresponding to testing electrical property by described code at the corresponding code of MCU (microprocessor) inediting; Place specific chip testing anchor clamps (with reference to the patent of our company chip to be analyzed application in 09 year, its application number is ZL 200920232730.9), and when described chip placed test fixture, the front openings of the encapsulation cladding of chip exposed internal wafer; Build circuit diagram then, please refer to shown in Figure 2, described MCU is connected with power lead by some signal wires with chip, and be equipped with power end VCC and earth terminal GND and corresponding pin on described MCU and the chip, the respective pins on the described MCU is connected by signal wire 10 with respective pins on the chip.And then, after whole device powers on, just the code of described MCU the inside can be passed to chip, just corresponding signal mode can be sent in the chip to be analyzed by described MCU since so, described MCU is equivalent to the effect of signal generator at this moment.Then, begin to test corresponding electrical parameter; At last, just can observe the also abnormity point of positioning chip, finally realize the fault of analysis chip at the low-light microscopically.

Now the dynamic power consumption with test chip is an example, so-called power consumption is meant because chip has input end and output terminal and power end and earth terminal, thereby so just can constitutes the performance number that a current return detects chip self generation behind voltage table of chip series connection and a reometer.Earlier the information under the dynamic power consumption to be measured is compiled corresponding code in the MCU the inside, chip to be measured is placed in this certain chip test fixture again, be delivered in the chip by signal wire then, chip just is under the dynamic power consumption state after receiving thus, owing to be provided with holding tank in these anchor clamps, and be provided with in the holding tank and corresponding each pin of decapsulation chip, so just can observe the abnormal module that occurs arbitrarily in the chip fast at described low-light microscopically, thereby find out failpoint, finally realize the defective of analysis chip.Because measured signal all can be input among the MCU by code, and the number of no matter treating measurement information has several, can be input among the MCU by editing corresponding code simultaneously, is delivered on the chip by signal wire, abnormity point in low-light microscopically observation chip is analyzed then.So, the user operates not only convenient, and has saved the time.Moreover, because microprocessor can send any desired signal to chip as sender unit, also be equivalent to simulate duty under measured signal so receive the chip of signal among the present invention.

The method of chip failure of the present invention location, can simulate the environment of chip failure under any state, described MCU is as signal generator, when input signal is the same, will cause the module in the chip failing there are differences, contrast by the low-light microscopically just can be found out failpoint fast, thereby the analytical approach of abandoning tradition probe contact chip respective pins has one by one improved work efficiency greatly.

Claims

1. the method for chip failure location, its step is as follows:

At first, determine the testing electrical property project of inefficacy;

Secondly, at the corresponding code of MCU inediting;

At last, send corresponding signal mode to chip to be analyzed by MCU.

2. the method for claim 1 is characterized in that: described behind the corresponding code of MCU inediting, need chip to be analyzed is placed specific test fixture.

3. method as claimed in claim 2 is characterized in that: after described chip places test fixture, build circuit diagram.

4. method as claimed in claim 3 is characterized in that: when described chip placed test fixture, the front openings of the encapsulation cladding of chip exposed internal wafer.

5. method as claimed in claim 3 is characterized in that: described MCU measures corresponding electrical parameter after signal mode is sent to chip to be analyzed.

6. method as claimed in claim 5 is characterized in that: behind the corresponding electrical parameter of described measurement, need to observe and the positioning chip abnormity point at the low-light microscopically.

7. the method for claim 1, it is characterized in that: described MCU is connected with power lead by some signal wires with chip.

8. the method for claim 1, it is characterized in that: described signal mode is to be formed by the respective code at the MCU inediting.

9. the method for claim 1 is characterized in that: described respective code is each inefficacy project of judging corresponding to testing electrical property.