CN202994975U - QFP128 packaged chip test board - Google Patents
QFP128 packaged chip test board Download PDFInfo
- Publication number
- CN202994975U CN202994975U CN 201220700367 CN201220700367U CN202994975U CN 202994975 U CN202994975 U CN 202994975U CN 201220700367 CN201220700367 CN 201220700367 CN 201220700367 U CN201220700367 U CN 201220700367U CN 202994975 U CN202994975 U CN 202994975U
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- CN
- China
- Prior art keywords
- chip test
- qfp128
- interface
- flash
- main control
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a QFP128 packaged chip test board which comprises a main control chip test socket and a plurality of flash interfaces, wherein the main control chip test socket and the flash interfaces are connected through a bus, the main control chip test socket is connected with an interface used for being connected with an upper computer and an interface used for data outputting, a configured power supply contains a 3.3V loop and a 1.2V loop, and each loop is provided with a test point. According to the utility model, the test content is wide, and the test efficiency can be improved.
Description
Technical field
The utility model relates to a kind of QFP128 packaged chip test board, and QFP is the abbreviation of Plastic Quad Flat Package, i.e. square Flat type packaged technology.
Background technology
Between the chip pin that QFP realizes, distance is very little, and pin is very thin, and general extensive or VLSI (very large scale integrated circuit) adopts this packing forms, and its number of pins is generally all more than 100.Easy to operate during this technology packaged chip, reliability is high; And its packaging appearance size is less, and parasitic parameter reduces, and is fit to frequency applications; This technology mainly is fit to SMT surface mounting technique installation wiring on PCB.
In SoC(System on Chip, SOC (system on a chip)) in the chip design process, it is whether successful important step of chip design that chip is completed test after flow.Simultaneously, as very wide in the Flash application, increasing manufacturer adds wherein, cause on market based on kind and the model of the Flash of various criterion varied, therefore, the test board that is used for test should compatible different Flash, and these tests are all the required contents of chip testing.
Can find out from above content, in the chip testing process, because outside need is to the different order of chip input, and want test chip work in voltage condition, chip is in the power consumption situation of zero load and full load, chip is with the compatible context of different flash, output signal integrality etc. during chip operation, and this just requires test board to have wider adaptability.Existing test board is subject to packing forms, and the content of test is limited.
Summary of the invention
Therefore, the purpose of this utility model is to propose the wider QFP128 packaged chip test board of a kind of content measurement, improves the efficient of test.
The technical solution adopted in the utility model is:
A kind of QFP128 packaged chip test board comprises the main control chip test bench and the multi-disc flash interface that connect by bus, and wherein the main control chip test bench is connected with the interface that is connected for host computer, and the interface that is used for data output; The board mounted power of configuration contains 3.3V loop and 1.2V loop, and is equipped with test point on every kind of loop.
Above-mentioned QFP128 packaged chip test board also comprise the flash plate by socket and the access of described bus, and described flash interface and described main control chip test bench is direct-connected by bus, form plate and carry the flash interface; Accordingly, the output terminal of described main control chip test bench coupling has two groups of signal testing points, carries test with the flash chip of two passages of flash plate with matching disc; Simultaneously, the CE signal trigger circuit of configuration main control chip test bench are to select different passages.
Can find out from above structure, convenient based on the QFP encapsulation operation, the high characteristics that get of reliability, integrate host computer interface, data export structure, can carry out partial test by host computer, and export test structure by data output interface, matching test seat and a plurality of flash interface, can change chip to be tested easily, so convenient to the compatibility test of flash chip.By the test point that power supply is reserved, the situation that can test very easily plank various voltages when zero load and load.
Above-mentioned QFP128 packaged chip test board, all data lines and the control line of each described passage dispose test point.
Above-mentioned QFP128 packaged chip test board is characterized in that, described flash interface is welding card or prefabricated flash chip pocket.
Above-mentioned QFP128 packaged chip test board, described board mounted power contains esd protection circuit.
Above-mentioned QFP128 packaged chip test board, the test point in corresponding described loop is arranged on the output terminal in loop, and is provided with output resistance at output terminal, and test point is arranged on the two ends of output resistance.
Above-mentioned QFP128 packaged chip test board, the interface that is used for being connected with host computer is USB interface, the interface that is used for data output is serial ports.
Above-mentioned QFP128 packaged chip test board also disposes the jtag interface that is connected in described main control chip test bench.
Description of drawings
Fig. 1 is the structure principle chart according to a kind of QFP128 packaged chip test board of the present utility model.
Embodiment
In the test process of chip, because outside need is inputted different orders to chip, and want the situation of test chip voltage in work, chip is in the power consumption situation of zero load and full load, chip is with the compatible context of different flash, integrality of output signal etc. during chip operation.All to need the test done in test process.
Above-mentioned purpose and effect can be more apparent in following content, and this test board provides a scheme that realizes above function.
QFP128 packaged chip test board as shown in Figure 1: this test board has a power input terminal, a USB interface, a jtag interface and a serial ports input.Placed the test bench (socket) of a QFP128 packaged chip on plank, signal output part at this chip has added two groups of signal testing points simultaneously, we can complete the test of two passages (chanel) simultaneously like this, chip has directly connected two flash chips, as shown in Figure 1, we can also connect a flash plate by socket simultaneously, can accomplish to test simultaneously a plurality of chanel, multi-disc flash.
Test board input be+direct supply of 5V that can be at first through an ESD(Electro-Static discharge after the power supply input, static discharges) holding circuit, can accomplish effective protection to power supply in the middle of test process like this.
Electric power loop also has two LDO(low dropout regulator, low pressure difference linear voltage regulator simultaneously), can produce respectively 3.3V and 1.2V power supply to main control chip and flash chip.
Simultaneously for the output in other words at the two ends of every kind of voltage, all reserve a test point, can test very easily the situation of our planks various voltages when zero load and load; Simultaneously, we also can by the voltage at test resistance two ends and the electric current that passes through, calculate respectively our power consumption when zero load and load.Wherein resistance is the resistance of the power supply output of coupling, is carried in the load that voltage and current on output resistance can directly know plank.
The USB interface that is connected in the main control chip test bench is used for the USB interface of external host computer as PC, can give an order to chip by PC etc., test board has also been reserved a serial interface simultaneously, be connected to 232 output ports of chip, can be in the middle of the process of test output we want the test result that obtains.
Placed two flash on test board, can directly weld the flash chip, also can weld SMD(Surface Mounted Devices, surface mount device) encapsulation socket.All data lines of each chanel and control line have with its corresponding test point, thereby can connect very easily oscillograph, and protocol analyzer etc. are done accurate test to signal.Simultaneously, our main control chip on test board encapsulate we accomplished can compatible chip directly welding and testing by socket.
Jtag interface is to do single stepping test, as the debugging of ARM.
The CE signal that can export by main control chip (here main control chip is directly to be connected with flash) comes flash on the choice for use test board still to use flash on the flash plate that connects by the CN bus.Wherein, the flash plate is selected pcb board, test when can change easily flash and satisfy many flash of a plurality of chanel.
This programme has been realized the compatibility (comprising main control chip, the flash chip) of a plurality of parts, so just can save greatly the cost of test, the efficient when also having improved simultaneously test.Can very conveniently change efficiently main control chip and flash chip.
Claims (8)
1. a QFP128 packaged chip test board, is characterized in that, comprises the main control chip test bench and the multi-disc flash interface that connect by bus, and wherein the main control chip test bench is connected with the interface that is connected for host computer, and the interface that is used for data output; The board mounted power of configuration contains 3.3V loop and 1.2V loop, and is equipped with test point on every kind of loop.
2. QFP128 packaged chip test board according to claim 1, is characterized in that, also comprise the flash plate by socket and the access of described bus, and described flash interface and described main control chip test bench is direct-connected by bus, form plate and carry the flash interface; Accordingly, the output terminal of described main control chip test bench coupling has two groups of signal testing points, carries test with the flash chip of two passages of flash plate with matching disc; Simultaneously, the CE signal trigger circuit of configuration main control chip test bench are to select different passages.
3. QFP128 packaged chip test board according to claim 3, is characterized in that, all data lines and the control line of each described passage dispose test point.
According to claim 1 to 3 arbitrary described QFP128 packaged chip test board, it is characterized in that, described flash interface is welding card or prefabricated flash chip pocket.
5. QFP128 packaged chip test board according to claim 1, is characterized in that, described board mounted power contains esd protection circuit.
6. QFP128 packaged chip test board according to claim 1 or 5, is characterized in that, the test point in corresponding described loop is arranged on the output terminal in loop, and is provided with output resistance at output terminal, and test point is arranged on the two ends of output resistance.
7. QFP128 packaged chip test board according to claim 1, is characterized in that, the interface that is used for being connected with host computer is USB interface, and the interface that is used for data output is serial ports.
8. QFP128 packaged chip test board according to claim 1, is characterized in that, also disposes the jtag interface that is connected in described main control chip test bench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220700367 CN202994975U (en) | 2012-12-17 | 2012-12-17 | QFP128 packaged chip test board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220700367 CN202994975U (en) | 2012-12-17 | 2012-12-17 | QFP128 packaged chip test board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202994975U true CN202994975U (en) | 2013-06-12 |
Family
ID=48566144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220700367 Expired - Fee Related CN202994975U (en) | 2012-12-17 | 2012-12-17 | QFP128 packaged chip test board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202994975U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105866658A (en) * | 2016-03-29 | 2016-08-17 | 深圳市九洲电器有限公司 | Electronic product single board for testing and testing apparatus |
| CN107544019A (en) * | 2017-08-22 | 2018-01-05 | 北京小米移动软件有限公司 | Apparatus for testing chip and chip detecting method |
-
2012
- 2012-12-17 CN CN 201220700367 patent/CN202994975U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105866658A (en) * | 2016-03-29 | 2016-08-17 | 深圳市九洲电器有限公司 | Electronic product single board for testing and testing apparatus |
| CN105866658B (en) * | 2016-03-29 | 2019-02-15 | 深圳市九洲电器有限公司 | A kind of test electronics product single board and test device |
| CN107544019A (en) * | 2017-08-22 | 2018-01-05 | 北京小米移动软件有限公司 | Apparatus for testing chip and chip detecting method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130612 Termination date: 20151217 |
|
| EXPY | Termination of patent right or utility model |