CN104865412A - Chip testing board and chip testing method - Google Patents
Chip testing board and chip testing method Download PDFInfo
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- CN104865412A CN104865412A CN201410065496.0A CN201410065496A CN104865412A CN 104865412 A CN104865412 A CN 104865412A CN 201410065496 A CN201410065496 A CN 201410065496A CN 104865412 A CN104865412 A CN 104865412A
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Abstract
The invention provides a chip testing board and a chip testing method. The chip testing board comprises a first testing board which is used for connecting a testing machine platform and comprises a first connection part, a second testing board which comprises a second connection part and a third connection part which is electrically connected to the second connection part, and a conductive connection part which is used for connecting the third connection part and the test pin of a chip to be tested. The first connection part and the second connection part are connected in a pluggable way. According to the chip testing board and chip testing method, the support of various package types can be realized, when the chips of different package types are tested, the design of a new testing board for each type of packaged chip is not needed any more, thus the testing efficiency is improved, the time cost is reduced, the money for manufacturing or order a new testing board is saved, and the chip testing board and the chip testing method have the advantages of simple structure, easy use and low cost.
Description
Technical field
The application relates to chip testing field, more specifically, relates to a kind of chip testing plate and chip detecting method.
Background technology
Semiconductor maker can manufacture integrated circuit or the product (chip) of multiple difference encapsulation usually.Wherein, each product may require its special packing forms.At present, the type of package for chips often used in the semiconductor industry is as follows: SBDIP(side soldering dual-in-line package), BGA(ball grid array), QFP(quad flat package), TSOP(Thin Small Outline Package), SOT(small outline transistor), the encapsulation of SOIC(small outline integrated circuit) and QFN(quad flat non-leaded chip package) etc.When selecting packing forms for a certain specific product, need the attribute considering encapsulation, such as size, number of pins, power consumption, execute-in-place condition, application and cost etc.
Electrostatic is a kind of objectively spontaneous phenomenon, is non-uniformly distributed on chip itself, human body, on machine and on environment that chip can exist and surroundings.These static electric charges, all can discharge by certain mode at any time.Static discharge (ESD, Electro-Static discharge) has the advantages that voltage is high, electricity is low, electric current is little and action time is short.The destruction that ESD causes electronic product and operation have two kinds.In a kind of situation, device is seriously damaged, afunction, and this situation can find in the detection of production run.In another kind of situation, device component is damaged, and function is not yet lost, and can not find in the detection of production run, but product can be made in the middle of use to become unstable, bad during fashion, thus, forms larger harm to product quality.Therefore, static discharge is the maximum killer of Quality of electronic products, and ESD also becomes an important indicator of chip performance.
Breech lock (LU, Latch-up) refers in the chips, and between power supply and ground, a kind of low impedance path that PNP and the NPN bipolarity BJT due to parasitism influences each other and produces, its existence can make to produce big current between power supply and ground.Along with the development of chip manufacturing process, potting and integrated level also more and more higher, produce the possibility of breech lock also increasing.The excessive current amount produced by breech lock may make chip produce permanent destruction, is one of most important measure of chip layout to the strick precaution of breech lock.
Visible, concerning chip production person, ESD and LU is two key indexs weighing product reliability, two important indicators when being also chip testing.But because product category is various, its packing forms is also different, therefore, usually can face such problem when product reliability is tested, namely in the redesign and order of various test board, a large amount of time and fund can be spent.
Up to now, as a rule, one piece of test board only can support a kind of chip of packing forms, such as, for PDIP64 test board, only can support the device that PDIP encapsulates, and the number of pins of this device is less than 64.In other words, except number of pins is less than the chip of PDIP encapsulation of 64, other chip all can not use this PDIP64 test board to test.
Fig. 1 shows a kind of test board for testing ESD and LU, such as, and Zapmaster test board.As shown in Figure 1, at the back side of this test board, be provided with multiple testing weld pad radially arranged, these testing weld pads 13 for contacting with the test probe of tester table, thus between tester table and chip to be tested transmission of signal.
Fig. 2 shows a kind of structural representation of PDIP test board.As shown in Figure 2, this test board is provided with multiple PDIP socket 14.
At present, the fc-specific test FC plate for a certain product has its oneself special packing forms.Such as, Fig. 3 shows a kind of structural representation of traditional BGA144 test board.In figure 3, this test board only can be used for the chip 15 of this encapsulated type of test b GA144.In order to test the chip of different encapsulated type, in prior art usually or be seek outsourcing support, or be redesign and order new test board.But the cost of these two kinds of modes is all very high.
But the situation that number of pins is different identical concerning encapsulated type, method of the prior art is by regulating test condition in conjunction with the actual operating conditions of some contact pins or power supply approximate simulation chip.But, like this when root is pinpointed the problems in detection, there is certain risk.
Therefore, this area needs a kind of ESD/LU test board that is general, that be not fixed against concrete packing forms.
Summary of the invention
The application aims to provide a kind of chip testing plate and chip detecting method, only can support a kind of problem of chip of specific type of encapsulation to solve a kind of test board in prior art.
For solving the problems of the technologies described above, according to first aspect of the application, provide a kind of chip testing plate, comprising: the first test board, for being connected with tester table, the first test board comprises the first connecting portion; Second test board, comprise the second connecting portion and the 3rd connecting portion, the second connecting portion is electrically connected with the 3rd connecting portion; First connecting portion and the second connecting portion are connected pluggablely; Conductive connection part, for connecting the test pin of the 3rd connecting portion and chip to be tested.
Further, the number of the first connecting portion and the second connecting portion is multiple, and the first connecting portion and the second connecting portion are arranged correspondingly.
Further, the number of the 3rd connecting portion is multiple, forms the chip fixed area for placing chip to be tested between multiple 3rd connecting portion.
Further, the first connecting portion comprises multiple jack, and the second connecting portion comprises the contact pin that multiple and multiple jack coordinates correspondingly.
Further, the first connecting portion is arranged on the first side of the first test board, and the second side of the first test board is provided with multiple testing weld pad, and multiple testing weld pad is connected correspondingly with multiple jack.
Further, multiple testing weld pad is divided into multiple test group, and the testing weld pad in each test group linearly distributes, and multiple test group is radially arranged.
Further, the second connecting portion also comprises multiple external test signal interface, and multiple external test signal interface is electrically connected correspondingly with multiple contact pin.
Further, the second test board is also provided with the contact pin mark for being numbered contact pin.
Further, multiple first connecting portion is in rectangular layout.
Further, multiple second connecting portion is in rectangular layout.
Further, the 3rd connecting portion is pad.
According to second aspect of the application, provide a kind of chip detecting method, comprising: above-mentioned chip testing plate is provided; The test pin of chip to be tested is electrically connected by the 3rd connecting portion of conductive connection part with the second test board of chip testing plate; By the second connecting portion of the second test board and the first connecting portion of the first test board pluggable be connected; Chip testing plate to be installed on tester table and to test.
Further, chip to be tested is wafer.
Further, chip detecting method also comprises: be connected, external test signal to provide test signal to chip to be tested with the external test signal interface of the second test board.
Further, by the second connecting portion of the second test board and the first connecting portion of the first test board pluggable be connected before, chip detecting method also comprises: chip to be tested is fixed to the step on chip to be tested.
Further, chip detecting method is for testing static discharge and/or the latching feature of chip to be tested.
When needing to test the chip of difference encapsulation, the application only needs the test pin of chip to be tested to be connected with the 3rd connecting portion by conductive connection part, thus, thus makes the second test board can support the chip to be tested of different encapsulation.In addition, the interface (i.e. the first connecting portion and the second connecting portion) between the first test board and the second test board can be designed to unified form.
This unified interface and between the second test board with chip to be tested by the mode that conductive connection part is connected, make the support that the application can realize various encapsulated type.When needing to test the chip of different encapsulated type, the chip being no longer necessary for often kind of encapsulation redesigns new test board, thus, not only increase testing efficiency, reduce time cost, but also save the fund manufacturing or order new test board, have the advantages that structure is simple, easy to use, cost is low.
Accompanying drawing explanation
The accompanying drawing forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 diagrammatically illustrates the schematic diagram of a kind of test board of the prior art;
Fig. 2 diagrammatically illustrates the schematic diagram of another kind of test board of the prior art;
Fig. 3 diagrammatically illustrates the schematic diagram of another test board of the prior art;
Fig. 4 diagrammatically illustrates the front view of the first test board in the application;
Fig. 5 diagrammatically illustrates the rear view of the second test board in the application;
Fig. 6 diagrammatically illustrates the front view of the second test board in the application;
Fig. 7 diagrammatically illustrates the connection diagram of chip to be tested in an embodiment in the application and the second test board.
Reference numeral in figure: 1, the first test board; 2, the first connecting portion; 3, the second test board; 4, the second connecting portion; 5, the 3rd connecting portion; 6, conductive connection part; 7, chip to be tested; 8, test pin; 9, jack; 10, contact pin; 11, external test signal interface; 12, contact pin mark; 13, testing weld pad; 14, PDIP socket; 15, chip.
Embodiment
Below the embodiment of the application is described in detail, but the multitude of different ways that the application can be defined by the claims and cover is implemented.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
In order to solve the technical matters of prior art as described above, please refer to Fig. 4-6, as the first aspect of the application, provide a kind of chip testing plate, especially, can be used for static discharge and/or the latching feature of test chip, comprising: the first test board 1, for being connected with tester table, the first test board 1 comprises the first connecting portion 2; Second test board 3, comprises the second connecting portion 4 and the 3rd connecting portion 5, second connecting portion 4 is electrically connected with the 3rd connecting portion 5; First connecting portion 2 and the second connecting portion 4 are connected pluggablely; Conductive connection part 6, for connecting the test pin (pin-pad) 8 of the 3rd connecting portion 5 and chip to be tested 7.Preferably, the 3rd connecting portion 5 is pad, and obviously, the 3rd connecting portion 5 also can be common other structures in this area, such as socket, jack etc.Especially, conductive connection part 6 can be flexible wire etc.
Please refer to Fig. 4 and Fig. 5, the first test board 1 can regard motherboard (mother board) as, and the second test board 3 can be regarded as daughter board (child board).Wherein, motherboard (the first test board 1) is for being connected with tester table, and daughter board (the second test board 3) is for supporting the chip of different encapsulation.Please refer to Fig. 6, when needing to test the chip of difference encapsulation, can by chip 7(to be tested especially, can be packaged chip, also can be the wafer (wafer level) not carrying out encapsulating) need the test pin 8 used to be electrically connected with the 3rd connecting portion 5 on the second test board 3 by conductive connection part 6 when testing.Owing to there is electrical connection between the 3rd connecting portion 5 with the second connecting portion 4, therefore, test pin 8 is also electrically connected with the second connecting portion 4.
After completing the connection between the test pin 8 of chip 7 to be tested and the 3rd connecting portion 5 of the second test board 3, the first connecting portion 2 grafting of the second connecting portion 4 of the second test board 3 and the first test board 1 can be got up.So each test pin 8 of chip 7 to be tested just and between the first test board 1 establishes electrical connection.
When needing to test the chip of difference encapsulation, only need the test pin 8 of chip 7 to be tested to be connected with the 3rd connecting portion 5 by conductive connection part 6, thus make the second test board 3 can support the chip to be tested 7 of different encapsulation.
In addition, the interface (i.e. the first connecting portion 2 and the second connecting portion 4) between the first test board 1 and the second test board 3 can be designed to unified form.This unified interface, and the mode be connected by conductive connection part 6 between the second test board 3 with chip 7 to be tested, make the support that the application can realize various encapsulated type.When needing to test the chip of different encapsulated type, the chip being no longer necessary for often kind of encapsulation redesigns new test board, thus, not only increase testing efficiency, reduce time cost, but also save the fund manufacturing or order new test board, have the advantages that structure is simple, easy to use, cost is low.
Preferably, please refer to Fig. 4 and Fig. 5, the number of the first connecting portion 2 and the second connecting portion 4 is multiple, and the first connecting portion 2 and the second connecting portion 4 are arranged correspondingly.Preferably, multiple first connecting portion 2 is in rectangular layout.Preferably, multiple second connecting portion 4 is in rectangular layout.Preferably, the first connecting portion 2 and the second connecting portion 4 also can the mode in multilayer be arranged, and like this, are specially adapted to the situation that number of pins is large.First connecting portion 2 and the second connecting portion 4 are arranged by above-mentioned formal distribution, the first test board 1 and the second test board 3 can be made when grafting, formed and connect reliably, it is unreliable to avoid owing to connecting, to testing the potential impact brought, thus, improve the stability of test, reliability and accuracy.
Preferably, please refer to Fig. 6, the number of the 3rd connecting portion 5 is multiple, forms the chip fixed area for placing chip 7 to be tested between multiple 3rd connecting portion 5.As shown in Figure 6, these the 3rd connecting portions 5 are arranged around the surrounding of chip fixed area, and chip 7 to be tested is located in this chip fixed area.Especially, chip 7 to be tested can be fixed in this chip fixed area by modes such as bonding or welding, and then is connected with test pin 8 one end of conductive connection part 6, and the other end is connected with the 3rd connecting portion 5.Because chip 7 to be tested can be fixed on the second test board 3 by chip fixed area, thus, can prevent in test process, due to the accidental movement of chip 7 to be tested, cause the loss of connectivity issue of test pin 8 and the 3rd connecting portion 5 and conductive connection part 6, make the connection between three be in reliable and stable state all the time, improve stability and the reliability of test.
Preferably, please refer to Fig. 4 to Fig. 6, the first connecting portion 2 comprises multiple jack 9, second connecting portion 4 and comprises the contact pin 10 that multiple and multiple jack 9 coordinates correspondingly.Obviously, the first connecting portion 2 also can be jack, and correspondingly, the second connecting portion 4 can be contact pin.By the form of jack and contact pin, the plug-in that can realize between the first test board 1 with the second test board 3 is connected, certainly, in a not shown embodiment, first connecting portion 2 and the second connecting portion 4 can also be all gang socket, like this, couple together by modes such as polycore cables therebetween.
Preferably, please refer to Fig. 4, the first connecting portion 2 is arranged on the first side of the first test board 1, and the second side of the first test board 1 is provided with multiple testing weld pad, and multiple testing weld pad is connected correspondingly with multiple jack 9.By testing weld pad, the first test board 1 can be made to contact with the test probe on tester table, to realize the signal transmission between tester table and chip to be tested.Especially, multiple testing weld pad is divided into multiple test group, and the testing weld pad in each test group linearly distributes, and multiple test group is radially arranged, and such as, testing weld pad can be arranged by the mode shown in Fig. 1.
Preferably, please refer to Fig. 6, the second connecting portion 4 also comprises multiple external test signal interface 11, and multiple external test signal interface 11 is electrically connected correspondingly with multiple contact pin 10.Such as, external test signal interface 11 can be jack, contact pin or pad etc.In some cases, tester table possibly cannot provide all signals required for chip 7 to be tested, now, by external test signal interface 11, can provide corresponding test signal to chip 7 to be tested, such as, and power supply (PWR), clock (CLK) etc.
Fig. 7 is the schematic diagram of the second test board after having installed chip to be tested in an embodiment.Please refer to Fig. 7, preferably, the second test board 3 being also provided with the contact pin mark 12 for being numbered contact pin 10.Such as, contact pin mark 12 can be the character (such as numeral or alphabetical etc.) being printed on the second test board 3 surface.By contact pin mark 12, can so that in the process connecting conductive connection part 6, the problem of wrong the 3rd connecting portion 5 can not be there is.In addition, owing to being provided with contact pin mark 12, in the process that conductive connection part 6 is connected with the 3rd connecting portion 5 by reality, do not need accurately conductive connection part 6 to be connected with a certain specific 3rd connecting portion 5, but first can select the 3rd connecting portion 5 easy to use as required, after connection to be done, then according to contact pin mark 12, the numbering of corresponding 3rd connecting portion 5 is read, thus facilitate confirmation and the definition of test pin.
As the second aspect of the application, provide a kind of chip detecting method, comprising: above-mentioned chip testing plate is provided; The test pin 8 of chip 7 to be tested is electrically connected by the 3rd connecting portion 5 of conductive connection part 6 with the second test board 3 of chip testing plate; By the second connecting portion 4 of the second test board 3 and the first connecting portion 2 of the first test board 1 pluggable be connected; Chip testing plate to be installed on tester table and to test.Preferably, chip detecting method is for testing static discharge and/or the latching feature of chip 7 to be tested.Preferably, chip 7 to be tested is wafer.Especially, wafer is not through the chip of encapsulation, uses wafer directly to test, can save the step being carried out by wafer encapsulating, thus, improve efficiency, reduce cost.
Please refer to Fig. 7, first, by chip to be tested 7 by conductive connection part 6(such as, can be flexible wire etc.) couple together (such as, can be weld) with the 3rd connecting portion 5.Then, then be connected pluggable to the second connecting portion 4 and the first connecting portion 2, thus the second test board is fixed on the first test board.Then, just can the first test board 1 be placed on tester table, carry out concrete testing.
Preferably, chip detecting method also comprises: be connected with the external test signal interface 11 of the second test board 3 by external test signal, to provide test signal to chip 7 to be tested.When tester table cannot provide required test signal, test signal can be provided by the external test signal interface 11 of the second test board 3 to chip 7 to be tested.
Preferably, by the second connecting portion 4 of the second test board 3 and the first connecting portion 2 of the first test board 1 pluggable be connected before, chip detecting method also comprises: chip 7 to be tested is fixed to the step on chip 7 to be tested.Because chip 7 to be tested can be fixed on the second test board 3, thus, can prevent in test process, due to the accidental movement of chip 7 to be tested, cause the loss of connectivity issue of test pin 8 and the 3rd connecting portion 5 and conductive connection part 6, make the connection between three be in reliable and stable state all the time, improve stability and the reliability of test.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection domain that all should be included in the application.
Claims (16)
1. a chip testing plate, is characterized in that, comprising:
First test board (1), for being connected with tester table, described first test board (1) comprises the first connecting portion (2);
Second test board (3), comprises the second connecting portion (4) and the 3rd connecting portion (5), and described second connecting portion (4) is electrically connected with described 3rd connecting portion (5); Described first connecting portion (2) and described second connecting portion (4) are connected pluggablely;
Conductive connection part (6), for connecting the test pin (8) of described 3rd connecting portion (5) and chip to be tested (7).
2. chip testing plate according to claim 1, is characterized in that, the number of described first connecting portion (2) and described second connecting portion (4) is multiple, and described first connecting portion (2) and described second connecting portion (4) are arranged correspondingly.
3. chip testing plate according to claim 1, is characterized in that, the number of described 3rd connecting portion (5) is multiple, forms the chip fixed area for placing described chip to be tested (7) between described multiple 3rd connecting portion (5).
4. chip testing plate according to claim 1, is characterized in that, described first connecting portion (2) comprises multiple jack (9), and described second connecting portion (4) comprises the contact pin (10) that multiple and described multiple jack (9) coordinates correspondingly.
5. chip testing plate according to claim 4, it is characterized in that, described first connecting portion (2) is arranged on the first side of described first test board (1), second side of described first test board (1) is provided with multiple testing weld pad, and described multiple testing weld pad is connected correspondingly with described multiple jack (9).
6. chip testing plate according to claim 5, is characterized in that, described multiple testing weld pad is divided into multiple test group, and the described testing weld pad in each described test group linearly distributes, and described multiple test group is radially arranged.
7. chip testing plate according to claim 4, it is characterized in that, described second connecting portion (4) also comprises multiple external test signal interface (11), and described multiple external test signal interface (11) is electrically connected correspondingly with described multiple contact pin (10).
8. chip testing plate according to claim 4, is characterized in that, described second test board (3) is also provided with contact pin mark (12) for being numbered described contact pin (10).
9. chip testing plate according to claim 2, is characterized in that, described multiple first connecting portion (2) is in rectangular layout.
10. chip testing plate according to claim 2, is characterized in that, described multiple second connecting portion (4) is in rectangular layout.
11. chip testing plates according to claim 1, is characterized in that, described 3rd connecting portion (5) is pad.
12. 1 kinds of chip detecting methods, is characterized in that, comprising:
Chip testing according to any one of claim 1 to 11 plate is provided;
The test pin (8) of chip to be tested (7) is electrically connected by the 3rd connecting portion (5) of conductive connection part (6) with second test board (3) of described chip testing plate;
Be connected pluggable to second connecting portion (4) of described second test board (3) and first connecting portion (2) of described first test board (1);
Described chip testing plate to be installed on tester table and to test.
13. chip detecting methods according to claim 12, is characterized in that, described chip to be tested (7) is wafer.
14. chip detecting methods according to claim 12, is characterized in that, described chip detecting method also comprises:
External test signal is connected with the external test signal interface (11) of described second test board (3), to provide test signal to described chip to be tested (7).
15. chip detecting methods according to claim 12, it is characterized in that, before pluggable to second connecting portion (4) of described second test board (3) and first connecting portion (2) of described first test board (1) connection, described chip detecting method also comprises: described chip to be tested (7) is fixed to the step on described chip to be tested (7).
16. chip detecting methods according to claim 12, is characterized in that, described chip detecting method is for testing static discharge and/or the latching feature of described chip to be tested (7).
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| CN201410065496.0A CN104865412A (en) | 2014-02-25 | 2014-02-25 | Chip testing board and chip testing method |
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| CN201410065496.0A CN104865412A (en) | 2014-02-25 | 2014-02-25 | Chip testing board and chip testing method |
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