CN103117263A - Integrated circuit package - Google Patents
Integrated circuit package Download PDFInfo
- Publication number
- CN103117263A CN103117263A CN2013100367410A CN201310036741A CN103117263A CN 103117263 A CN103117263 A CN 103117263A CN 2013100367410 A CN2013100367410 A CN 2013100367410A CN 201310036741 A CN201310036741 A CN 201310036741A CN 103117263 A CN103117263 A CN 103117263A
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- CN
- China
- Prior art keywords
- chip
- packaging
- pad
- integrated circuit
- integrated antenna
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention discloses and provides an integrated circuit package, which can effectively reduce the amount of packaging pins, eliminate angle and position limits of leads, and provide flexible packaging styles so as to reduce packaging cost, application cost and integrated circuit researching and developing cost. The integrated circuit package comprises a packaging frame and one or a plurality of integrated circuit packaging inner chips. The packaging frame is composed of an electrically conductive chip bonding pad and a plurality of packaging pins. A plurality of bonding pads are arranged on the integrated circuit packaging inner chips and are electrically connected with the chip bonding pad through bonding wires. The chip bonding pad is electrically connected to the packaging pins through bonding wires. The bonding pads include power source bonding pads, grounded bonding pads and signal bonding pads; on the integrated circuit packaging inner chips, the chip bonding pad is connected to the power source bonding pads at the same electrical level, or the grounded bonding pads at the same electrical level or one or a plurality of signal bonding pads through one or a plurality of bonding wires. The integrated circuit package is applicable to the technical field of circuit packaging.
Description
Technical field
The present invention relates to a kind of integrated antenna package, relate in particular to and a kind ofly can connect the integrated antenna package of wire on the chip bonding pad of packaging frame, be applied to SOC integrated antenna package technical field.
Background technology
According to the needs of present stage integrated circuit development, on the one hand, the function of integrated circuit (IC) design chip constantly increases, and the requirement of packaging pin number also is on the increase.On the other hand, for reducing packaging cost and application cost, concerning integrated antenna package, during integrated circuit (IC) design, expectation can be used the low-cost compact package mode that satisfies the application function demand.
The encapsulation of the integrated circuit of present stage is because deficiency has in various degree appearred in following some reason.
1, in order to adapt to multiple application function demand, the restriction of multiple cost, to shorten the integrated circuit R﹠D cycle, need to use the same chip, do the encapsulation of multiple different number of pins, different pin order;
2, when replacing older generation's integrated circuit (IC) chip with integrated circuit (IC) chip of new generation, require the old and new's two generations chip fully compatible on number of pins and pin order, thereby do not need to revise the pcb board of application scheme, reduce R﹠D costs and the risk of application scheme;
3, after integrated circuit (IC) chip of new generation was used new design way, arrangement and the position of weld pad on chip (PAD) inevitably changed.When doing the encapsulation of new chip with old packing forms, occur causing encapsulating difficulty, the low problem of encapsulation yield across chip bracing wire, wire intersection etc.As shown in Figure 1, be connected by bonding wire between weld pad on integrated circuit (IC) chip on being in peripheral packaging pin 1～16 in figure and being in chip bonding pad, but the weld pad of the same level on same chip (PAD9) need to arrange two bonding wires simultaneously with weld pad (PAD58) just can be connected on packaging pin 16, namely need to adopt the intersection bonding wire could realize that two weld pads are connected on same packaging pin, this can make the encapsulation difficulty.
In a word, because above-mentioned reason, the rough sledding such as pin is too much, bracing wire is difficult, compatibility is difficult, chip redundancy cost is many appear in integrated antenna package.The invention provides a kind of way, specific chip PAD is connected to chip bonding pad, then chip bonding pad is connected to packaging pin, thereby addresses the above problem.
Summary of the invention
Technical problem to be solved by this invention is to overcome the deficiencies in the prior art, provide a kind of and can effectively reduce the packaging pin number, eliminate lead-in wire angle and position limitation, packing forms flexibly is provided, finally reduce the integrated antenna package of packaging cost, application cost and integrated circuit R﹠D costs.
The technical solution adopted in the present invention is: described a kind of integrated antenna package comprises a packaging frame, and chip in one or more integrated antenna packages, described packaging frame is comprised of a conductive chip bonding pad and several packaging pins, be provided with several weld pads on chip in described integrated antenna package, described weld pad is by bonding wire and chip bonding pad electrical connection, and described chip bonding pad is by bonding wire and packaging pin electrical connection.
Described weld pad comprises power supply weld pad, ground connection weld pad and signal weld pad, in described integrated antenna package on chip, by one or some bonding wires power supply weld pad with same level, or the ground connection weld pad of same level, perhaps one or more signal weld pads and described chip bonding pad electrical connection.
In described integrated antenna package, chip sticks on described chip bonding pad by insulating cement.
the invention has the beneficial effects as follows: because described a kind of integrated antenna package comprises a packaging frame, and chip in one or more integrated antenna packages, described packaging frame is comprised of a conductive chip bonding pad and several packaging pins, be provided with several weld pads on chip in described integrated antenna package, described weld pad is by bonding wire and chip bonding pad electrical connection, described chip bonding pad is by bonding wire and packaging pin electrical connection, so, the present invention can satisfy the weld pad of chip in integrated antenna package by chip bonding pad and packaging pin electrical connection, thereby reduce the packaging pin number, avoid holding wire across chip package, reduce the encapsulation fraction defective, strengthen the alternative of signal pins position, reach the purpose that reduces packaging cost and application cost.
Description of drawings
Fig. 1 is the integrated antenna package physical connection schematic diagram of existing encapsulation;
Fig. 2 is cutaway view of the present invention;
Fig. 3 is the integrated antenna package physical connection schematic diagram in the present invention.
Embodiment
As shown in Figure 2, the present embodiment provides a kind of integrated antenna package.Generally include one or more power supply weld pad PAD, one or more ground weld pad PAD, a plurality of signal weld pad PAD in integrated circuit (IC) chip.By chip bonding pad, can realize:
1, the ejusdem generis adjacent or non-conterminous power supply PAD conducting that can be connected;
2, the ejusdem generis adjacent or non-conterminous ground PAD conducting that can be connected;
3, according to the demand of function definition, adjacent or non-conterminous two or more signal PAD, signal PAD and power supply PAD, signal PAD and the ground PAD conducting that can be connected.
Because chip bonding pad has certain area and thickness, the electric capacity of itself, resistance and inductance characteristic determine that it can not have destructive negative effect as the electrical communication conductor to the integrated circuit (IC) chip performance characteristics.
The solution of the present invention is as follows: comprise a packaging frame, and chip 1 in one or more integrated antenna package.Described packaging frame is comprised of a conductive chip bonding pad 2 and several packaging pins 3, be provided with several weld pads PAD on chip 1 in described integrated antenna package, described weld pad PAD is by bonding wire 4 and chip bonding pad 2 electrical connections, and described chip bonding pad 2 is by bonding wire 4 and packaging pin 3 electrical connections.Described weld pad PAD comprises power supply weld pad, ground connection weld pad and signal weld pad, in described integrated antenna package on chip 1, by one or some bonding wires power supply weld pad with same level, or the ground connection weld pad of same level, perhaps one or more signal weld pads and 2 electrical connections of described chip bonding pad.
Affect the electrical characteristic of chip 1 substrate in integrated antenna package for fear of the electrical characteristic of chip bonding pad 2, finally 1 functional circuit of chip in integrated antenna package is caused a devastating effect, the present invention pastes by insulating cement 5 between chip 1 and chip bonding pad 2 in integrated antenna package.In integrated antenna package, the weld pad PAD of chip 1 follows chip bonding pad 2 to connect by bonding wire, and chip bonding pad 2 connects with packaging pin 3 by other bonding wire 4, has realized that indirectly the weld pad PAD of chip 1 in integrated antenna package is with the connection of packaging pin 3.
As shown in Figure 3, weld pad PAD58 in described integrated antenna package on chip 1 directly is connected by the packaging pin 15 of bonding wire with the periphery, and weld pad PAD9 first is connected with described chip bonding pad by the bonding wire I, be connected with described weld pad PAD58 by the bonding wire II again, thereby two weld pads having realized same level are connected with same pin.
The present invention can be applicable to the circuit package technical field.
Claims (3)
1. integrated antenna package, it is characterized in that: described a kind of integrated antenna package comprises
One packaging frame, and
Chip in one or more integrated antenna packages;
Described packaging frame is comprised of a conductive chip bonding pad and several packaging pins, be provided with several weld pads on chip in described integrated antenna package, described weld pad is by bonding wire and chip bonding pad electrical connection, and described chip bonding pad is by bonding wire and packaging pin electrical connection.
2. a kind of integrated antenna package according to claim 1, it is characterized in that: described weld pad comprises power supply weld pad, ground connection weld pad and signal weld pad, in described integrated antenna package on chip, by one or some bonding wires power supply weld pad with same level, or the ground connection weld pad of same level, perhaps one or more signal weld pads and described chip bonding pad electrical connection.
3. a kind of integrated antenna package according to claim 1 and 2 is characterized in that: in described integrated antenna package, chip sticks on described chip bonding pad by insulating cement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100367410A CN103117263A (en) | 2013-01-31 | 2013-01-31 | Integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100367410A CN103117263A (en) | 2013-01-31 | 2013-01-31 | Integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103117263A true CN103117263A (en) | 2013-05-22 |
Family
ID=48415598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013100367410A Pending CN103117263A (en) | 2013-01-31 | 2013-01-31 | Integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103117263A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104684250A (en) * | 2013-11-27 | 2015-06-03 | 广东美的制冷设备有限公司 | Package structure of integrated circuit chip of printed circuit board and package design method |
| CN106098672A (en) * | 2016-06-20 | 2016-11-09 | 东莞市联洲知识产权运营管理有限公司 | A kind of integrated antenna package of improvement |
| CN106803502A (en) * | 2016-12-29 | 2017-06-06 | 广州凯耀资产管理有限公司 | A kind of integrated circuit package structure |
| CN110752197A (en) * | 2019-09-30 | 2020-02-04 | 华为技术有限公司 | Lead frame, packaged integrated circuit board, power supply chip and packaging method of circuit board |
| WO2020097767A1 (en) * | 2018-11-12 | 2020-05-22 | 北京比特大陆科技有限公司 | Circuit board and supercomputing equipment |
| CN115410935A (en) * | 2022-08-30 | 2022-11-29 | 江苏泰治科技股份有限公司 | Wiring method and system for avoiding cross of bonding wires during packaging of IC chip |
| CN116525594A (en) * | 2023-07-03 | 2023-08-01 | 成都爱旗科技有限公司 | Packaging structure, packaging method and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2006005383A (en) * | 2005-09-15 | 2006-01-05 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
| CN101404279A (en) * | 2008-11-11 | 2009-04-08 | 华亚微电子（上海）有限公司 | Multi-chip 3D stacking and packaging structure |
| CN201946589U (en) * | 2010-12-22 | 2011-08-24 | 宇芯（成都）集成电路封装测试有限公司 | Improved lead frame |
| CN202957237U (en) * | 2012-12-11 | 2013-05-29 | 中芯国际集成电路制造(北京)有限公司 | Chip encapsulation structure |
-
2013
- 2013-01-31 CN CN2013100367410A patent/CN103117263A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006005383A (en) * | 2005-09-15 | 2006-01-05 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
| CN101404279A (en) * | 2008-11-11 | 2009-04-08 | 华亚微电子（上海）有限公司 | Multi-chip 3D stacking and packaging structure |
| CN201946589U (en) * | 2010-12-22 | 2011-08-24 | 宇芯（成都）集成电路封装测试有限公司 | Improved lead frame |
| CN202957237U (en) * | 2012-12-11 | 2013-05-29 | 中芯国际集成电路制造(北京)有限公司 | Chip encapsulation structure |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104684250A (en) * | 2013-11-27 | 2015-06-03 | 广东美的制冷设备有限公司 | Package structure of integrated circuit chip of printed circuit board and package design method |
| CN106098672A (en) * | 2016-06-20 | 2016-11-09 | 东莞市联洲知识产权运营管理有限公司 | A kind of integrated antenna package of improvement |
| CN106803502A (en) * | 2016-12-29 | 2017-06-06 | 广州凯耀资产管理有限公司 | A kind of integrated circuit package structure |
| WO2020097767A1 (en) * | 2018-11-12 | 2020-05-22 | 北京比特大陆科技有限公司 | Circuit board and supercomputing equipment |
| CN110752197A (en) * | 2019-09-30 | 2020-02-04 | 华为技术有限公司 | Lead frame, packaged integrated circuit board, power supply chip and packaging method of circuit board |
| US11887918B2 (en) | 2019-09-30 | 2024-01-30 | Huawei Technologies Co., Ltd. | Lead frame, packaged integrated circuit board, power chip, and circuit board packaging method |
| CN115410935A (en) * | 2022-08-30 | 2022-11-29 | 江苏泰治科技股份有限公司 | Wiring method and system for avoiding cross of bonding wires during packaging of IC chip |
| CN115410935B (en) * | 2022-08-30 | 2023-09-26 | 江苏泰治科技股份有限公司 | Wiring method and system for preventing bonding wires from crossing during packaging of IC chip |
| CN116525594A (en) * | 2023-07-03 | 2023-08-01 | 成都爱旗科技有限公司 | Packaging structure, packaging method and electronic equipment |
| CN116525594B (en) * | 2023-07-03 | 2023-10-13 | 成都爱旗科技有限公司 | Packaging structure, packaging method and electronic equipment |
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| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130522 |