CN116525594A - Packaging structure, packaging method and electronic equipment - Google Patents
Packaging structure, packaging method and electronic equipment Download PDFInfo
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- CN116525594A CN116525594A CN202310802725.1A CN202310802725A CN116525594A CN 116525594 A CN116525594 A CN 116525594A CN 202310802725 A CN202310802725 A CN 202310802725A CN 116525594 A CN116525594 A CN 116525594A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 106
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 54
- 238000005192 partition Methods 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 4
- 230000005672 electromagnetic field Effects 0.000 abstract description 7
- 230000000875 corresponding effect Effects 0.000 description 49
- 238000010586 diagram Methods 0.000 description 18
- 238000003780 insertion Methods 0.000 description 18
- 230000037431 insertion Effects 0.000 description 18
- 238000004891 communication Methods 0.000 description 13
- 230000009467 reduction Effects 0.000 description 10
- 238000010992 reflux Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000004590 computer program Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000001276 controlling effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The application discloses a packaging structure, a packaging method and electronic equipment, and relates to the technical field of radio frequency and digital-analog hybrid packaging. The packaging structure comprises: the packaging frame is provided with target ground pins which are respectively arranged at four vertex angles of the packaging frame; the four target ground pins are in short-circuit electrical contact with the off-chip network pins; the return path is changed, so that the loop area formed by the signal and the return is obviously reduced, the isolation between the interference signal and the sensitive signal passive link is obviously improved, and the signal quality can be improved; the packaging frame comprises an interference signal pin and a sensitive signal pin which correspond to the chip to be packaged; at least three ground network wires are arranged in the vertex angle area of the packaging frame corresponding to the target ground pin so as to isolate electromagnetic field interference between signals at two adjacent sides of the packaging, further improve isolation between interference signals and sensitive signals and improve high-speed and high-frequency signal quality.
Description
Technical Field
The application relates to the technical field of radio frequency and digital-analog hybrid packaging, in particular to a packaging structure, a packaging method and electronic equipment.
Background
For radio frequency and digital-analog hybrid miniaturized Quad Flat No-lead (QFN) package chips, the design index requirements of radio frequency interference and digital-analog interference are high, and the design index requirements of isolation index are high on passive indexes.
Four vertex angle non-pins (Pin) of a traditional low-cost and small-sized QFN package Frame (Frame) are distributed, the periphery of the package is distributed without ground pins, and all reflow of signal pins and power pins are required to be reflowed through a thermal welding disc (EPAD) in the middle of the package.
When the traditional QFN packaging chip is applied to a low-cost application scene of a 2-layer printed circuit board (Printed Circuit Board, PCB), a reflow loop of a cascading area of the packaging and the PCB is large, so that isolation or crosstalk indexes between an interference signal and a sensitive signal are obviously deteriorated, and high-frequency insertion loss of a high-speed signal and a high-frequency signal is obviously deteriorated.
Disclosure of Invention
The invention aims to provide a packaging structure, a packaging method and electronic equipment, which are used for solving the problems that the isolation degree or crosstalk index between an interference signal and a sensitive signal of the existing packaging chip is obviously deteriorated, and the high-frequency insertion loss of a high-speed signal and a high-frequency signal is obviously deteriorated.
In a first aspect, the present application provides a package structure, including a package frame, and target ground pins respectively arranged at four top corners of the package frame; the four target ground pins are in short-circuit electrical contact with the off-chip network pins;
the packaging frame comprises an interference signal pin and a sensitive signal pin which correspond to the chip to be packaged; the interference signal pin and the sensitive signal pin are arranged close to the corresponding target ground pin;
at least three ground network wires are arranged in the vertex angle area of the packaging frame corresponding to the target ground pin, and vertical partition walls are formed by the at least three ground network wires.
Under the condition of adopting the technical scheme, the packaging structure provided by the embodiment of the application comprises a packaging frame and target ground pins respectively distributed at four vertex angles of the packaging frame; the four target ground pins are in short-circuit electrical contact with the off-chip network pins; according to the packaging structure, the target ground pins are respectively arranged at the four vertex angles of the packaging frame, so that main reflux paths of interference signals and sensitive signals are pcb top-layer ground to the target ground pins corresponding to the packaging vertex angles, wiring is conducted from the packaging frame to the ground network, and finally, the bare chip in front of a single unit of a chip to be packaged is changed, namely, the reflux paths are changed, so that the loop area formed by the signals and the reflux is obviously reduced, the antenna effect between the key signals and the sensitive signals is weakened by the reduction of the loop area, the isolation between the interference signals and the sensitive signal passive links is obviously improved on the passive index, meanwhile, the parasitic inductance on the signal links is reduced by the reduction of the loop area, the problem of signal passive link insertion loss is facilitated, and further, the signal quality can be improved; the packaging frame comprises an interference signal pin and a sensitive signal pin which correspond to the chip to be packaged; the interference signal pin and the sensitive signal pin are arranged close to the corresponding target ground pin; at least three ground network wires are arranged in the vertex angle area of the packaging frame corresponding to the target ground pin, and at least three ground network wires form a vertical isolation wall so as to isolate electromagnetic field interference between signals at two adjacent sides of the packaging, further improve isolation between interference signals and sensitive signals and improve high-speed and high-frequency signal quality.
In one possible implementation manner, one end of the ground network routing is connected with the target ground pin, the other end of the ground network routing is connected with a part of the packaging frame corresponding to the vertex angle area, and at least three ground network routing layers are stacked up and down.
In one possible implementation, at least three ground network wirings are spaced above the target ground pins and the portion of the package frame corresponding to the vertex angle region.
In one possible implementation, the shape of the target ground pin includes at least one of a cylinder, a cube, a cuboid, a Y-shaped body, or a Z-shaped body.
In one possible implementation, the ground network wire is a wire made of a conductive material.
In a second aspect, the present application further provides a packaging method for preparing the packaging structure according to any one of the first aspect, where the packaging method includes:
setting target ground pins at four vertex angles of the packaging frame respectively;
controlling the four target ground pins to be in short-circuit electrical contact with the off-chip network pins;
setting an interference signal pin and a sensitive signal pin corresponding to a chip to be packaged in the packaging frame close to the corresponding target ground pin;
and arranging at least three ground network routing wires in the vertex angle area of the packaging frame corresponding to the target ground pin to form a vertical isolation wall.
In one possible implementation manner, the setting at least three ground network wires in the vertex angle area of the package frame corresponding to the target ground pin to form a vertical partition wall includes:
and arranging at least three ground network routing wires in an up-down stacking mode in the vertex angle area of the packaging frame corresponding to the target ground pin so as to form the vertical isolation wall.
In one possible implementation manner, the setting at least three ground network wires in the vertex angle area of the package frame corresponding to the target ground pin to form a vertical partition wall includes:
and setting at least three ground network routing lines in a vertex angle area of the packaging frame corresponding to the target ground pin in a spacing routing mode to form the vertical partition wall.
In one possible implementation manner, the setting at least three ground network wires in the vertex angle area of the package frame corresponding to the target ground pin to form a vertical partition wall includes:
and setting at least three ground network routing lines in a similar ground pin routing mode in the vertex angle area of the packaging frame corresponding to the target ground pin so as to form the vertical isolation wall.
The advantages of the packaging method provided in the second aspect are the same as those of the packaging structure described in the first aspect or any possible implementation manner of the first aspect, and are not described here in detail.
In a third aspect, the present application further provides an electronic device, including: one or more processors; and one or more machine-readable media having instructions stored thereon that, when executed by the one or more processors, cause performance of the packaging method described in any one of the possible implementations of the second aspect.
The electronic device provided in the third aspect has the same advantages as the packaging method described in the second aspect or any possible implementation manner of the second aspect, and is not described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1a shows a schematic top structure of a conventional QFN package provided in an embodiment of the present application;
fig. 1b shows a schematic bottom structure of a conventional QFN package provided by an embodiment of the present application;
fig. 1c shows a schematic 3D structure of a conventional QFN package according to an embodiment of the present application;
fig. 1d shows a schematic side view of a conventional QFN package according to an embodiment of the present application;
FIG. 2a illustrates a top plan view of a package structure provided by an embodiment of the present application;
FIG. 2b illustrates a bottom view of a package structure provided by embodiments of the present application;
FIG. 2c illustrates a side view of a package structure provided by an embodiment of the present application;
FIG. 2D illustrates a 3D view of a package structure provided by an embodiment of the present application;
FIG. 2e illustrates an enlarged view of the vertical partition wall in the area of the package structure M shown in FIG. 2d provided by an embodiment of the present application;
FIG. 3a illustrates a top plan view of another package structure provided by embodiments of the present application;
FIG. 3b illustrates a 3D view of another package structure provided by embodiments of the present application;
FIG. 3c illustrates a partial enlarged view of the area M of the package structure of FIG. 3b provided by an embodiment of the present application;
FIG. 4a illustrates a top plan view of yet another package structure provided by embodiments of the present application;
FIG. 4b illustrates a 3D view of yet another package structure provided by embodiments of the present application;
FIG. 4c illustrates a partial enlarged view of the area M of the package structure of FIG. 4b provided by an embodiment of the present application;
FIG. 5a illustrates a top plan view of yet another package structure provided by embodiments of the present application;
FIG. 5b illustrates a bottom view of yet another package structure provided by embodiments of the present application;
FIG. 5c illustrates a 3D view of yet another package structure provided by an embodiment of the present application;
FIG. 6a illustrates a top plan view of yet another package structure provided by embodiments of the present application;
FIG. 6b illustrates a bottom view of yet another package structure provided by embodiments of the present application;
FIG. 6c illustrates a 3D view of yet another package structure provided by an embodiment of the present application;
FIG. 7a is a schematic diagram illustrating isolation of non-target ground pins at a top corner of a package according to an embodiment of the present application;
FIG. 7b is a schematic diagram illustrating the isolation of a package corner targeted ground pin according to an embodiment of the present application;
fig. 8a shows a schematic diagram of comparison of signal link insertion loss corresponding to XTAL-IN a pin of a single chip microcomputer according to an embodiment of the present application;
fig. 8b is a schematic diagram illustrating comparison of an insertion loss of a radio frequency identification signal link according to an embodiment of the present application;
FIG. 9a is a schematic diagram of an isolation curve of a package corner targeted ground pin according to an embodiment of the present application;
FIG. 9b illustrates a schematic diagram of an isolation curve provided by embodiments of the present application where the package corners have targeted ground pins and have vertical isolation walls;
FIG. 9c is a schematic diagram illustrating a comparison of the insertion loss of an XTAL-IN signal link according to an embodiment of the disclosure;
fig. 10 shows a schematic flow chart of a packaging method according to an embodiment of the present application;
fig. 11 shows a schematic hardware structure of an electronic device according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a chip according to an embodiment of the present application.
Reference numerals:
101-packaging a frame; 102-a target ground pin; e-grounding network routing; 300-an electronic device; 310-a processor; 320-a communication interface; 330-memory; 340-communication lines; 400-chip; 440-bus system.
Detailed Description
In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In this application, the terms "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
Four vertex angle non-ground pins (Pin) of a traditional low-cost and small-sized QFN package Frame are distributed, the periphery of the package is distributed without the non-ground pins, and all the reflow of signal pins and power pins is required to be performed through an EPAD in the middle of the package. For example, referring to fig. 1a, a schematic top structure of a conventional QFN package provided by an embodiment of the present application is shown, fig. 1b illustrates a schematic bottom structure of a conventional QFN package provided by an embodiment of the present application, fig. 1c illustrates a schematic 3D structure of a conventional QFN package provided by an embodiment of the present application, fig. 1D illustrates a schematic side view of a conventional QFN package provided by an embodiment of the present application, and as indicated by z in fig. 1b, four corners of a Frame have no pins, and all signals and power supply reflow require an intermediate EPAD for reflow based on low cost and miniaturization considerations. For a two-layer PCB low-cost application scenario, the main return paths of the interference signals and the sensitive signals are as follows: the reflow path can cause a larger loop area formed by the signal and the reflow, the larger loop area can lead to the enhancement of the antenna effect of the interference signal and the sensitive signal, the obvious reduction of the isolation between the interference signal and the sensitive signal passive link on the passive index, and finally the increase of the interference risk.
When the QFN packaging chip is applied to a low-cost two-layer PCB scene, if the ground reflow is carried out by only relying on the intermediate EPAD, the reflow loop area of the packaging and PCB cascading area can be large due to the thicker PCB plate thickness, and the two problems can be brought: in the first aspect, the isolation or crosstalk index between the interfering signal and the sensitive signal may be significantly deteriorated, and in the second aspect, the high frequency insertion loss of the high speed and high frequency signal may be significantly deteriorated. Still further, referring to fig. 1a, n, the ground network routing for the four vertex angle areas of the Frame is sparse, which can affect the isolation between the signal ground network routing on two adjacent sides of the package. Based on this, the application provides a packaging structure and a packaging method, specifically as follows:
fig. 2a shows a top plan view of a package structure provided by an embodiment of the present application, fig. 2b shows a bottom plan view of a package structure provided by an embodiment of the present application, fig. 2c shows a side view of a package structure provided by an embodiment of the present application, fig. 2D shows a 3D view of a package structure provided by an embodiment of the present application, fig. 2e shows an enlarged view of vertical partition walls in an area of a package structure M shown in fig. 2D provided by an embodiment of the present application, as shown in fig. 2a, fig. 2b, fig. 2c, fig. 2D and fig. 2e, the package structure comprising: a package frame 101, and target ground pins 102 respectively arranged at four corners of the package frame 101; four of the target ground pins 102 are in short electrical contact with off-chip network pins;
the package frame 101 comprises an interference signal pin and a sensitive signal pin corresponding to a chip to be packaged; the interference signal pin and the sensitive signal pin are arranged close to the corresponding target ground pin;
at least three ground network wires E are arranged in the vertex angle area of the package frame corresponding to the target ground pin 102, and the at least three ground network wires E form a vertical partition wall.
In summary, the package structure provided in the embodiment of the present application includes a package frame, and target ground pins respectively arranged at four top corners of the package frame; the four target ground pins are in short-circuit electrical contact with the off-chip network pins; according to the packaging structure, the target ground pins are respectively arranged at the four vertex angles of the packaging frame, so that main reflux paths of interference signals and sensitive signals are pcb top-layer ground to the target ground pins corresponding to the packaging vertex angles, wiring is conducted from the packaging frame to the ground network, and finally, the bare chip in front of a single unit of a chip to be packaged is changed, namely, the reflux paths are changed, so that the loop area formed by the signals and the reflux is obviously reduced, the antenna effect between the key signals and the sensitive signals is weakened by the reduction of the loop area, the isolation between the interference signals and the sensitive signal passive links is obviously improved on the passive index, meanwhile, the parasitic inductance on the signal links is reduced by the reduction of the loop area, the problem of signal passive link insertion loss is facilitated, and further, the signal quality can be improved; the packaging frame comprises an interference signal pin and a sensitive signal pin which correspond to the chip to be packaged; the interference signal pin and the sensitive signal pin are arranged close to the corresponding target ground pin; at least three ground network wires are arranged in the vertex angle area of the packaging frame corresponding to the target ground pin, and at least three ground network wires form a vertical isolation wall so as to isolate electromagnetic field interference between signals at two adjacent sides of the packaging, and further improve isolation between interference signals and sensitive signals so as to improve high-speed and high-frequency signal quality.
In the application, at least three ground network routing lines are positioned on an approximately inclined straight line with a target ground pin at the top angle of the packaging frame, and the vertical isolation wall has a certain height and good isolation effect.
Optionally, as shown in fig. 2c, fig. 2d, and fig. 2E, one end of the ground network wire E is connected to the target ground pin 102, the other end of the ground network wire E is connected to a part of the package frame 101 corresponding to the vertex angle area, and at least three ground network wires E are stacked up and down.
Optionally, at least three ground network routing intervals E are disposed above the target ground pins 102 and the package frame 101 corresponding to the vertex angle area.
For example, fig. 3a shows a top plan view of another package structure provided by an embodiment of the present application, fig. 3b shows a 3D diagram of another package structure provided by an embodiment of the present application, fig. 3c shows a partial enlarged view of an area M of the package structure of fig. 3b provided by an embodiment of the present application, and as shown in fig. 3a, fig. 3b and fig. 3c, at least three ground network wires E are arranged in a vertex angle area of the package frame corresponding to the target ground pin in a spaced wire bonding manner to form the vertical isolation wall, so as to isolate electromagnetic field interference between signals on two adjacent sides of the package, and further improve isolation between an interference signal and a sensitive signal; the impedance of the QFN package signal ground network wire is generally larger, and if the isolated ground network wire is close to the signal ground network wire, the impedance of the signal ground network wire can be properly reduced, and the signal quality can be improved.
As another example, fig. 4a shows a top plan view of another package structure provided by an embodiment of the present application, fig. 4b shows a 3D diagram of another package structure provided by an embodiment of the present application, fig. 4c shows a partial enlarged view of an area M of the package structure of fig. 4b provided by an embodiment of the present application, and as shown in fig. 4a, fig. 4b and fig. 4c, at least three ground network wires E are provided in a ground needle wire bonding mode in a vertex angle area of the package frame corresponding to the target ground pin to form the vertical isolation wall, so as to isolate electromagnetic field interference between signals on two adjacent sides of the package, and further improve isolation between an interference signal and a sensitive signal; the impedance of the QFN package signal ground network wire is generally larger, and if the isolated ground network wire is close to the signal ground network wire, the impedance of the signal ground network wire can be properly reduced, and the signal quality can be improved.
The specific number of the ground network routing is not limited, and the specific number of the ground network routing is positively correlated with the size of the actual packaging structure, so that specific setting can be performed according to actual application scenes.
Optionally, the shape of the target ground pin includes at least one of a cylinder, a cube, a cuboid, a Y-shaped body, or a Z-shaped body.
For example, referring to fig. 2b, the destination pin 102 is shaped like a Y-letter.
For example, fig. 5a illustrates a top plan view of yet another package structure provided by an embodiment of the present application, fig. 5b illustrates a bottom plan view of yet another package structure provided by an embodiment of the present application, and fig. 5c illustrates a 3D view of yet another package structure provided by an embodiment of the present application, as shown in fig. 5a, 5b, and 5c, where the shape of the destination pin 102 is a cylinder.
For example, fig. 6a shows a top plan view of a further package structure provided in an embodiment of the present application, fig. 6b shows a bottom plan view of the further package structure provided in an embodiment of the present application, fig. 6c shows a 3D view of the further package structure provided in an embodiment of the present application, and as shown in fig. 6a, fig. 6b and fig. 6c, the shape of the destination pin 102 is a cube, and the specific shape of the destination pin is not limited in this embodiment of the present application.
Optionally, the ground network wire bonding is wire bonding made of a conductor material, which may be, for example, copper, gold or other conductor materials.
Fig. 7a shows a schematic diagram of isolation of a package vertex without a target ground pin provided by the embodiment of the present application, fig. 7b shows a schematic diagram of isolation of a package vertex with a target ground pin provided by the embodiment of the present application, the horizontal axes of fig. 7a and fig. 7b are frequencies (Freq), units are gigahertz (GHz), the vertical axes represent isolation Y1, as can be seen from comparison of fig. 7a and fig. 7b, the isolation of the package vertex with a target ground pin is improved by 10db as a whole, db represents pure measurement units, no practical meaning is provided, and the isolation is improved significantly.
Fig. 8a shows a comparative schematic diagram of signal link insertion loss corresponding to XTAL-IN a pin of a single chip microcomputer provided by an embodiment of the present application, fig. 8b shows a comparative schematic diagram of signal link insertion loss of Radio Frequency Identification (RFIO) provided by an embodiment of the present application, and horizontal axes of fig. 8a and fig. 8b are frequencies IN gigahertz (GHz), vertical axes represent insertion loss IN dB, and dB represents pure measurement units without practical meaning. In fig. 8a, the curve corresponding to the corner non-target ground pin is T1, the curve corresponding to the corner non-target ground pin is T2, the curve corresponding to the corner non-target ground pin is T3, and the curve corresponding to the corner target ground pin is T4, as can be seen from fig. 8a, the insertion loss is reduced by 0.09dB/2.4GHz, compared with the absolute insertion loss value of 0.43dB/2.4GHz, the insertion loss reduction gain is obvious, the insertion loss is reduced, the signal external radiation loss is reduced, and the signal quality can be improved.
Fig. 9a shows a schematic diagram of an isolation curve of a targeted ground pin at a package vertex angle provided by an embodiment of the present application, fig. 9b shows a schematic diagram of an isolation curve of a targeted ground pin at a package vertex angle and having a vertical isolation wall provided by an embodiment of the present application, the horizontal axes of fig. 9a and fig. 9b are frequencies, the unit is gigahertz (GHz), the vertical axes represent isolation, fig. 9c shows a comparative schematic diagram of an XTAL-IN signal link loss provided by an embodiment of the present application, the unit is gigahertz (GHz), the vertical axes represent insertion loss, the unit is dB, dB represents a pure measurement unit, and there is no practical meaning, it is known from fig. 9a and fig. 9b that the isolation is further improved by 2dB/2.4GHz, the isolation is improved by 12dB/2.4GHz relative to the isolation of fig. 9a, the isolation is significantly improved, the curve corresponding to the targeted ground pin at the vertex angle IN fig. 9c is T5, the curve corresponding to the targeted ground pin at the vertex angle and the vertical isolation wall is T6, and the signal line is improved after the signal line is beaten to the signal line is beaten.
In summary, the package structure provided in the embodiment of the present application includes a package frame, and target ground pins respectively arranged at four top corners of the package frame; the four target ground pins are in short-circuit electrical contact with the off-chip network pins; according to the packaging structure, the target ground pins are respectively arranged at the four vertex angles of the packaging frame, so that main reflux paths of interference signals and sensitive signals are pcb top-layer ground to the target ground pins corresponding to the packaging vertex angles, wiring is conducted from the packaging frame to the ground network, and finally, the bare chip in front of a single unit of a chip to be packaged is changed, namely, the reflux paths are changed, so that the loop area formed by the signals and the reflux is obviously reduced, the antenna effect between the key signals and the sensitive signals is weakened by the reduction of the loop area, the isolation between the interference signals and the sensitive signal passive links is obviously improved on the passive index, meanwhile, the parasitic inductance on the signal links is reduced by the reduction of the loop area, the problem of signal passive link insertion loss is facilitated, and further, the signal quality can be improved; the packaging frame comprises an interference signal pin and a sensitive signal pin which correspond to the chip to be packaged; the interference signal pin and the sensitive signal pin are arranged close to the corresponding target ground pin; at least three ground network wires are arranged in the vertex angle area of the packaging frame corresponding to the target ground pin, and at least three ground network wires form a vertical separation wall so as to isolate electromagnetic field interference between signals at two adjacent sides of the packaging, and further improve the isolation between interference signals and sensitive signals so as to improve the signal quality.
Fig. 10 is a schematic flow chart of a packaging method according to an embodiment of the present application, for preparing the packaging structure of any one of fig. 2a to 6c, as shown in fig. 10, where the method includes:
step 201: setting target ground pins at four vertex angles of the packaging frame respectively;
step 202: controlling the four target ground pins to be in short-circuit electrical contact with the off-chip network pins;
step 203: setting an interference signal pin and a sensitive signal pin corresponding to a chip to be packaged in the packaging frame close to the corresponding target ground pin;
step 204: and arranging at least three ground network routing wires in the vertex angle area of the packaging frame corresponding to the target ground pin to form a vertical isolation wall.
And arranging at least three ground network routing wires in an up-down stacking mode in the vertex angle area of the packaging frame corresponding to the target ground pin so as to form the vertical isolation wall.
And setting at least three ground network routing lines in a vertex angle area of the packaging frame corresponding to the target ground pin in a spacing routing mode to form the vertical partition wall.
And setting at least three ground network routing lines in a similar ground pin routing mode in the vertex angle area of the packaging frame corresponding to the target ground pin so as to form the vertical isolation wall.
In summary, in the packaging method provided by the embodiment of the present application, the target ground pins are respectively disposed at four top corners of the packaging frame; controlling the four target ground pins to be in short-circuit electrical contact with the off-chip network pins; setting an interference signal pin and a sensitive signal pin corresponding to a chip to be packaged in the packaging frame close to the corresponding target ground pin; setting at least three ground network routing lines in the vertex angle area of the packaging frame corresponding to the target ground pins to form a vertical isolation wall, wherein the target ground pins are respectively arranged at the four vertex angles of the packaging frame, so that the main return paths of interference signals and sensitive signals are pcb top-layer ground to the target ground pins corresponding to the packaging vertex angles, the package frame is routed to the ground network, and finally the bare chip before a single unit of a chip to be packaged is changed, namely the return paths are changed, so that the loop area formed by the signals and the return flow is obviously reduced, the antenna effect between key signals and sensitive signals is weakened by the reduction of the loop area, the isolation between the interference signals and the sensitive signals is obviously improved on the passive indexes, meanwhile, the parasitic inductance on the signal links is reduced by the reduction of the loop area, the signal passive link insertion loss problem is facilitated, and the signal quality is further improved; at least three ground network wires are arranged in the vertex angle area of the packaging frame corresponding to the target ground pin, and at least three ground network wires form a vertical isolation wall so as to isolate electromagnetic field interference between signals at two adjacent sides of the packaging, and further improve isolation between interference signals and sensitive signals so as to improve high-speed and high-frequency signal quality.
The encapsulation method provided in the present application may prepare an encapsulation structure as shown in any one of fig. 2a to 6c, and in order to avoid repetition, a description thereof will not be repeated here.
The electronic device in the embodiment of the application may be an apparatus, or may be a component, an integrated circuit, or a chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. By way of example, the mobile electronic device may be a cell phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, wearable device, ultra-mobile personal computer (ultra-mobile personal computer, UMPC), netbook or personal digital assistant (personal digital assistant, PDA), etc., and the non-mobile electronic device may be a server, network attached storage (Network ATTached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., and the embodiments of the present application are not limited in particular.
The electronic device in the embodiment of the application may be a device having an operating system. The operating system may be an Android operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.
Fig. 11 shows a schematic hardware structure of an electronic device according to an embodiment of the present application. As shown in fig. 11, the electronic device 300 includes a processor 310.
As shown in FIG. 11, the processor 310 may be a general purpose central processing unit (central processing unit, CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the programs of the present application.
As shown in fig. 11, the electronic device 300 may further include a communication line 340. Communication line 340 may include a path to communicate information between the components described above.
Optionally, as shown in fig. 11, the electronic device may further include a communication interface 320. The communication interface 320 may be one or more. The communication interface 320 may use any transceiver-like device for communicating with other devices or communication networks.
Optionally, as shown in fig. 11, the electronic device may further include a memory 330. Memory 330 is used to store computer-executable instructions for performing aspects of the present application and is controlled by the processor for execution. The processor is configured to execute computer-executable instructions stored in the memory, thereby implementing the method provided in the embodiments of the present application.
As shown in fig. 11, the memory 330 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), a compact disc (compact disc read-only memory) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto. Memory 330 may be a stand-alone device coupled to processor 310 via communication line 340. Memory 330 may also be integrated with processor 310.
Alternatively, the computer-executable instructions in the embodiments of the present application may be referred to as application program codes, which are not specifically limited in the embodiments of the present application.
In a particular implementation, as one embodiment, as shown in FIG. 11, processor 310 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 11.
In a specific implementation, as an embodiment, as shown in fig. 11, the terminal device may include a plurality of processors, such as the processors in fig. 11. Each of these processors may be a single-core processor or a multi-core processor.
Fig. 12 is a schematic structural diagram of a chip according to an embodiment of the present application. As shown in fig. 12, the chip 400 includes one or more (including two) processors 310.
Optionally, as shown in fig. 12, the chip further includes a communication interface 320 and a memory 330, and the memory 330 may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (non-volatile random access memory, NVRAM).
In some implementations, as shown in FIG. 12, the memory 330 stores elements, execution modules or data structures, or a subset thereof, or an extended set thereof.
In the embodiment of the present application, as shown in fig. 12, by calling an operation instruction stored in the memory (the operation instruction may be stored in the operating system), a corresponding operation is performed.
As shown in fig. 12, the processor 310 controls the processing operation of any one of the terminal devices, and the processor 310 may also be referred to as a central processing unit (central processing unit, CPU).
As shown in fig. 12, memory 330 may include read-only memory and random access memory and provides instructions and data to the processor. A portion of the memory 330 may also include NVRAM. Such as a memory, a communication interface, and a memory coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. But for clarity of illustration the various buses are labeled as bus system 440 in fig. 12.
As shown in fig. 12, the method disclosed in the embodiment of the present application may be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The processor may be a general purpose processor, a digital signal processor (digital signal processing, DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.
In one aspect, a computer readable storage medium is provided, in which instructions are stored, which when executed, implement the functions performed by the terminal device in the above embodiments.
In one aspect, a chip is provided, where the chip is applied to a terminal device, and the chip includes at least one processor and a communication interface, where the communication interface is coupled to the at least one processor, and the processor is configured to execute instructions to implement the functions performed by the packaging method in the above embodiment.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user equipment, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, e.g., floppy disk, hard disk, tape; optical media, such as digital video discs (digital video disc, DVD); but also semiconductor media such as solid state disks (solid state drive, SSD).
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the present application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to include such modifications and variations as well.
Claims (10)
1. The packaging structure is characterized by comprising a packaging frame and target ground pins respectively distributed at four vertex angles of the packaging frame; the four target ground pins are in short-circuit electrical contact with the off-chip network pins;
the packaging frame comprises an interference signal pin and a sensitive signal pin which correspond to the chip to be packaged; the interference signal pin and the sensitive signal pin are arranged close to the corresponding target ground pin;
at least three ground network wires are arranged in the vertex angle area of the packaging frame corresponding to the target ground pin, and vertical partition walls are formed by the at least three ground network wires.
2. The package structure according to claim 1, wherein one end of the ground network routing is connected to the target ground pin, the other end of the ground network routing is connected to a portion of the package frame corresponding to the vertex angle area, and at least three ground network routing layers are stacked one above the other.
3. The package structure of claim 1, wherein at least three ground network routing lines are disposed above the portion of the package frame corresponding to the target ground pins and the vertex angle area.
4. The package structure of claim 1, wherein the shape of the target ground pin comprises at least one of a cylinder, a cube, a cuboid, a Y-shaped body, or a Z-shaped body.
5. The package structure of any one of claims 1 to 4, wherein the ground network wire is a wire made of a conductive material.
6. A packaging method for preparing the packaging structure of any one of claims 1 to 5, comprising:
setting target ground pins at four vertex angles of the packaging frame respectively;
controlling the four target ground pins to be in short-circuit electrical contact with the off-chip network pins;
setting an interference signal pin and a sensitive signal pin corresponding to a chip to be packaged in the packaging frame close to the corresponding target ground pin;
and arranging at least three ground network routing wires in the vertex angle area of the packaging frame corresponding to the target ground pin to form a vertical isolation wall.
7. The packaging method according to claim 6, wherein the arranging at least three ground network wires in the vertex angle area of the packaging frame corresponding to the target ground pin to form a vertical partition wall comprises:
and arranging at least three ground network routing wires in an up-down stacking mode in the vertex angle area of the packaging frame corresponding to the target ground pin so as to form the vertical isolation wall.
8. The packaging method according to claim 6, wherein the arranging at least three ground network wires in the vertex angle area of the packaging frame corresponding to the target ground pin to form a vertical partition wall comprises:
and setting at least three ground network routing lines in a vertex angle area of the packaging frame corresponding to the target ground pin in a spacing routing mode to form the vertical partition wall.
9. The packaging method according to claim 6, wherein the arranging at least three ground network wires in the vertex angle area of the packaging frame corresponding to the target ground pin to form a vertical partition wall comprises:
and setting at least three ground network routing lines in a similar ground pin routing mode in the vertex angle area of the packaging frame corresponding to the target ground pin so as to form the vertical isolation wall.
10. An electronic device, comprising: one or more processors; and one or more machine readable media having instructions stored thereon, which when executed by the one or more processors, cause performance of the packaging method of any of claims 6 to 9.
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| CN202310802725.1A CN116525594B (en) | 2023-07-03 | 2023-07-03 | Packaging structure, packaging method and electronic equipment |
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