CN205319148U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
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- CN205319148U CN205319148U CN201521055419.3U CN201521055419U CN205319148U CN 205319148 U CN205319148 U CN 205319148U CN 201521055419 U CN201521055419 U CN 201521055419U CN 205319148 U CN205319148 U CN 205319148U
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- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 229910000679 solder Inorganic materials 0.000 claims abstract description 81
- 230000001815 facial effect Effects 0.000 claims abstract description 3
- 239000003990 capacitor Substances 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 45
- 239000003792 electrolyte Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 2
- 230000015654 memory Effects 0.000 description 8
- 238000004891 communication Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a semiconductor package. Semiconductor package can include the base plate, the base plate includes: the sandwich layer, its possess arrange have a plurality of first faces that weld the finger and with the second face of first facial features to showing a plurality of solder ball bonding dishes side by side, and a connecting terminal and the 2nd connecting terminal, they form and do part each other and run through in the sandwich layer first face reaches the second face. Semiconductor package can include the condenser, the condenser dispose in the inside of the sandwich layer of base plate, and possess the electrode, the electrode configure into respectively with a connecting terminal reaches the contact of the 2nd connecting terminal. Semiconductor package can include conductive parts, conductive parts will a connecting terminal reaches the 2nd connecting terminal connect in the electrode of condenser.
Description
Technical field
This utility model relates to semiconductor package body, more particularly, to the semiconductor package body including capacitor.
Background technology
Along with many people carry out the various operations to storage and appreciation HD video of the surfing from network by the such mobile equipment of smart mobile phone and panel computer, require the mobile equipment of higher performance, correspondingly, the performance of the semiconductor device constituting mobile equipment becomes extremely important, and wherein especially the performance of memory semiconductor becomes even more important.
It addition, in the high performance mobile equipment being equipped with memory semiconductor, require necessary built-in capacitor to strengthen power characteristic, thus, it is intended to and research and develop the various technology for the inside built-in capacitor in semiconductor package body.
Utility model content
Embodiment of the present utility model provides the semiconductor package body of the restriction of a kind of capacitor configuration space that can overcome the package interior caused because of the realization of the increase of die size and high stacking (highstack).
Semiconductor package body in embodiment comprises the steps that substrate, it includes sandwich layer, the first connection terminal and second connects terminal, described sandwich layer possess first that is arranged with that multiple weldering refers to and with described first relative and be arranged with second of multiple solder ball pad, described first connects terminal and described second connects terminal and is formed as being separated from each other and run through described first and described second in described sandwich layer; Capacitor, it is configured at the inside of sandwich layer of described substrate, and possesses electrode, and described electrode is configured to be connected terminal and described second respectively with described first and connects termination contact; And conductive component, described first connection terminal and described second are connected terminal and are connected to the electrode of described capacitor by it.
Have employed the controller that the electronic system of the semiconductor package body in embodiment includes being combined by bus, interface, input/output unit and storage device, described controller and storage device can include semiconductor package body, this semiconductor package body includes: substrate, it includes sandwich layer, first connects terminal and second connects terminal, described sandwich layer possess first that is arranged with that multiple weldering refers to and with described first relative and be arranged with second of multiple solder ball pad, described first connection terminal and described second connects terminal and is formed as being separated from each other and run through described first and described second in described sandwich layer,Capacitor, it is configured at the inside of sandwich layer of described substrate, and possesses electrode, and described electrode is configured to be connected terminal and described second respectively with described first and connects termination contact; And conductive component, described first connection terminal and described second are connected terminal and are connected to the electrode of described capacitor by it.
Storage card including the semiconductor package body in embodiment includes: memorizer, and it includes semiconductor package body; And storage control, described memorizer is controlled by it, described semiconductor package body comprises the steps that substrate, it includes sandwich layer, the first connection terminal and second connects terminal, described sandwich layer possess first that is arranged with that multiple weldering refers to and with described first relative and be arranged with second of multiple solder ball pad, described first connects terminal and described second connects terminal and is formed as being separated from each other and run through described first and described second in described sandwich layer; Capacitor, it is configured at the inside of sandwich layer of described substrate, and possesses electrode, and described electrode is configured to be connected terminal and described second respectively with described first and connects termination contact; And conductive component, described first connection terminal and described second are connected terminal and are connected to the electrode of described capacitor by it.
In semiconductor package body in an embodiment, described substrate also includes: the first solder resist, and it is formed on first of described sandwich layer in the way of making described weldering refer to expose; And second solder resist, its by make described solder ball pad, described first connect terminal, described second connect terminal and described capacitor expose in the way of formed on second of described sandwich layer.
In semiconductor package body in an embodiment, described sandwich layer includes from second of the described sandwich layer groove formed, and is configured with described first and connects terminal, described second connection terminal and described capacitor in described groove.
In semiconductor package body in an embodiment, described first connection terminal and described second connects terminal and is arranged in the relative sidewall in described groove and on another sidewall, and described capacitor is with built-in described first connection terminal and described second bottom surface being connected between terminal being arranged in described groove.
In semiconductor package body in an embodiment, described first connection terminal and described second link attached bag are drawn together the first extension and the second extension, described first extension and described second extension and toward each other and are extended to the second face portion of described sandwich layer respectively and configure.
In semiconductor package body in an embodiment, described first extension includes: the first ball pattern, and it is connected terminal separate configuration with described first; And at least more than one the first connecting portion, they connect described first ball pattern and are connected between terminal with described first, and described second extension includes: the second ball pattern, and it is connected terminal separate configuration with described second; And at least more than one the second connecting portion, they connect described second ball pattern and are connected between terminal with described second.
In semiconductor package body in an embodiment, described first connection terminal and described second link attached bag are drawn together the first electrode portion and the second electrode portion, described first electrode portion and described second electrode portion and are divided extension to configure toward each other and respectively to the first facial of described sandwich layer.
In semiconductor package body in an embodiment, described capacitor includes: the first electrode, and it is configured to be connected termination contact with described first; Second electrode, it is configured to be connected termination contact with described second;And electrolyte, it is between described first electrode and described second electrode.
In semiconductor package body in an embodiment, in the edge of second of described sandwich layer, be not configured with the part of described solder ball pad, configure at least more than one described capacitor.
In semiconductor package body in an embodiment, described conductive component includes solder.
In semiconductor package body in an embodiment, described semiconductor package body also includes: semiconductor chip, it possesses the active face being arranged with multiple pad at edge and the lower surface relative with described active face, and makes described lower surface relative with the upper surface of the described substrate corresponding to first of described sandwich layer; Connection member, the weldering of described substrate is referred to electrically connect with the pad of described semiconductor chip by it; Seal member, it is to be formed on the upper surface of described substrate in the way of covering described semiconductor chip and connection member; And solder ball, it is formed on the solder ball pad of described substrate.
In semiconductor package body in an embodiment, described connection member includes sealing wire.
In semiconductor package body in an embodiment, described semiconductor chip tegillum is laminated with at least more than one.
In semiconductor package body in an embodiment, described semiconductor chip includes the stacking of memory chip or the stacking of memory chip and logic chip.
Accompanying drawing explanation
Fig. 1 indicates that the sectional view of the semiconductor package body in embodiment.
The top view of the capacitor of the semiconductor package body that Fig. 2 is an illustration in embodiment.
Fig. 3 is the sectional view illustrated along the A-A' line incision of Fig. 2.
The top view of the capacitor of the semiconductor package body that Fig. 4 A and Fig. 4 B is an illustration in embodiment and sectional view.
Fig. 5 indicates that the substrate of the semiconductor package body in embodiment and the sectional view of capacitor.
Fig. 6 is the block diagram of the electronic system that have employed the semiconductor package body according to various embodiments.
Fig. 7 indicates that the block diagram of the storage card including the semiconductor package body according to various embodiments.
Detailed description of the invention
Below, with reference to accompanying drawing, preferred embodiment of the present utility model is described in detail.
Referring to figs. 1 through Fig. 3, the semiconductor package body 100 in embodiment comprises the steps that substrate 40, capacitor 50, semiconductor chip 60, connection member 70, seal member 80 and solder ball (solderball) 90.
Described substrate 40 comprises the steps that sandwich layer 10, multiple weldering refer to that (bondfinger) 22 and solder ball pad (ballland) 24, first connect terminal 26 and second and connect terminal the 28, first solder resist 32 and the second solder resist 34. Although it is not shown, but substrate 40 may also include that circuit pattern, it is formed on first 10a and second 10b of sandwich layer 10; And path pattern (viapattern), it is formed in the inside of sandwich layer 10, will be formed in the circuit pattern electrical connection on first 10a and second 10b of described sandwich layer 10.
Sandwich layer 10 can be made up of megohmite insulant, and is formed as including being equivalent to first 10a of upper surface and relative with first 10a and be equivalent to the tetragon tabular of second 10b of lower surface. It addition, sandwich layer 10 can include from its second 10b at least more than one groove H formed.
In an embodiment, groove H-shaped becomes in the part configuring capacitor 50, can in the edge of the second of sandwich layer 10 10b, the part that is not pasted with solder ball 90 be namely not configured with the part of solder ball pad 24, form more than one groove H.Such as, when overlooking, groove H has the size that lateral length × longitudinal length is 1,100 μm～1,300 μ m 600 μm～800 μm, it is preferable that can possess the size of 1,200 μ m 700 μm.
Weldering refers to that 22 is the part electrically connected with the semiconductor chip 60 on the upper surface being arranged in substrate 40, can arrange multiple weldering and refer to 22 on first 10a of sandwich layer 10. Such weldering refers to the end section of 22 circuit patterns that can be formed on first 10a of sandwich layer 10, and can possess the confined form according to the first solder resist 32 formed on first 10a of sandwich layer 10.
Solder ball pad 24 is the part electrically connected with the motherboard of external circuit such as module substrate or system via the such external connection terminals of solder ball 90, can arrange multiple solder ball pad 24 on second 10b of sandwich layer 10. The end section of the circuit pattern that such solder ball pad 24 can be formed on second 10b of sandwich layer 10, and can possess the confined form according to the second solder resist 34.
Although it is not shown, but be arranged in the weldering of first 10a of sandwich layer 10 and refer to that 22 and can be formed at the path pattern of inside of sandwich layer 10 by being respectively formed in the circuit pattern of first 10a and second 10b of sandwich layer 10 and are electrically connected to each other with the solder ball pad 24 of second 10b being arranged in sandwich layer 10.
First connection terminal 26 and the second connection terminal 28 are arranged to electrically connect with capacitor 50, and first connects terminal 26 and second connects terminal 28 on the relative sidewall being formed in groove H in the way of extending through first 10a and second 10b of sandwich layer 10 and another sidewall. In an embodiment, connect terminal 26 by the first of configuration capacitor 50 and the second connection terminal 28 part can be etched prescribed depth degree.
First connects terminal 26 and second connects the extension 27,29 that terminal 28 can include toward each other and extend to second 10b part of sandwich layer 10 respectively and configure. The first ball pattern 27a that first extension 27 can include being connected terminal 26 separate configuration with first and connect terminal 26 and the first ball pattern 27a the first connecting portion 27b being connected by first, the second ball pattern 29a that the second extension 29 can include being connected terminal 28 separate configuration with second and by the second connection terminal 28 and the second ball pattern 29a the second connecting portion 29b being connected.
In an embodiment, when overlooking, first connects terminal 26 and second connects terminal 28 and possesses the width w of 600 μm～800 μm (being preferably 700 μm) and the thickness t of 300 μm～400 μm (being preferably 350 μm), and is separated from each other configuration with the interval s of 450 μm～550 μm (being preferably 500 μm). First ball pattern 27a and the second ball pattern 29a possesses and solder ball pad 24 same shape and size, and separately configures to the first outside connecting terminal 26 and the second connection terminal 28 with the interval d of 300 μm～500 μm of degree respectively. First connecting portion 27b and the second connecting portion 29b is respectively formed with two, to connect between the first connection terminal 26 with the first ball pattern 27a and second to be connected between terminal 28 and the second ball pattern 29a.
First connects terminal 26 and second connects electrode portion 27c, 29c that terminal 28 may also include toward each other and extends to first 10a part of sandwich layer 10 respectively and configure. Electrode portion 27c, 29c can be used as the electric connection terminal between other circuit in the semiconductor package body 100 of embodiment.
Although it is not shown, but the first connecting portion 27b and the second connecting portion 29b can be omitted, in this case, the first ball pattern 27a and the second ball pattern 29b can be connected terminal 26 respectively with corresponding first and the second connection terminal 28 configures or contiguously to be at utmost adjacent to configuration.
Forming the circuit pattern at each face 10a, 10b to protect, the first solder resist 32 and the second solder resist 34 are respectively formed on first 10a and second 10b of sandwich layer 10. First solder resist 32 and the second solder resist 34 are formed as respectively on the first of sandwich layer 10 10a and second 10b: make multiple weldering refer to 22 and multiple solder ball pad 24 expose, the groove H being configured with the first extension 27 and second extension the 29, first connection terminal 26 and the second connection terminal 28 is made to expose, wherein, the first extension 27 and the second extension 29 include the first ball pattern 27a and the second ball pattern 29a and the first connecting portion 27b and the second connecting portion 29b.
Then, described capacitor 50 is to arrange to strengthen the power characteristic of the semiconductor package body 100 in embodiment, described capacitor 50 can include the first electrode 51 and the second electrode 52 and the electrolyte 53 between described first electrode 51 and described second electrode 52, and, in the inside of the groove H being formed with the first connection terminal 26 and the second connection terminal 28 apart from each other, described capacitor 50 can be configured from the second of sandwich layer 10 10b with built-in (Embeddedtype).
As shown in fig. 4 a and fig. 4b, such capacitor 50 can by the such conductive component 96 of solder by the way of physics and be arranged in groove H to electrically, wherein, the such conductive component 96 of above-mentioned solder collectively forms with the solder ball 90 being attached on the solder ball pad 24 of second 10b being arranged in sandwich layer 10 as external connection terminals.
Specifically, capacitor 50 can by its first electrode 51 with first connect terminal 26 contact and its second electrode 52 with second connection terminal 28 contact in the way of be configured at inside groove H from second 10b of sandwich layer 10. Although it is not shown, but in order to easily carry out operation, capacitor 50 is attached in groove H by binding agent etc.
When having carried out known subsequent handling such as die bonding, lead-in wire engage and when moulding operation etc., the rear surface of substrate 40, the solder ball pad 24 being namely located at second 10b of sandwich layer 10 and the first ball pattern 27a and the second ball pattern 29a attach solder ball 90 and virtual solder (dummysolder) 95 respectively. Virtual solder 95 possesses substantially identical with solder ball 90 size and shape.
Then, the Reflow Soldering operation to solder ball 90 and virtual solder 95 is carried out. the result carrying out Reflow Soldering operation is as follows: the solder ball 90 being attached on solder ball pad 24 is formed with solder ball pad 24 and is firmly combined, on the contrary, the virtual solder 95 being attached on the first ball pattern 27a and the second ball pattern 29a flows into the first electrode 51 of capacitor 50 respectively through the first connecting portion 27b and the second connecting portion 29b and the second electrode 52 and first connects terminal 26 and second and connects and fixed in the way of physics by the capacitor 50 being configured in groove H on terminal 28, additionally, first electrode 51 of the capacitor 50 that electrical connection contacts with each other is connected between terminal 26 with first, and the second electrode 52 of capacitor 50 is connected between terminal 28 with second. at this, the first connecting portion 27b and the second connecting portion 29b plays the effect of the passage that the solder of fusing can be made in reflow process to move. drawing reference numeral 96 represents the conductive component being made up of solder.
Therefore, in the semiconductor package body 100 of embodiment, when not carrying out extra installation procedure, the installation of capacitor 50 can be carried out by the attaching of solder ball and reflow process simultaneously.
Refer again to Fig. 1, described semiconductor chip 60 can possess active face 60a and with described lower surface 60b relative for active face 60a, additionally can include the multiple pads 62 being arranged in active face 60a edge. The lower surface 60b of such semiconductor chip 60, by binding agent 64, is attached on the upper surface of substrate 40 and described first 10a of sandwich layer 10 in the way of relative with first 10a. Semiconductor chip 60 can be dynamic RAM (DRAM) chip or nand flash memory chip. In an embodiment, it is configured with a semiconductor chip 60 at the upper surface of substrate 40 but it also may the multiple semiconductor chip 60 of stacking. In this case, about multiple semiconductor chips 60, both can only stacked memories chip, it is also possible to by memory chip stacking together with logic chip.
Described connection member 70 can include conductor wire, and the weldering being formed as electrically connecting on first 10a of the upper surface being arranged in substrate 40 and sandwich layer 10 refers between 22 and the pad 62 at active face 60a edge being arranged in semiconductor chip 60.
Described seal member 80 can be made up of epoxy molding material (EpoxyMoldingCompound), and on the upper surface 10a of the upper surface and sandwich layer 10 that may be formed at substrate 40 in the way of covering semiconductor chip 60 and connection member 70.
Described solder ball 90 is the external connection terminals for the semiconductor package body 100 in embodiment is connected to external circuit, and namely the lower surface being respectively formed at substrate 40 is located on multiple solder ball pads 24 of second 10b of sandwich layer 10. Solder ball 90 is mounted after solder ball pad 24 applies scaling powder, then can be formed by carrying out Reflow Soldering. As mentioned above, semiconductor package body 100 in embodiment is when the installation of the coating of scaling powder and solder ball, also after namely the lower surface of substrate 54 is located at the first ball pattern 27a and the second ball pattern 29a coating scaling powder of second 10b of sandwich layer 10, virtual solder 95 is installed, and virtual solder 95 is carried out Reflow Soldering and can be formed and be electrically connected the first connection terminal 26 and the second conductive component 96 connecting between terminal 28 and the first electrode 51 and second electrode 52 of capacitor 50.
Although it is not shown, but, in the semiconductor package body 100 of embodiment, it is connected terminal 26 and second respectively with the first of capacitor 50 and connects the first electrode 27c and the second electrode 29c that terminal 28 connects, can be connected with the circuit pattern of the upper surface being formed at substrate 40 and first 10a of sandwich layer 10 or can be connected with the other external device (ED) of the upper surface being formed at substrate 40.
As it has been described above, the semiconductor package body in embodiment possesses structure as follows: be configured with capacitor at the lower surface of substrate and the second face portion of sandwich layer that are not pasted with solder ball with built-in. Therefore, the semiconductor package body in embodiment is when installing capacitor, it is possible to improve the restriction spatially in the upper surface of base plate of the multiple semiconductor chip of stacking.
Additionally, semiconductor package body in embodiment can solve the problem that the problem that the capacitor mounting space of the package interior caused because of the realization of the increase of die size and high stacking (highstack) is not enough, it is therefore not necessary to packaging body is formed as guaranteeing the space of deficiency anomalous structure or without being adjusted the operations unnecessary such as lead-in wire engagement angles.
With reference to Fig. 4, the semiconductor package body 200 in embodiment can include the substrate 40 being formed without groove and the capacitor 50 being arranged on the lower surface of substrate 40.
Specifically, the substrate 40 in embodiment can include sandwich layer 10, multiple weldering refer to 22 and solder ball pad 24, first connect terminal 26 and second and connect terminal the 28, first solder resist 32 and the second solder resist 34. Although it is not shown, substrate 40 may also include that circuit pattern, it is formed on first 10a and second 10b of sandwich layer 10; And path pattern, it is formed in the inside of sandwich layer 10, will be formed in the circuit pattern electrical connection on first 10a and second 10b of described sandwich layer 10.
Sandwich layer 10 can include first 10a and relative with first 10a and lower surface corresponding to substrate 40 second 10b of the upper surface corresponding to substrate 40. Weldering refers to that 22 can be arranged with multiple at the first of sandwich layer 10 10a, and can possess the confined form according to the first solder resist 32. Solder ball pad 24 can be arranged with multiple on the second of sandwich layer 10 10b, and can possess the confined form according to the second solder resist 34.
Although it is not shown, but be arranged in the weldering of first 10a of sandwich layer 10 and refer to that 22 and can be formed at the path pattern of inside of sandwich layer 10 by being respectively formed in the circuit pattern of first 10a and second 10b of sandwich layer 10 and are electrically connected to each other with the solder ball pad 24 of second 10b being arranged in sandwich layer 10.
First connects terminal 26 and second connects terminal 28 and is formed as being separated from each other in sandwich layer 10 and first 10a and second 10b that run through sandwich layer 10. First connects terminal 26 and second connects the extension 27,29 that terminal 28 can include toward each other and extend to second 10b part of sandwich layer 10 respectively and configure. The first ball pattern 27a that first extension 27 can include being connected terminal 26 separate configuration with first and connect terminal 26 and the first ball pattern 27a the first connecting portion 27b being connected by first, the second ball pattern 29a that the second extension 29 can include being connected terminal 28 separate configuration with second and by the second connection terminal 28 and the second ball pattern 29a the second connecting portion 29b being connected. First connects terminal 26 and second connects electrode portion 27c, 29c that terminal 28 may also include toward each other and extends to first 10a part of sandwich layer 10 respectively and configure.
In order to protect the circuit pattern being respectively formed in each face 10a, 10b; first solder resist 32 and the second solder resist 34 are formed on first 10a and second 10b of sandwich layer 10; additionally; first solder resist 32 and the second solder resist 34 are formed as: 22 and solder ball pad the 24, first extension 27 and the second extension 29, first connect terminal 26 and the second connection terminal 28 exposes to make weldering refer to; wherein, the first extension 27 and the second extension 29 include the first ball pattern 27a and the second ball pattern 29a and the first connecting portion 27b and the second connecting portion 29b.
Described capacitor 50 can include the first electrode 51 and the second electrode 52 and the electrolyte 53 between described first electrode 51 and described second electrode 52, and is configured in the first connection terminal 26 and the second connection terminal 28 and the sandwich layer between them 10 part. At this, capacitor 50 can be configured to its first electrode 51 and contacts with the first connection terminal 26, and its second electrode 52 connects terminal 28 with second and contacts. In contrast to this, although not shown, capacitor 50 can also be configured to its first electrode 51 and contact with the second connection terminal 28, and its second electrode 52 connects terminal 56 with first and contacts.
In an embodiment, it is contemplated that be attached to the height of the solder ball 90 of solder ball pad 24 as external connection terminals, capacitor 50 is set.Such as, when the semiconductor package body 200 in embodiment is installed to module substrate or system board via solder ball 90, the height of capacitor 50 is below the height of solder ball.
By the conductive component 96 that solder is constituted can by electrically connect first connection terminal 26 and the first electrode 51 of capacitor 50 between and second be connected between terminal 28 and the second electrode 52 of capacitor 50 in the way of form second 10b at sandwich layer 10. Specifically, conductive component 96 may be formed at the first ball pattern 27a exposed of second 10b from sandwich layer 10 and the second ball pattern 29a, the first connecting portion 27b and the second connecting portion 29b, the first connection terminal 26 and the second connection terminal 28 and on the side of the first electrode 51 and the second electrode 52. According to such conductive component 96, can by capacitor 50 on the lower surface being fixed on the substrate 40 of second 10b corresponding to sandwich layer 10 in the way of physics.
The substrate of above-mentioned various embodiments is applicable to the semiconductor device of various kind and possesses the package body module of semiconductor device.
With reference to Fig. 6, have employed the electronic system 1000 of the substrate in various embodiment and comprise the steps that controller 1100, input/output unit 1200 and storage device 1300. Controller 1100, input/output unit 1200 and storage device 1300 can be combined by bus 1500, and this bus 1500 provides the path moved for data.
Such as, controller 1100 can include at least one microprocessor, digital signal processor, microcontroller and perform the logical device of similar function at least one. Controller 1100 and storage device 1300 can include the semiconductor device in various embodiment. Input/output unit 1200 can include from keypad (keypad), keyboard (keyboard) and display device etc. select at least one.
Storage device 1300 can store data and/or the instruction etc. performed by controller 1100. Storage device 1300 can include the such volatile memory elements of DRAM and/or the such non-volatile memory device of flash memory. Such as, in mobile equipment or the such information processing system of desktop computer, flash memory can be installed. Such flash memory is made up of semiconductor disk device SSD. In this case, jumbo data stabilization can be stored in flash memory system by electronic system 1000.
Such electronic system 1000 may also include for transmitting data to communication network or receiving the interface 1400 of data from communication network. Interface 1400 can be wire/wireless form. Such as, interface 1400 can include antenna or wire/wireless transceiver etc.
It addition, although it is not shown, electronic system 1000 may also include application chip group (ApplicationChipset) and camera image processor etc.
Electronic system 1000 can be mobile system, PC, industrial computer or the logical system etc. performing various function. Such as, mobile system can be portable personal information terminal (PDA; PersonalDigitalAssistant), any one in laptop computer, web tablet (webtablet), mobile phone (mobilephone), smart mobile phone (smartphone), radio telephone (wirelessphone), (laptop) on knee computer, storage card, digital music system (digitalmusicsystem) and information transmission/reception system.
When electronic system 1000 is the device that can carry out radio communication, electronic system 1000 can be used in CDMA (CodeDivisionMultipleAccess: CDMA), GSM (GlobalSystemforMobilecommunication: global system for mobile communications), NADC (NorthAmericanDigitalCellular: north American digital cellular), E-TDMA (Enhanced-TimeDivisionMultipleAccess: enhancement mode time division multiple acess), WCDMA (WidebandCodeDivisionMultipleAccess: WCDMA), CDMA2000, LTE (LongTermEvolution: Long Term Evolution), in the communication system of Wibro (WirelessBroadbandInternet: wireless broadband network) etc.
With reference to Fig. 7, storage card 2000 can include the substrate in various embodiment, and storage card 2000 can include memorizer 2100 and storage control 2200. Such as, although do not limited, but memorizer 2100 and storage control 2200 can include non-volatile memory device. Memorizer 2100 and storage control 2200 can store data maybe can read the data of storage.
Memorizer 2100 can include have employed at least one in the non-volatile memory device of the semiconductor package body in the above embodiments. Storage control 2200 can respond the read/write requests of main frame 2300, controls memorizer 2100 and reads stored data or storage data.
Above, illustrate according to specific embodiment at this and describe this utility model, but this utility model is not limited to this, those skilled in the art are it should be readily apparent that this utility model can be transformed and deform in the limit without departing from spirit of the present utility model and field by claims below in every way.
The application advocates the priority of the Korean Patent Application No. 10-2015-0077784 submitted on June 2nd, 2015 to Korean Intellectual Property Office, and this by referring to and introduce its full content.
Claims (14)
1. a semiconductor package body, it is characterised in that this semiconductor package body includes:
Substrate, it includes sandwich layer, the first connection terminal and second connects terminal, described sandwich layer possess first that is arranged with that multiple weldering refers to and with described first relative and be arranged with second of multiple solder ball pad, described first connects terminal and described second connects terminal and is formed as being separated from each other and run through described first and described second in described sandwich layer;
Capacitor, it is configured at the inside of sandwich layer of described substrate, and possesses electrode, and described electrode is configured to be connected terminal and described second respectively with described first and connects termination contact; And
Conductive component, it is formed as that described first connection terminal and described second are connected terminal and is connected to the electrode of described capacitor.
2. semiconductor package body according to claim 1, it is characterised in that
Described substrate also includes:
First solder resist, it is formed on first of described sandwich layer in the way of making described weldering refer to expose; And
Second solder resist, it is formed on second of described sandwich layer in the way of making described solder ball pad, described first connection terminal, described second connection terminal and described capacitor expose.
3. semiconductor package body according to claim 1, it is characterised in that
Described sandwich layer includes from second of the described sandwich layer groove formed, and is configured with described first and connects terminal, described second connection terminal and described capacitor in described groove.
4. semiconductor package body according to claim 3, it is characterised in that
Described first connection terminal and described second connects terminal and is arranged in the relative sidewall in described groove and on another sidewall,
Described capacitor is with built-in described first connection terminal and described second bottom surface being connected between terminal being arranged in described groove.
5. semiconductor package body according to claim 1, it is characterised in that
Described first connection terminal and described second link attached bag are drawn together the first extension and the second extension, described first extension and described second extension and toward each other and are extended to the second face portion of described sandwich layer respectively and configure.
6. semiconductor package body according to claim 5, it is characterised in that
Described first extension includes:
First ball pattern, it is connected terminal separate configuration with described first;And
At least more than one the first connecting portion, they connect described first ball pattern and are connected between terminal with described first,
Described second extension includes:
Second ball pattern, it is connected terminal separate configuration with described second; And
At least more than one the second connecting portion, they connect described second ball pattern and are connected between terminal with described second.
7. semiconductor package body according to claim 5, it is characterised in that
Described first connection terminal and described second link attached bag are drawn together the first electrode portion and the second electrode portion, described first electrode portion and described second electrode portion and are divided extension to configure toward each other and respectively to the first facial of described sandwich layer.
8. semiconductor package body according to claim 1, it is characterised in that
Described capacitor includes:
First electrode, it is configured to be connected termination contact with described first;
Second electrode, it is configured to be connected termination contact with described second; And
Electrolyte, it is between described first electrode and described second electrode.
9. semiconductor package body according to claim 1, it is characterised in that
In the edge of second of described sandwich layer, be not configured with the part of described solder ball pad, configure at least more than one described capacitor.
10. semiconductor package body according to claim 1, it is characterised in that
Described conductive component includes solder.
11. semiconductor package body according to claim 1, it is characterised in that
Described semiconductor package body also includes:
Semiconductor chip, it possesses the active face being arranged with multiple pad at edge and the lower surface relative with described active face, and makes described lower surface relative with the upper surface of the described substrate corresponding to first of described sandwich layer;
Connection member, the weldering of described substrate is referred to electrically connect with the pad of described semiconductor chip by it;
Seal member, it is to be formed on the upper surface of described substrate in the way of covering described semiconductor chip and connection member; And
Solder ball, it is formed on the solder ball pad of described substrate.
12. semiconductor package body according to claim 11, it is characterised in that
Described connection member includes sealing wire.
13. semiconductor package body according to claim 11, it is characterised in that
Described semiconductor chip tegillum is laminated with at least more than one.
14. semiconductor package body according to claim 13, it is characterised in that
Described semiconductor chip includes the stacking of memory chip or the stacking of memory chip and logic chip.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2015-0077784 | 2015-06-02 | ||
| KR1020150077784A KR20160142012A (en) | 2015-06-02 | 2015-06-02 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205319148U true CN205319148U (en) | 2016-06-15 |
Family
ID=56186364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521055419.3U Active CN205319148U (en) | 2015-06-02 | 2015-12-17 | Semiconductor package |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20160142012A (en) |
| CN (1) | CN205319148U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115668483A (en) * | 2020-05-21 | 2023-01-31 | 三菱电机株式会社 | Semiconductor device, power conversion device, mobile object, and method for manufacturing semiconductor device |
-
2015
- 2015-06-02 KR KR1020150077784A patent/KR20160142012A/en unknown
- 2015-12-17 CN CN201521055419.3U patent/CN205319148U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115668483A (en) * | 2020-05-21 | 2023-01-31 | 三菱电机株式会社 | Semiconductor device, power conversion device, mobile object, and method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20160142012A (en) | 2016-12-12 |
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