CN202796920U - Multi-chip quad flat no-lead (QFN) packaging structure - Google Patents
Multi-chip quad flat no-lead (QFN) packaging structure Download PDFInfo
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- CN202796920U CN202796920U CN 201220442150 CN201220442150U CN202796920U CN 202796920 U CN202796920 U CN 202796920U CN 201220442150 CN201220442150 CN 201220442150 CN 201220442150 U CN201220442150 U CN 201220442150U CN 202796920 U CN202796920 U CN 202796920U
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- qfn
- circuit function
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Abstract
The utility model discloses a multi-chip quad flat no-lead (QFN) packaging structure which comprises at least one chip with a logic circuit function, an electric connecting chip and a QFN packaging tube casing. The electric connecting chip is connected with at least one chip with the logic circuit function and/or the QFN packing tube casing. By adding the electric connecting chip, feasibility for packing one or a plurality of chips in one QFN is provided, packaging cost is reduced, and integration degree and reliability of a device are improved.
Description
Technical field
The utility model relates to the encapsulation technology field of semiconductor device, relates in particular to a kind of multi-chip QFN encapsulating structure.
Background technology
In semiconductor packaging process, quad flat non-pin (Quad Flat No-lead Package, QFN) is packaged with lot of advantages, cost such as encapsulation is low, the electrical property of brilliance etc. can be provided, but some defectives are also arranged, fewer such as available electrode contacts quantity.Present QFN encapsulating structure is that single chips (Die) is packaged into a QFN encapsulation mostly, also has producer that two chips are packaged into a QFN encapsulation.But owing to be subject to QFN package design rule limits, as require to encapsulate inner short leg and lead-in wire and can not intersect etc., the chip that has therefore limited a lot of more complicated can't adopt the QFN encapsulation when needs carry out multi-chip package (MCP).
The utility model content
The purpose of this utility model is for the above-mentioned problems in the prior art, and a kind of encapsulating structure is provided, and adopts a QFN encapsulation in order to the chip (Die) of realizing at least one more complicated.
The utility model provides a kind of multi-chip QFN encapsulating structure, comprising:
At least one the chip with the logical circuit function; Be electrically connected chip; The QFN encapsulating package;
Described electrical connection chip is connected with the chip of logical circuit function and/or with described QFN encapsulating package with described at least one.
Preferably, comprise at least two bond pad on the described electrical connection chip, the Metal Phase by conductive layer between two or more bond pad connects.
Preferably, the bond pad of described chip with the logical circuit function is connected by the bond pad of metal connecting line with described electrical connection chip, and the bond pad by the described chip with the logical circuit function of metal connecting line and another is connected again.
Preferably, the bond pad of described chip with the logical circuit function is connected by the bond pad of metal connecting line with described electrical connection chip, is connected by the electrode contacts of metal connecting line with described QFN encapsulating package again.
Preferably, the bond pad of described chip with the logical circuit function is connected by the bond pad of metal connecting line with described electrical connection chip, bond pad by the described chip with the logical circuit function of metal connecting line and another is connected again, and another bond pad of described chip with the logical circuit function is connected with another bond pad of described electrical connection chip by the metal connecting line, is connected by the electrode contacts of metal connecting line with the QFN encapsulating package again.
Preferably, described chip with the logical circuit function is no more than the quantity of the electrode contacts of QFN encapsulating package to the bond pad quantity of outer lead with described after being electrically connected chip and being electrically connected.
Preferably, described multi-chip QFN encapsulating structure also comprises immobilization material; Described at least one the chip with the logical circuit function is the lamination placement with the described chip that is electrically connected in described QFN encapsulating package, fix by immobilization material between each layer chip, the orlop chip that lamination is placed is fixed on the QFN encapsulating package by immobilization material.
The utility model is electrically connected chip by increase by one in the QFN encapsulating structure, realized with one or many with the chip package of logic function in the QFN shell, thereby solved owing to be subject to the restriction of QFN package design rule, as encapsulated inner short leg, lead-in wire and can not intersect etc. and cause a lot of complex chip when needs carry out multi-chip package, can't adopt the problem of QFN encapsulation.
Description of drawings
The schematic top plan view of the QFN apparatus structure that Fig. 1 provides for the utility model embodiment one;
The QFN shell schematic diagram that Fig. 2 provides for the utility model embodiment;
The Die10 schematic diagram that Fig. 3 provides for the utility model embodiment;
The Die20 schematic diagram that Fig. 4 provides for the utility model embodiment;
The Die30 schematic diagram that Fig. 5 provides for the utility model embodiment;
The generalized section of the QFN encapsulating structure that Fig. 6 provides for the utility model embodiment one;
The schematic top plan view of the QFN apparatus structure that Fig. 7 provides for the utility model embodiment two;
The schematic top plan view of the QFN apparatus structure that Fig. 8 provides for the utility model embodiment three;
The Die20 schematic diagram that Fig. 9 provides for the utility model embodiment three;
The Die40 schematic diagram that Figure 10 provides for the utility model embodiment three.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing the utility model specific embodiment is described in further detail.
What following embodiment described is a kind of multi-chip QFN encapsulating structure.
Fig. 1 is the schematic top plan view of QFN encapsulating structure among the utility model embodiment one; Fig. 2 is QFN shell schematic diagram; Fig. 3 is the Die10 schematic diagram; Fig. 4 is the Die20 schematic diagram, and Fig. 5 is the Die30 schematic diagram.
As shown in Figure 1, the QFN encapsulating structure specifically comprises Die10, Die20, and Die30, QFN shell 40, and between the bond pad of each chip (Die) and the connecting line 50 between the electrode contacts of QFN shell 60 and each chip (Die) bond pad.
Die20 comprises a conducting medium 23 that is used for connecting two bond pad 21 and 22 for being electrically connected chip.
Die10 and Die30 be two with the chip of logical circuit function, Die10 can realize a circuit function with Die30 by being electrically connected.
For realizing that this circuit function need to link to each other the bond pad 31 of Die30 with the bond pad 11 of Die10, the bond pad 32 of Die30 is linked to each other with the bond pad 12 of Die10, the bond pad 13 of Die10 need to be connected with the electrode contacts 61 of QFN shell 60 simultaneously, and the I/O of encapsulated device (I/O) port is the electrode contacts 61 on the QFN shell 60.
As shown in Figure 1, the bond pad 32 of Die30 and the bond pad 12 of Die10 are directly carried out Bonding (Wire Bonding), the bond pad 13 of Die10 and the electrode contacts 61 of QFN shell 60 are directly carried out Bonding.
In the prior art, because be subject to the design rule (Design Rule) of QFN packaging technology, the length of metal connecting line (Wire) can not surpass certain value, if thereby 12 of the bond pad of the bond pad 32 of Die30 and Die10 have carried out Bonding (Wire Bonding), then just can't carry out Bonding between the bond pad 11 of the bond pad 31 of Die30 and Die10.If want the circuit function that realizes that Die10 and Die30 couple together, must by this two chips be encapsulated separately, carry out again the outside and be electrically connected and to realize.
In the present embodiment, being electrically connected by following manner between the bond pad 11 of the bond pad 31 of Die30 and Die10 realized:
The bond pad 31 of Die30 is carried out Bonding with the bond pad 22 of Die20, the bond pad 21 of Die20 is carried out Bonding with the bond pad 11 of Die10, the bond pad 21 of Die22 and 22 is electrically connected direct-connected by conducting medium 23 at Die20, realized being electrically connected by Die20 between the bond pad 11 of the bond pad 31 of Die30 and Die10 thus.
The generalized section of the QFN encapsulating structure that Fig. 6 provides for the utility model embodiment one, as shown in the figure, Die30, Die20, Die10, QFN shell 60 successively lamination place, and 60 of each chip and QFN shells carry out Bonding by metal connecting line 50, Die30, Die20, Die10 chip and chip chamber, 60 of chip Die10 and QFN shells are fixed together successively by immobilization material.Typical immobilization material can comprise viscose glue, such as epoxy resin silver slurry; Perhaps be with sticking film, such as epoxy resin thin film.
The disclosed multi-chip QFN encapsulating structure of the utility model embodiment, realized being electrically connected between Die10 and the Die30 by adding Die20 with electrical connection, a so that QFN encapsulation complete circuit function after having realized Die10 and Die30 being connected, reduce packaging cost, improved the integrated level of device.
What following embodiment described is another kind of multi-chip QFN encapsulating structure.
Fig. 7 is the schematic top plan view of QFN encapsulating structure among the utility model embodiment two, the utility model embodiment two specifically comprises, Die20, Die30 is between the bond pad of QFN shell 60 and each chip (Die) and the connecting line 50 between the electrode contacts of QFN shell 60 and each chip (Die) bond pad.
Die20 comprises a conducting medium 23 that is used for connecting two bond pad 21 and 22 for being electrically connected chip.
Die30 is the chip with the logical circuit function.
In an application, need to be with 31, the 32 homonymy realization I/O in encapsulation of Die30, the bond pad 31 of Die30 need to be connected with the electrode contacts 61 of QFN shell 60, and the bond pad 32 of Die30 is connected with the electrode contacts 62 of QFN shell 60.The I/O of encapsulated device (I/O) port is the electrode contacts 61,62 on the QFN shell 60.
In the prior art, because be subject to the design rule (Design Rule) of QFN packaging technology, the length of metal connecting line (Wire) can not surpass certain value, if thereby carried out Bonding (Wire Bonding) between the electrode contacts 62 of the bond pad 32 of Die30 and QFN shell 60, then just can't carry out Bonding between the electrode contacts 61 of the bond pad 31 of Die30 and QFN shell 60.If want to use the QFN encapsulation to realize that 31,32 of Die30 realizes I/O at homonymy, must go between to realize by package outside, greatly reduce reliability.
In embodiment of the present utility model, as shown in Figure 7, the bond pad 32 of Die30 and the electrode contacts 62 of QFN shell 60 are directly carried out Bonding (Wire Bonding), and being electrically connected by following manner between the electrode contacts 61 of the bond pad 31 of Die30 and QFN shell 60 realizes:
The bond pad 31 of Die30 is carried out Bonding with the bond pad 22 of Die20, the bond pad 21 of Die20 is carried out Bonding with the electrode contacts 61 of QFN shell 60, the bond pad 21 of Die20 and 22 is electrically connected direct-connected by conducting medium 23 at Die20, realized being electrically connected by Die20 between the electrode contacts 61 of the bond pad 31 of Die30 and QFN shell 60 thus.The disclosed multi-chip QFN encapsulating structure of the utility model embodiment, realized being electrically connected between the electrode contacts of Die30 and QFN shell 60 by adding Die20 with electrical connection, so that QFN encapsulation realized Die30 to the homonymy I/O of side ports in the QFN encapsulation, improved device reliability.
What following embodiment described is another multi-chip QFN encapsulating structure.
Fig. 8 is the schematic top plan view of QFN encapsulating structure among the utility model embodiment three; Fig. 9 is the Die20 schematic diagram; Figure 10 is the Die40 schematic diagram.
As shown in Figure 8, the QFN encapsulating structure comprises, Die10, Die20, Die30, Die40, QFN shell 60, and the connecting line 50 between the bond pad of each chip (Die), between QFN shell electrode contacts and each chip (Die) bond pad.
Die20 is electrically connected chip, comprises a conducting medium 23 that is used for connecting two bond pad 21 and 22, with the conducting medium 26 of being connected for two bond pad 24 of connection and 25.
Die10, Die30, Die40 be three with the chip of logical circuit function.Die10, Die30, Die40 can realize a circuit function by being electrically connected.
For realizing this circuit function, the bond pad 41 of Die40 need to be linked to each other with the bond pad 33 of Die30, the bond pad 43 of Die40 links to each other with the bond pad 12 of Die10, the bond pad 42 of Die40 need to be connected with the electrode contacts 62 of QFN shell 60 simultaneously, and the bond pad 11 of Die10 need to be connected with the electrode contacts 61 of QFN shell 60.The I/O of encapsulated device (I/O) port is the electrode contacts 61,62 on the QFN shell.
As shown in Figure 8, bond pad 41 and the bond pad 33 of Die30 of Die40 are directly carried out Bonding (Wire Bonding), the bond pad 11 of Die10 and the electrode contacts 61 of QFN shell 60 are directly carried out Bonding.And being electrically connected between the electrode contacts 62 of the bond pad 42 of Die40 and QFN shell 60, and the electrical connection between the bond pad 12 of the bond pad 43 of Die40 and Die10 realizes by following manner respectively:
The bond pad 42 of Die40 is carried out Bonding with the bond pad 22 of Die20, the bond pad 21 of Die20 is carried out Bonding with the electrode contacts 61 of QFN shell 60, the bond pad 21 of Die2 20 and 22 is electrically connected direct-connected by conducting medium 23 at Die2 20, realized being electrically connected by Die20 between the electrode contacts 62 of the bond pad 42 of Die40 and QFN shell 60 thus.
The bond pad 43 of Die40 is carried out Bonding with the bond pad 24 of Die20, the bond pad 25 of Die20 is carried out Bonding with the bond pad 12 of Die10, the bond pad 24 of Die2 and 25 is electrically connected direct-connected by conducting medium 26 at Die20, realized being electrically connected by Die20 between the bond pad 12 of the bond pad 43 of Die40 and Die10 thus.
The disclosed multi-chip QFN encapsulating structure of the utility model embodiment, by being electrically connected between Die3 30 and the Die4 40, being electrically connected between Die1 10 and QFN shell 60 electrode contacts, and by add Die2 20 with electrical connection realized between Die10 and the Die40 be electrically connected and Die40 and QFN shell 60 electrode contacts between be electrically connected, a so that QFN encapsulation complete circuit function after having realized Die1 10, Die3 30 and Die4 40 being connected, reduce packaging cost, improved integrated level and the reliability of device.
Need to prove that among above-mentioned several embodiment, the electrical connection between each bond pad of Die20 is that the position with the bond pad on the chip of logic function that is attached thereto is as required determined.In actual applications, be electrically connected chip and be not limited to these two kinds of forms that Die20 provides in the present embodiment, can set as required the position of bond pad, and can be connected by conducting medium between any two bond pad, also can be designed to as required between a plurality of bond pad by conducting medium to connection.
Application Example of the present utility model is not limited to and comprises one, two or three and use at the multi-chip package (MCP) based on the QFN encapsulating structure with the chips of logical circuit, and it is equally applicable to many with the chip of logical circuit.
In sum, the utility model embodiment discloses a kind of QFN encapsulating structure with being electrically connected chip, has realized at least one the chip package with logic function in a QFN shell.This encapsulating structure has solved owing to be subject to the requirement of QFN package design rule, as encapsulate that inner short leg, lead-in wire such as can not intersect at the restriction and the problem that causes a lot of complex chip when needs carry out multi-chip package, can't adopt QFN to encapsulate, reduce simultaneously packaging cost, improved integrated level and the reliability of device.
Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the above only is embodiment of the present utility model; and be not used in and limit protection range of the present utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (7)
1. a multi-chip QFN encapsulating structure is characterized in that comprising,
At least one the chip with the logical circuit function; Be electrically connected chip; The QFN encapsulating package;
Described electrical connection chip is connected with the chip of logical circuit function and/or with described QFN encapsulating package with described at least one.
2. multi-chip QFN encapsulating structure as claimed in claim 1 is characterized in that, comprises at least two bond pad on the described electrical connection chip, and the Metal Phase by conductive layer between two or more bond pad connects.
3. multi-chip QFN encapsulating structure as claimed in claim 1, it is characterized in that, the bond pad of described chip with the logical circuit function is connected by the bond pad of metal connecting line with described electrical connection chip, and the bond pad by the described chip with the logical circuit function of metal connecting line and another is connected again.
4. multi-chip QFN encapsulating structure as claimed in claim 1, it is characterized in that, the bond pad of described chip with the logical circuit function is connected by the bond pad of metal connecting line with described electrical connection chip, is connected by the electrode contacts of metal connecting line with described QFN encapsulating package again.
5. multi-chip QFN encapsulating structure as claimed in claim 1, it is characterized in that, the bond pad of described chip with the logical circuit function is connected by the bond pad of metal connecting line with described electrical connection chip, bond pad by the described chip with the logical circuit function of metal connecting line and another is connected again, and another bond pad of described chip with the logical circuit function is connected with another bond pad of described electrical connection chip by the metal connecting line, is connected by the electrode contacts of metal connecting line with the QFN encapsulating package again.
6. multi-chip QFN encapsulating structure as claimed in claim 1 is characterized in that, described chip with the logical circuit function is no more than the quantity of the electrode contacts of QFN encapsulating package to the bond pad quantity of outer lead with described after being electrically connected chip and being electrically connected.
7. multi-chip QFN encapsulating structure as claimed in claim 1 is characterized in that, described multi-chip QFN encapsulating structure also comprises immobilization material; Described at least one the chip with the logical circuit function is the lamination placement with the described chip that is electrically connected in described QFN encapsulating package, fix by immobilization material between each layer chip, the orlop chip that lamination is placed is fixed on the QFN encapsulating package by immobilization material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220442150 CN202796920U (en) | 2012-08-31 | 2012-08-31 | Multi-chip quad flat no-lead (QFN) packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220442150 CN202796920U (en) | 2012-08-31 | 2012-08-31 | Multi-chip quad flat no-lead (QFN) packaging structure |
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| CN202796920U true CN202796920U (en) | 2013-03-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220442150 Expired - Fee Related CN202796920U (en) | 2012-08-31 | 2012-08-31 | Multi-chip quad flat no-lead (QFN) packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681551A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | QFN (Quad Flat No Lead) package design suitable for high-speed chip application |
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2012
- 2012-08-31 CN CN 201220442150 patent/CN202796920U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681551A (en) * | 2013-12-03 | 2015-06-03 | 上海北京大学微电子研究院 | QFN (Quad Flat No Lead) package design suitable for high-speed chip application |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130313 Termination date: 20200831 |
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| CF01 | Termination of patent right due to non-payment of annual fee |