CN203085511U - Re-wiring multi-chip AAQFN packaging device - Google Patents

Re-wiring multi-chip AAQFN packaging device Download PDF

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Publication number
CN203085511U
CN203085511U CN2012206990105U CN201220699010U CN203085511U CN 203085511 U CN203085511 U CN 203085511U CN 2012206990105 U CN2012206990105 U CN 2012206990105U CN 201220699010 U CN201220699010 U CN 201220699010U CN 203085511 U CN203085511 U CN 203085511U
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China
Prior art keywords
chip
pin
metal material
packaging
material layer
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Expired - Fee Related
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CN2012206990105U
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Chinese (zh)
Inventor
秦飞
夏国峰
安彤
刘程艳
武伟
朱文辉
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Beijing University of Technology
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Beijing University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

The utility model discloses a re-wiring multi-chip AAQFN packaging device. The prepared re-wiring multi-chip AAQFN packaging device has multiple stacked IC chips, wherein a mother IC chip is configured at a central position of the packaging device through pasting material, a sub IC chip can be configured above the mother IC chip through the pasting material, partition material or welding material, insulation filling material is configured among pins, the mother IC chip is connected with a first metal material layer through metal lead, the pins are connected with the first metal material layer through a re-wiring layer, a second metal material layer is configured at a lower surface of the pins, and the pins are in array arrangement in the packaging device and are packed by utilizing plastic packaging material. The re-wiring multi-chip AAQFN packaging device solves problems of low I/O quantity, high packaging cost existing in tradition GFN packaging and improves reliability of a packaging body.

Description

A kind of multicore sheet AAQFN packaging that connects up again
Technical field
The utility model relates to QFN packaging manufacturing technology field, refers more particularly to the QFN packaging with high I/O density, multicore sheet.
Background technology
Along with electronic product such as mobile phone, notebook computer etc. towards miniaturization, portable, ultra-thinization, multimedization and satisfy popular needed low-cost direction and develop, high density, high-performance, high reliability and packing forms and packaging technology thereof have obtained development fast cheaply.Compare with packing forms such as expensive BGA, Kuai Sufazhan novel encapsulated technology in recent years, i.e. four limit flat non-pin QFN(Quad Flat Non-lead Package) encapsulation, because have good hot property and electrical property, size is little, cost is low and numerous advantages such as high production rate, has caused a new revolution in microelectronic packaging technology field.
Because the raising of IC integrated level and the continuous enhancing of function, the I/O number of IC increases thereupon, the also corresponding increase of I/O number of pins of corresponding packaging, but the pin of traditional QFN packaging part device is individual pen around the chip carrier periphery to be arranged, limited the raising of I/O quantity, do not satisfy high density, have the needs of the IC of more I/O numbers, therefore the QFN packaging of multi-turn pin arrangements has appearred being, wherein pin is the multi-turn arrangement around chip carrier, has significantly improved the I/O number of pins of packaging.
Figure 1A and Figure 1B are respectively the schematic rear view of the QFN packaging with multi-turn pin arrangements and along the generalized section of I-í section.The QFN encapsulating structure of this multi-turn pin arrangements comprises chip carrier 11, is the pin 12 that three circles are arranged, capsulation material 13, adhesive material 14, IC chip 15, plain conductor 16 around chip carrier 11.IC chip 15 is fixed on the chip carrier 12 by adhesive material 14; IC chip 15 is realized being electrically connected by plain conductor 16 with the pin of arranging all around 12; 13 pairs of IC chips 15 of capsulation material, plain conductor 16, chip carrier 11 and pin 12 are sealed the effect to reach protection and to support; pin 12 exposes in the bottom surface of capsulation material 13, is welded on by scolder on the circuit board such as PCB to realize and extraneous being electrically connected.The exposed chip carrier in bottom surface 11 is welded on by scolder on the circuit board such as PCB, has direct heat dissipation channel, can effectively discharge the heat that IC chip 15 produces.
Compare with the QFN packaging of traditional individual pen pin arrangements, the QFN packaging of multi-turn pin arrangements has higher pin number, has satisfied the more and more higher requirement of IC integrated level.Yet, in order to improve the I/O quantity of QFN packaging, need more zone to place a plurality of pins, therefore need to increase the size of QFN packaging, the requirement of this and packaging miniaturization is runed counter to, and along with package dimension increases, distance between chip and the pin can increase, cause plain conductor, use amount as gold (Au) line increases, increased manufacturing cost, long plain conductor very easily causes problems such as subsiding, breasting the tape of plain conductor and intersection in the Shooting Technique process, influenced the yield of packaging and the lifting of reliability.Therefore, for oversize bottleneck, the above-mentioned yield of solution and integrity problem and the reduction manufacturing cost that breaks through existing multi-turn pin arrangements QFN packaging, be badly in need of the QFN packaging and the manufacture method thereof of a kind of small size of research and development, high reliability, low cost, high I/O density.
The utility model content
The utility model provides a kind of multicore of wiring again AAQFN(Area Array Quad Flat Non-lead Package that unilateral battle array is arranged) packaging, with bottleneck that reaches the low I/O quantity that breaks through traditional Q FN encapsulation, high packaging cost and the purpose that improves the reliability of packaging body.
To achieve these goals, the utility model adopts following technical proposals:
The utility model proposes a kind of multicore sheet AAQFN packaging that connects up again, comprise one of following three kinds of schemes:
Scheme one:
Pin is the face battle array and arranges in packaging, insulation filling material is disposed between pin and the pin, female IC chip is disposed at the center of packaging by adhesive material, sub-IC chip is disposed at the top of female IC chip by adhesive material, first metal material layer is around female IC arrangements of chips, pin is realized and being connected of first metal material layer by wiring layer again, second metal material layer is disposed at the lower surface of pin, female IC chip is connected to first metal material layer by plain conductor, sub-IC chip is connected to first metal material layer by plain conductor, capsulation material coats the above-mentioned female IC chip of sealing, sub-IC chip, adhesive material, plain conductor, first metal material layer and wiring layer more only expose second metal material layer that is disposed at the pin lower surface.
Scheme two:
Pin is the face battle array and arranges in packaging, insulation filling material is disposed between pin and the pin, female IC chip is disposed at the center of packaging by adhesive material, separator material is disposed at the top of female IC chip, sub-IC chip configuration is in the top of separator material, first metal material layer is around female IC arrangements of chips, pin is realized and being connected of first metal material layer by wiring layer again, second metal material layer is disposed at the lower surface of pin, female IC chip is connected to first metal material layer by plain conductor, sub-IC chip is connected to first metal material layer by plain conductor, capsulation material coats the above-mentioned female IC chip of sealing, sub-IC chip, separator material, adhesive material, plain conductor, first metal material layer and wiring layer more only expose second metal material layer that is disposed at the pin lower surface.
Scheme three:
Pin is the face battle array and arranges in packaging, insulation filling material is disposed between pin and the pin, female IC chip is disposed at the center of packaging by adhesive material, sub-IC chip passes through the welding material flip-chip configuration in the top of female IC chip, first metal material layer is around female IC arrangements of chips, pin is realized and being connected of first metal material layer by wiring layer again, second metal material layer is disposed at the lower surface of pin, female IC chip is connected to first metal material layer by plain conductor, capsulation material coats the above-mentioned female IC chip of sealing, sub-IC chip, welding material, adhesive material, plain conductor, first metal material layer and wiring layer more only expose second metal material layer that is disposed at the pin lower surface.
Of particular note: the arrangement mode that is the pin of face battle array arrangement can be and is arranged in parallel, also can be for being staggered the rounded or rectangle of the shape of cross section of pin.
According to embodiments of the invention, the pin that the face battle array is arranged is and is arranged in parallel.
According to embodiments of the invention, the shape of cross section rectangular shaped of pin.
According to embodiments of the invention, to make a plurality of pins that form and pass through again the bonding position that wiring layer changes plain conductor, realization is interconnected with the IC chip.
According to embodiments of the invention, first and second metal material layer comprises nickel (Ni), palladium (Pd), gold (Au), silver (Ag) metal material.
According to embodiments of the invention, adopt insulation filling material and capsulation material to carry out secondary and coat sealing formation packaging.
According to embodiments of the invention, insulation filling material is disposed between the pin.
According to embodiments of the invention, the insulation filling material kind is the thermosetting capsulation material, perhaps materials such as plug socket resin, printing ink and welding resistance green oil.
According to embodiment of the present utility model, separator material is an insulating material, can be and IC chip identical materials.
According to embodiment of the present utility model, welding material can be lead-free solder or metal salient point.
Based on above-mentioned, the wiring layer again that the utility model adopts can make the size of packaging significantly reduce, shortened the distance between IC chip and the pin, can realize and being connected of the pin of IC chip below, reduce plain conductor, as the use amount of gold (Au) line, reduced manufacturing cost, solved subsiding, breast the tape and problem such as intersection of plain conductor in the Shooting Technique process, promoted the yield and the reliability of packaging, and significantly promoted the I/O density of packaging.The utility model carries out stacked package with a plurality of IC chips, has reduced the size of encapsulation greatly.The utility model adopts insulation filling material and capsulation material to carry out secondary and coats sealing, wherein insulation filling material is disposed under the wiring layer again, the above zone of wiring layer adopts capsulation material to coat sealing again, this filling, clad structure feature can realize that the no cavity that encapsulates seals, and eliminate because of defectives such as the bubble of sealing incomplete generation, cavities.The generation of bridging phenomenon when the pin of the small size size that the utility model manufacturing forms can effectively prevent surface mount, the lower surface of pin and the metal material layer that disposes on the wiring layer again can effectively improve metal lead wire bonding quality and surface mount quality respectively.
Embodiment cited below particularly, and conjunction with figs. elaborates to above-mentioned feature and advantage of the present utility model.
Description of drawings
Figure 1A is the schematic rear view of the QFN packaging of multi-turn pin arrangements;
Figure 1B is the generalized section along the I-í section among Figure 1A;
Fig. 2 A is the schematic rear view of the multicore sheet AAQFN packaging that connects up again of the present utility model;
Fig. 2 B is the front schematic view of the multicore sheet AAQFN packaging that connects up again of the present utility model;
Fig. 3 is along the I-among Fig. 2 B IFirst embodiment of profile drawing;
Fig. 4 is along the I-among Fig. 2 B ISecond embodiment of profile drawing;
Fig. 5 is along the I-among Fig. 2 B IThe 3rd embodiment of profile drawing;
Number in the figure: the QFN packaging of 100. multi-turn pin arrangements, 11. chip carriers, 12. pins, 13. capsulation materials, 14. adhesive material, 15.IC chip, 16. plain conductors, the 200. multicore sheet AAQFN packagings that connect up again, 21. pin, 22. insulation filling materials, 23. first metal material layers, 24. second metal material layer, 25. wiring layers again, 26. capsulation materials, 27. female IC chip, 28. adhesive materials, 29. plain conductors, 30. sub-IC chip, 31. separator materials, 32. welding materials.
Embodiment
Below in conjunction with accompanying drawing the utility model is elaborated:
Fig. 2 A is the multicore sheet AAQFN packaging schematic rear view that connects up again of the present utility model, second metal material layer 24 is disposed at and is pin 21 surfaces that the face battle array is arranged in the multicore sheet AAQFN packaging 200 that connects up again, the arrangement mode of pin 21 is for being arranged in parallel, the cross section of pin 21 is a rectangle, disposes insulation filling material 22 in the multicore sheet AAQFN packaging 200 that connects up again.The arrangement mode of pin 21 is not defined as and is arranged in parallel, and can be other arrangement modes, and the shape of cross section of pin 21 is not defined as rectangle, can be circle.
Fig. 2 B is the front schematic view according to the multicore sheet AAQFN packaging that connects up again of the present utility model, in order clearly to show the internal structure of the multicore sheet AAQFN packaging 200 that connects up again, only show insulation filling material 22, the wiring layer 25 and first metal material layer 23 again.Can see that insulation filling material 22 is disposed between pin 21 and the pin 21, and be disposed at the below of wiring layer 25 again, first metal material layer 23 optionally is disposed at wiring layer 25 tops again.
Fig. 3 is along the I-among Fig. 2 B IFirst embodiment of profile drawing.In conjunction with Fig. 2 A and 2B, with reference to Fig. 3, in the present embodiment, the multicore sheet AAQFN packaging 200 that connects up again comprises the pin 21 that is the face battle array and arranges, insulation filling material 22, first metal material layer 23, second metal material layer 24, wiring layer 25, capsulation material 26, female IC chip 27, adhesive material 28, plain conductor 29 and sub-IC chip 30 again.
Pin 21 is the face battle array in the multicore sheet AAQFN packaging 200 that connects up again arranges, and its shape of cross section is rectangular.Insulation filling material 22 is disposed between pin 21 and the pin 21, and is disposed at the below of wiring layer 25 again, and the zone of wiring layer more than 25 adopts capsulation material 26 to coat sealing again.First metal material layer 23 is arranged around female IC chip 27, and optionally is disposed at the surface of wiring layer 25 again.Second metal material layer 24 is disposed at the lower surface of pin 21.Pin 21 is realized and being connected of first metal material layer 23 by wiring layer 25 again.Female IC chip 27 is disposed at the center of the multicore sheet AAQFN packaging 200 that connects up again by adhesive material 28, sub-IC chip 30 is disposed at the top of female IC chip 27 by adhesive material 28, female IC chip 27 is connected to first metal material layer 23 by plain conductor 29, and sub-IC chip 30 is connected to first metal material layer 23 by plain conductor 29.26 pairs of the capsulation materials multicore sheet AAQFN packaging 200 that connects up again plays the effect of supporting with protection.
Fig. 4 is along the I-among Fig. 2 B ISecond embodiment of profile drawing.In conjunction with Fig. 2 A and 2B, with reference to Fig. 4, in the present embodiment, the multicore sheet AAQFN packaging 200 that connects up again comprises the pin 21 that is the face battle array and arranges, insulation filling material 22, first metal material layer 23, second metal material layer 24, wiring layer 25, capsulation material 26, female IC chip 27, adhesive material 28, plain conductor 29, sub-IC chip 30 and separator material 31 again.
Pin 21 is the face battle array in the multicore sheet AAQFN packaging 200 that connects up again arranges, and its shape of cross section is rectangular.Insulation filling material 22 is disposed between pin 21 and the pin 21, and is disposed at the below of wiring layer 25 again, and the zone of wiring layer more than 25 adopts capsulation material 26 to coat sealing again.First metal material layer 23 is arranged around female IC chip 27, and optionally is disposed at the surface of wiring layer 25 again.Second metal material layer 24 is disposed at the lower surface of pin 21.Pin 21 is realized and being connected of first metal material layer 23 by wiring layer 25 again.Female IC chip 27 is disposed at the center of the multicore sheet AAQFN packaging 200 that connects up again by adhesive material 28, separator material 31 is disposed at the top of female IC chip 27, sub-IC chip 30 is disposed at the top of separator material 31, female IC chip 27 is connected to first metal material layer 23 by plain conductor 29, and sub-IC chip 30 is connected to first metal material layer 23 by plain conductor 29.26 pairs of the capsulation materials multicore sheet AAQFN packaging 200 that connects up again plays the effect of supporting with protection.
Fig. 5 is along the I-among Fig. 2 B IThe 3rd embodiment of profile drawing.In conjunction with Fig. 2 A and 2B, with reference to Fig. 5, in the present embodiment, the multicore sheet AAQFN packaging 200 that connects up again comprises the pin 21 that is the face battle array and arranges, insulation filling material 22, first metal material layer 23, second metal material layer 24, wiring layer 25, capsulation material 26, female IC chip 27, adhesive material 28, plain conductor 29 and sub-IC chip 30 and welding material 32 again.
Pin 21 is the face battle array in the multicore sheet AAQFN packaging 200 that connects up again arranges, and its shape of cross section is rectangular.Insulation filling material 22 is disposed between pin 21 and the pin 21, and is disposed at the below of wiring layer 25 again, and the zone of wiring layer more than 25 adopts capsulation material 26 to coat sealing again.First metal material layer 23 is arranged around female IC chip 27, and optionally is disposed at the surface of wiring layer 25 again.Second metal material layer 24 is disposed at the lower surface of pin 21.Pin 21 is realized and being connected of first metal material layer 23 by wiring layer 25 again.Female IC chip 27 is disposed at the center of the multicore sheet AAQFN packaging 200 that connects up again by adhesive material 28, sub-IC chip 30 passes through welding material 32 flip-chip configuration in the top of female IC chip 27, female IC chip 27 is connected to first metal material layer 23 by plain conductor 29, and sub-IC chip 30 is connected to first metal material layer 23 by plain conductor 29.26 pairs of the capsulation materials multicore sheet AAQFN packaging 200 that connects up again plays the effect of supporting with protection.
Description to embodiment of the present utility model is for effectively illustrating and describe the purpose of this utility model, be not in order to limit the utility model, those skilled in the art is to be understood that under any: under the condition that does not break away from utility model design of the present utility model and scope, can change the foregoing description.So the utility model is not limited to disclosed specific embodiment, but cover the modification in defined essence of the present utility model of claim and the scope.

Claims (3)

1. multicore sheet AAQFN packaging that connects up again is characterized in that:
Pin is the face battle array and arranges in packaging;
Insulation filling material is disposed between pin and the pin;
Female IC chip is disposed at the center of packaging by adhesive material;
Sub-IC chip is disposed at the top of female IC chip by adhesive material;
First metal material layer is around female IC arrangements of chips;
Pin is realized and being connected of first metal material layer by wiring layer again;
Second metal material layer is disposed at the lower surface of pin;
Female IC chip is connected to first metal material layer by plain conductor;
Sub-IC chip is connected to first metal material layer by plain conductor;
Capsulation material coats the above-mentioned female IC chip of sealing, sub-IC chip, adhesive material, plain conductor, first metal material layer and wiring layer again, only exposes second metal material layer that is disposed at the pin lower surface.
2. multicore sheet AAQFN packaging that connects up again is characterized in that:
Pin is the face battle array and arranges in packaging;
Insulation filling material is disposed between pin and the pin;
Female IC chip is disposed at the center of packaging by adhesive material;
Separator material is disposed at the top of female IC chip;
Sub-IC chip configuration is in the top of separator material;
First metal material layer is around female IC arrangements of chips;
Pin is realized and being connected of first metal material layer by wiring layer again;
Second metal material layer is disposed at the lower surface of pin;
Female IC chip is connected to first metal material layer by plain conductor;
Sub-IC chip is connected to first metal material layer by plain conductor;
Capsulation material coats the above-mentioned female IC chip of sealing, sub-IC chip, separator material, adhesive material, plain conductor, first metal material layer and wiring layer again, only exposes second metal material layer that is disposed at the pin lower surface.
3. multicore sheet AAQFN packaging that connects up again is characterized in that:
Pin is the face battle array and arranges in packaging;
Insulation filling material is disposed between pin and the pin;
Female IC chip is disposed at the center of packaging by adhesive material;
Sub-IC chip passes through the welding material flip-chip configuration in the top of female IC chip;
First metal material layer is around female IC arrangements of chips;
Pin is realized and being connected of first metal material layer by wiring layer again;
Second metal material layer is disposed at the lower surface of pin;
Female IC chip is connected to first metal material layer by plain conductor;
Capsulation material coats the above-mentioned female IC chip of sealing, sub-IC chip, welding material, adhesive material, plain conductor, first metal material layer and wiring layer again, only exposes second metal material layer that is disposed at the pin lower surface.
CN2012206990105U 2012-12-17 2012-12-17 Re-wiring multi-chip AAQFN packaging device Expired - Fee Related CN203085511U (en)

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Application Number Priority Date Filing Date Title
CN2012206990105U CN203085511U (en) 2012-12-17 2012-12-17 Re-wiring multi-chip AAQFN packaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012206990105U CN203085511U (en) 2012-12-17 2012-12-17 Re-wiring multi-chip AAQFN packaging device

Publications (1)

Publication Number Publication Date
CN203085511U true CN203085511U (en) 2013-07-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594447A (en) * 2013-10-24 2014-02-19 天水华天科技股份有限公司 IC chip stack packaged component large in packaging density and good in high frequency performance and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103594447A (en) * 2013-10-24 2014-02-19 天水华天科技股份有限公司 IC chip stack packaged component large in packaging density and good in high frequency performance and manufacturing method thereof
CN103594447B (en) * 2013-10-24 2017-01-04 天水华天科技股份有限公司 IC chip stacked packaging piece that the big high frequency performance of packaging density is good and manufacture method

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