CN205621701U - Plane array does not have pin CSP packaging part - Google Patents
Plane array does not have pin CSP packaging part Download PDFInfo
- Publication number
- CN205621701U CN205621701U CN201620392697.6U CN201620392697U CN205621701U CN 205621701 U CN205621701 U CN 205621701U CN 201620392697 U CN201620392697 U CN 201620392697U CN 205621701 U CN205621701 U CN 205621701U
- Authority
- CN
- China
- Prior art keywords
- exit
- packaging part
- resin bed
- resin layer
- nickel dam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a plane array does not have pin CSP packaging part, include a plurality of each other about separated the surface all with the end of drawing that has the nickel dam, the stack has the resin layer on the nickel dam to fill adjacent upper end cavity of drawing forth between the end, be equipped with a plurality of copper facing through -holes that communicate with the nickel dam on the resin layer, the copper facing through -hole communicates through the printing line, and it has the IC chip to paste, there is the plastic -sealed body on the resin layer. The copper alloy thin slice of nickel dam is plated to the sculpture, and a plurality of copper facing through -hole and many printing lines that feed through nickel dams are made to the resin layer that superposes on the copper alloy thin slice on the resin layer, paste the IC chip on the resin layer, and the plastic envelope makes the CSP packaging part. This CSP for the packaging part resin layer realized encapsulated circuit's rewiring through the printing line as middle supporting layer, be the end of drawing of wrapper spare plane array and distribute in the plastic -sealed body bottom, make the packaging part can hold more leading -out terminal in the unit erection space.
Description
Technical field
This utility model belongs to electronic device and manufactures technical field of semiconductor encapsulation, relates to a kind of face array without pin CSP
Packaging part.
Background technology
Since electronic device manufacturing industry produces, semicon industry provides various packaging part to encapsulate chip also
Electrical connection is provided for semiconductor element.Along with the development of the emerging technology such as mobile communication equipment, smart mobile phone, semiconductor package
Dress gradually trends towards high density, miniaturization.
QFN(Quad Flat No-lead Package) be in order to tackle semiconductor packing device high density, miniaturization is sent out
A kind of leadless packages opened up and produce.QFN square or rectangular, there is an exposed weldering of large area package bottom middle position
Dish, the encapsulation periphery around big pad has the conductive welding disk realizing electrical connection.Owing to QFN encapsulates unlike traditional SOIC
Encapsulation and TSOP encapsulation have Larus ridibundus wing pin like that, and the conductive path between internal pin and pad is short, electrodynamic capacity and
In packaging body, routing resistance is the lowest, so it is provided that the electrical property of brilliance.But due to the restriction of QFN encapsulating structure, QFN seals
The pin of piece installing can only be distributed in surrounding bottom plastic-sealed body, and number of pin is maintained between 12～72.Along with electronic information technology
Fast development, the leading-out terminal that electronic encapsulation device needs gets more and more, and QFN encapsulation can not meet high density, draws more
The encapsulation requirement of end, needs to develop a kind of novel encapsulated knot that can accommodate more exit on the basis of original QFN encapsulates
Structure replaces original QFN pin to be distributed in the design of surrounding bottom plastic-sealed body, by the large area of package bottom middle position
Exposed pads exit replaces, and can accommodate more leading-out terminal in per installation area.
Summary of the invention
The purpose of this utility model is to provide a kind of face array without pin CSP packaging part, it is possible in per installation area
Accommodating more leading-out terminal, substitute original QFN and pin is distributed in the design of surrounding bottom plastic-sealed body, making pin is face
The formal distribution of array is bottom packaging part.
For achieving the above object, this utility model be the technical scheme is that a kind of face array encapsulates without pin CSP
Part, including multiple mutual disjunct exits, the upper and lower surface of exit is all plated with nickel dam；It is positioned at table on exit
Being superimposed with resin bed on the nickel dam in face, resin bed covers all of nickel dam being positioned at exit upper surface, and fills adjacent extraction
Upper end cavity between end；Resin bed is provided with the copper plated through holes that quantity is identical with exit quantity, a copper plated through holes and one
The nickel dam connection of individual exit upper surface, resin bed upper surface is provided with a plurality of track, with the copper facing above string exit
Through hole is connected by a track, and resin bed is pasted with IC chip, and IC chip is connected with track by bonding wire；Resin
Layer is provided with plastic-sealed body, and IC chip, bonding wire, track and resin bed are all packaged in plastic-sealed body；Exit bottom is coated with
Soldering paste.
This utility model packaging part is a kind of without pin, highdensity CSP encapsulation, compact conformation.Relative to same number of pins
QFN encapsulation, this encapsulation needs erection space less.Existing QFN encapsulates, and lower center position has a large area naked
Dew pad, the encapsulation periphery around big pad has the conductive welding disk realizing electrical connection, but large area exposed pads occupies
Substantial amounts of erection space, makes the packaging part can not accommodate more leading-out terminal.This utility model resin bed is as centre
Supporting layer, achieves connecting up again of encapsulated circuit by track, is that face array distribution is at plastic packaging by the exit of packaging
Bottom body, enable packaging part can accommodate more leading-out terminal in per installation area.
Accompanying drawing explanation
Fig. 1 is the profile of this utility model CSP packaging part.
Fig. 2 is the schematic diagram of multiple exits arrangement in Fig. 1.
In figure: 1. exit, 2. resin bed, 3. soldering paste, 4. track, 5. copper plated through holes, 6. nickel dam, 7. tack coat,
8.IC chip, 9. plastic-sealed body, 10. bonding welding pad, 11. bonding wires, 12. upper end cavitys, 13. lower end cavitys, 14. spaces.
Detailed description of the invention
With detailed description of the invention, this utility model is described in detail below in conjunction with the accompanying drawings.
In using lead frame as the packaging part of exit, due to the limitation of frame structure, this exit can only be distributed
In the bottom surrounding of packaging part, or draw from the side of packaging part, make packaging part can not accommodate more leading-out terminal, unit
The leading-out terminal limited amount that can accommodate in erection space, it is impossible to meet the encapsulation requirement of high density, many exits.In order to overcome
Existing packaging part exist problem, this utility model provide a kind of structure as shown in Figure 1 can accommodate more leading-out terminal
Face array without pin CSP packaging part, this packaging part includes multiple mutual disjunct exit 1, and multiple exits 1 are with face array
Mode arranges, and such as Fig. 2, forms upper and lower two cavitys between adjacent exit 1, and cavity above is upper end cavity 12, position
Cavity in lower section is lower end cavity 13, has space 14, the upper and lower surface of exit 1 all to plate between adjacent exit 1
It is covered with nickel dam 6；Being positioned on the nickel dam 6 of exit 1 upper surface and be superimposed with resin bed 2, resin bed 2 covers and all of is positioned at exit
The nickel dam 6 of 1 upper surface, and fill all of upper end cavity 12；Resin bed 2 is provided with the plating that quantity is identical with exit 1 quantity
Copper vias 5, a copper plated through holes 5 connects with the nickel dam 6 of exit 1 upper surface, and resin bed 2 upper surface is provided with a plurality of print
Line 4 processed, is connected by a track 4 with the copper plated through holes 5 above string exit 1, and resin bed 2 is glued by tack coat 7
Posting IC chip 8, the bonding welding pad 10 on IC chip 8 is connected with track 4 by bonding wire 11；Resin bed 2 is provided with plastic packaging
Body 9, plastic-sealed body 9 encloses IC chip 8, bonding wire 11, track 4 and resin bed 2；Exit 1 bottom is coated with soldering paste 3, shape
Semicircular bump point, adjacent bump point is become to be not attached to mutually.
In this utility model packaging part: exit 1 is arranged in bottom packaging part in the way of the array of face, and it is coated with in outside
Soldering paste forms semicircle bump point, for realizing the connection with external circuit；Resin bed 2 is used for supporting track 4 and printing
Line 4 and exit 1 are separated from each other；Exit 1 and track 4 are coupled together by copper plated through holes 5；The Main Function of track 4 is
Realize the redistribution of circuit；Bonding wire 11 realizes the electrical connection of IC chip 8 and bonding welding pad 10.
This utility model CSP packaging part resin bed 2 replaces substrate as the intermediate layer of packaging part, it is achieved encapsulated circuit
Connect up again, exit 1 is distributed to the bottom of packaging part, enable packaging part to accommodate more extraction in per installation area
Terminal.
Comparison between table 1 this utility model packaging part and QFN packaging part
As can be seen from Table 1, (the exit quantity of unit are refers to exit to this utility model packaging part unit are
Ratio with erection space) exit quantity is 1.31, QFN encapsulation unit are exit quantity is 0.50, this utility model
Packaging part unit are exit quantity is 2.62 times of QFN encapsulation, and packaging density is significantly larger than QFN encapsulation.
The manufacture method of this utility model packaging part, particularly as follows: prepare one piece of upper and lower surface be all coated with nickel dam 6
Copper alloy sheet, then etches upper end cavity 12 and lower end cavity 13 in this copper alloy sheet upper and lower surface, is formed
Multiple exits 1 of face array arrangement, the plurality of exit 1 forms lead frame, sees Fig. 2, now upper end cavity 12 and lower end
Cavity 13 does not connects completely, resist layer when functioning as etching upper end cavity 12 and lower end cavity 13 of nickel dam 6；Under
One step, on the lead frames one layer of resin bed 2 of surface superposition, resin bed 2 is filled upper end cavity 12, is then made on resin bed 2
Produce multiple copper plated through holes 6, copper plated through holes 6 and an exit top nickel dam connect, then power at resin bed 2
Plating one layer of copper and etch a plurality of mutual disconnected track 4, a track 4 connects multiple platings on string exit 1 top
Copper vias 6；
Use binding agent to be pasted on resin bed 2 by IC chip 8, and with bonding wire 11, track 4 and IC chip 8 is connected
Get up；Then, with plastic-sealed body 9, IC chip 8, bonding wire 11, track 4 and resin bed 2 are encapsulated.Afterwards, etching is used
Technique etching lower end cavity 13, is kept completely separate adjacent exit 1 and comes；Finally use pit template, this pit template
Pit shape and size match with the shape and size of exit 1 bottom, fill up soldering paste in the pit of this pit template, will
The pit filling up soldering paste is put in exit 1 bottom, makes one layer of soldering paste 3 of exit 1 lower adhesive form semicircular bump point.
It is described above embodiment of the present utility model and manufacture method.It will be appreciated, however, that without departing from this reality
In the case of novel spirit and scope, various modifications may be made.
Claims (2)
1. a face array is without pin CSP packaging part, it is characterised in that include multiple mutual disjunct exit (1), exit
(1) upper and lower surface is all plated with nickel dam (6)；It is positioned on the nickel dam (6) of exit (1) upper surface and is superimposed with resin bed
(2), resin bed (2) covers all of nickel dam (6) being positioned at exit (1) upper surface, and fills between adjacent exit (1)
Upper end cavity (12)；Resin bed (2) is provided with the copper plated through holes (5) that quantity is identical with exit (1) quantity, a copper plated through holes
(5) nickel dam (6) with exit (1) upper surface connects, and resin bed (2) upper surface is provided with a plurality of track (4), same
The copper plated through holes (5) of row exit (1) top is connected by a track (4), and resin bed (2) is pasted with IC chip (8),
IC chip (8) is connected with track (4) by bonding wire (11)；Resin bed (2) is provided with plastic-sealed body (9), IC chip (8), key
Plying (11), track (4) and resin bed (2) are all packaged in plastic-sealed body (9)；Exit (1) bottom is coated with soldering paste (3).
The most according to claim 1 array is without pin CSP packaging part, it is characterised in that multiple exits (1) are with face battle array
Row mode arranges, and forms upper and lower two cavitys between adjacent exit (1), and cavity above is upper end cavity (12), position
Cavity in lower section is lower end cavity (13).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620392697.6U CN205621701U (en) | 2016-05-04 | 2016-05-04 | Plane array does not have pin CSP packaging part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620392697.6U CN205621701U (en) | 2016-05-04 | 2016-05-04 | Plane array does not have pin CSP packaging part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205621701U true CN205621701U (en) | 2016-10-05 |
Family
ID=57024977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620392697.6U Withdrawn - After Issue CN205621701U (en) | 2016-05-04 | 2016-05-04 | Plane array does not have pin CSP packaging part |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205621701U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789072A (en) * | 2016-05-04 | 2016-07-20 | 天水华天科技股份有限公司 | Area array pin-less CSP packaging member and manufacturing method thereof |
-
2016
- 2016-05-04 CN CN201620392697.6U patent/CN205621701U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789072A (en) * | 2016-05-04 | 2016-07-20 | 天水华天科技股份有限公司 | Area array pin-less CSP packaging member and manufacturing method thereof |
| CN105789072B (en) * | 2016-05-04 | 2018-06-08 | 天水华天科技股份有限公司 | A kind of face array is without pin CSP packaging parts and its manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105428334B (en) | Semiconductor package | |
| CN104064551B (en) | A kind of chip stack package structure and electronic equipment | |
| CN110197793A (en) | A kind of chip and packaging method | |
| TWI482261B (en) | Three-dimensional system-in-package package-on-package structure | |
| CN107104087A (en) | Semiconductor package and forming method thereof | |
| CN109585430A (en) | Stacked semiconductor package assembling comprising two-sided redistribution layer | |
| KR20100050511A (en) | Packaged integrated circuit devices with through-body conductive vias, and methods of making same | |
| CN1937194A (en) | Method of making stacked die package | |
| CN103633076B (en) | Chip type package on encapsulating piece | |
| CN107393880A (en) | Semiconductor package | |
| US8368192B1 (en) | Multi-chip memory package with a small substrate | |
| TW201304018A (en) | Stacked semiconductor package and manufacturing method thereof | |
| CN107622996A (en) | Three-dimensional high-density fan-out package structure and its manufacture method | |
| TW200849536A (en) | Semiconductor package and fabrication method thereof | |
| CN105977220A (en) | Semiconductor package assembly | |
| US20070052082A1 (en) | Multi-chip package structure | |
| CN105990326A (en) | A semiconductor package, a semiconductor package assembly, and a method of manufacturing the semiconductor package | |
| CN206259351U (en) | Electronic equipment | |
| CN105845585A (en) | Chip packaging method and chip packaging structure | |
| CN106409785A (en) | Thin type array plastic packaging part and production method thereof | |
| US20090134504A1 (en) | Semiconductor package and packaging method for balancing top and bottom mold flows from window | |
| CN205621701U (en) | Plane array does not have pin CSP packaging part | |
| CN107946282A (en) | Three-dimensional fan-out package structure and its manufacture method | |
| CN104916599B (en) | Chip packaging method and chip-packaging structure | |
| KR20140045461A (en) | Integrated circuit package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20161005 Effective date of abandoning: 20180608 |