CN106409785A - Thin type array plastic packaging part and production method thereof - Google Patents
Thin type array plastic packaging part and production method thereof Download PDFInfo
- Publication number
- CN106409785A CN106409785A CN201611083734.6A CN201611083734A CN106409785A CN 106409785 A CN106409785 A CN 106409785A CN 201611083734 A CN201611083734 A CN 201611083734A CN 106409785 A CN106409785 A CN 106409785A
- Authority
- CN
- China
- Prior art keywords
- carrier
- chip
- layer
- bond pads
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000002184 metal Substances 0.000 claims abstract description 93
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000010949 copper Substances 0.000 claims description 71
- 229910052802 copper Inorganic materials 0.000 claims description 57
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 40
- 239000010931 gold Substances 0.000 claims description 34
- 238000007747 plating Methods 0.000 claims description 31
- 229910052759 nickel Inorganic materials 0.000 claims description 30
- 229910052737 gold Inorganic materials 0.000 claims description 29
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000000465 moulding Methods 0.000 claims description 15
- 238000005538 encapsulation Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 10
- 238000003466 welding Methods 0.000 claims description 8
- 238000005476 soldering Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 229910000906 Bronze Inorganic materials 0.000 claims description 5
- 239000010974 bronze Substances 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 5
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 5
- 239000010421 standard material Substances 0.000 claims description 5
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 3
- 241000218202 Coptis Species 0.000 claims description 3
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 abstract 2
- 238000009434 installation Methods 0.000 abstract 1
- 238000012856 packing Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001746 injection moulding Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 241001168968 Chroicocephalus ridibundus Species 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- -1 and by bottom Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a thin type array plastic packaging part, including a carrier, lead bonding pads, grounding rings, an IC chip, bonding wires, a plastic packaging body and solder balls. The middle position of the carrier is a chip bonding area DAP, the chip bonding area DAP is provided with the IC chip, edges of the carrier are provided with the grounding rings, and the grounding rings are formed by multiple layers of metals which are superposed on the carrier; the lead bonding pads are arranged at the periphery of the carrier in a multi-row array mode, and are composed of multiple layers of metals; the IC chip is electrically connected to the lead bonding pads and the grounding rings through the bonding wires; the packaging body is used for wrapping the IC chip, the bonding wires, the lead bonding pads and part of the carrier, and the bottom of the carrier is exposed outside the packaging body; and the solder balls are arranged at the bottom of the packaging body, and are connected with the lead bonding pads. The thin type array plastic packaging part provided by the invention is simple and compact in structure, and compared with pin exposure type IC packaging such as SSOP and QFP, the installation area and packaging size required by the thin type array plastic packaging part are smaller.
Description
Technical field
The invention belongs to electronic device manufactures technical field of semiconductor encapsulation and in particular to a kind of thin array Plastic Package
Part and its production method.
Background technology
The encapsulation of integrated circuit just develops towards short, little, light, thin, multiway, high density direction, and its packing forms is by passing
The direction that jack encapsulation (THP) of system installs (SMP) towards surface is developed.DIP, SOIC, QFP, PLCC, PGA, BGA, CSP are each
Plant packing forms to emerge in an endless stream, with the development of information technology, semicon industry requires more and more higher to the encapsulating of circuit.Tradition
Using lead frame as support and conducting structure packing forms, because lead frame has pin, dowel etc. connect knot
Structure, leads to the semiconductor device stray inductance parameter using lead-frame packages very big.As SOP encapsulation, its pin is in that Larus ridibunduss are wing
Outside plastic-sealed body, not only stray inductance parameter is very big, and erection space on substrate for the packaging part is also very big for leakage.
Additionally, in order to improve the performance of semiconductor chip and the current demand to high frequency characteristics, manufacturing and there is good frequency
The semiconductor packages of characteristic becomes more and more important.
Content of the invention
The technical problem to be solved is to provide one kind simple and compact for structure for shortcoming of the prior art
Thin array plastic package.
Another object of the present invention is for providing the production method of above-mentioned thin array plastic package.
Technical problem for solving the present invention adopts the following technical scheme that：
A kind of thin array plastic package, including carrier, wire bond pads, ground loop, IC chip, bonding wire, plastic-sealed body and
Soldered ball, described carrier is made up of Au, Ni, Cu three-layer metal layer successively from bottom, and the centre position of described carrier bonds for chip
Area DAP, described chip bond regions DAP is provided with IC chip, and the edge of described carrier is provided with ground loop, and described ground loop is by folding
The multiple layer metal being added on carrier is constituted；Described wire bond pads are arranged in carrier surrounding in multiple rows of array way, described draw
Line bonding pad is made up of multiple layer metal；Described IC chip is electrically connected with wire bond pads and ground connection by bonding wire
Ring；Described packaging body is used for coating IC chip, bonding wire and wire bond pads and a part for carrier, wherein outside the bottom of carrier
Leakage is outside packaging body；Described soldered ball is arranged at the bottom of packaging body, and is connected with wire bond pads.
Metal layer A u of described carrier is 1-2 μm, and metal level Ni is 4 μm, and metal level Cu is 79 μm.
Described ground loop is made up of metal level Ni and Au successively from bottom, and wherein metal level Ni is 4 μm, and metal layer A u is
1-2μm.
Described wire bond pads start to be made up of metal layer A u, Ni, Cu, Ni, Au successively from bottom, wherein every layer metal
Layer Au is 1-2 μm, and every layer of metal level Ni is 4 μm, and metal level Cu is 79 μm.
Described bonding wire is gold thread or copper cash or silver alloy wire.
The production method of above-mentioned thin array plastic package, its step is as follows：
Step one：Prepare a bronze medal carrier strip first and the photoetching resist of one layer of plating is coated on copper carrier strip, through photoetching process
Form the graph window of needs over the barrier layer, the copper carrier strip of the window's position is exposed；Then in the window's position of copper carrier strip
Plating multiple layers metal, plating removes plating barrier layer after completing, form carrier, wire bond pads and ground loop；Described load
Body is stacked gradually plating Au, Ni, Cu three-layer metal and constitutes by bottom, and wherein metal layer A u is 1-2 μm, and metal level Ni is 4 μm,
Metal level Cu is 79 μm；Described ground loop is stacked gradually electroplated Ni by bottom and Au two metal layers are constituted, wherein metal level Ni
For 4 μm, metal layer A u is 1-2 μm；Described wire bond pads stack gradually plating five layers of gold of Au, Ni, Cu, Ni, Au by bottom
Belong to and constituting, wherein every layer metal layer A u is 1-2 μm, every layer of metal level Ni is 4 μm, and metal level Cu is 79 μm；
Step 2：Using standard material, IC chip is bonded in the chip bond regions DAP of carrier, then adopts ball-bonding process with bonding wire
Complete wire bonding, then carry out molded on the copper carrier strip assembling surface after completing to be bonded, complete to IC chip, bonding wire
And the molding encapsulation of wire bond pads, carrier；
Step 3：After molding, with the method for chemical etching, the copper carrier strip of plastic-sealed body bottom is removed；
Step 4：Soldered ball is directed at one by one the bottom that wire bond pads are installed to packaging body, whole moulding band is cut
Cut, isolate single IC package product.
First electroplate one layer 7-21 μm of Sn in ball bond in the bottom of wire bond pads, then adopt Reflow Soldering
Soldered ball is combined by mode with wire bond pads.
A kind of thin array plastic package, described packaging part includes carrier, wire bond pads, IC chip, bonding wire, moulds
Envelope body and soldered ball, described carrier is made up of Au, Ni, Cu three-layer metal layer successively from bottom, and the centre position of described carrier is core
Piece bond regions DAP, described chip bond regions DAP is provided with IC chip, and described wire bond pads are in multiple rows of array way arrangement
In carrier surrounding, described wire bond pads are made up of multiple layer metal；Described IC chip is electrically connected with drawing by bonding wire
Line bonding pad；Described packaging body is used for coating IC chip, bonding wire and wire bond pads and a part for carrier, wherein carrier
Bottom leak outside outside packaging body；Described soldered ball is arranged at the bottom of packaging body, and is connected with wire bond pads.
The beneficial effects of the present invention is simple and compact for structure, with respect to the IC package of the pin leakage such as SSOP, QFP,
Erection space required for thin array plastic package and encapsulation volume are less.Same SSOP, QFP etc. adopt lead frame conduct
Chip bearing, the packing forms of conductive structure compare, although this encapsulation employ in encapsulation process identical with lead frame
The copper carrier strip of material, but do not have copper carrier strip in final encapsulating structure, copper carrier strip is intended only as one and forms carrier and draw
The intermediate tool of line bonding pad.Simultaneously as bonding line is shorter and does not have outer pin so that this packaging part has excellent electricity
Learn performance.
Brief description
Fig. 1 is the generalized section of thin array plastic package of the present invention；
Fig. 2 is the generalized section that present invention plating completes copper carrier strip surface metal-layer；
Fig. 3 is the generalized section of packaging part after present invention molding；
Fig. 4 is the generalized section that the present invention removes packaging part after copper carrier strip；
Fig. 5 is the schematic diagram of the packaging part that the present invention is mounted with after soldered ball；
Fig. 6 is the generalized section of the thin array plastic package that the present invention removes ground loop；
In accompanying drawing：22：Carrier；21：Wire bond pads；23：Ground loop；10：IC chip； 11：Plastic-sealed body；12：Bonding wire；31：
Soldered ball；20：Copper carrier strip.
Specific embodiment
In order that technical problem solved by the invention, technical scheme and beneficial effect become more apparent, below in conjunction with
Drawings and the specific embodiments, the present invention will be described in further detail.
As shown in figure 1, a kind of thin array plastic package includes：Carrier 22, wire bond pads 21, ground loop 23,
IC chip 10, bonding wire 12, plastic-sealed body 11 and soldered ball 31.
Carrier 22 is made up of multiple layer metal, and by carrier base, metal level can be Au, Ni, Cu, wherein metal successively
Layer Au is 1-2 μm, and metal level Ni is 4 μm, and metal level Cu is 79 μm.The centre position of carrier 22 is chip bond regions（DAP）,
The marginal position of carrier 22 is ground loop 23, and ground loop 23 can be consisted of superposition multiple layer metal on carrier, ground loop 23
It is made up of metal level Ni and Au successively from bottom, wherein metal level Ni is 4 μm, metal layer A u is 1-2 μm.Wire bond pads
21 are arranged in carrier 22 surrounding in array way, and wire bond pads 21 are configured to two row's array arrangements；Wire bond pads
21 are made up of multiple layer metal, and by bottom, metal level can be Au, Ni, Cu, Ni, Au, wherein two metal layers Au successively, often
Layer is 1-2 μm, two metal layers Ni, and every layer is 4 μm, and metal level Cu is 79 μm.It may be noted that in the feelings not using longer bonding wire
Under condition, wire bond pads 21 can be arranged to single row or multiple rows（≥3）The mode of row's periphery arrangement.
IC chip 10 is arranged at the chip bond regions of carrier 22 upper surface（DAP）, and be electrically connected at by bonding wire 12 and draw
Line bonding pad 21 and ground loop 23, bonding wire 12 can be gold thread, copper cash or silver alloy wire, and IC chip 10 can adopt bonding die
Glue, glue film etc. are arranged on chip bond regions（DAP）.Packaging body 11 cladding IC chip 10, bonding wire 12 and wire bond pads
21st, a part for carrier 22, the bottom of carrier 22 leaks outside outside plastic-sealed body, can be used as the radiating area of packaging part.Packaging body
11 may include phenolic group resin, epoxy, silicone or other suitable coverings.Packaging body 11 also may include suitably
Filler, the e.g. silicon dioxide of powdery.Can using several encapsulation technologies formed packaging body 11, e.g. compression forming,
Injection moulding.
Soldered ball 31 is arranged at the bottom of packaging body 11, and is connected with wire bond pads 21, be used for realizing packaging part with
The electrical connection of external circuit.Soldered ball 31 can realize the combination with bonding welding pad 21 by modes such as Reflow Solderings.
Can also optionally be removed according to the design requirement ground loop of packaging part.Form a kind of thin array Plastic Package
Part, packaging part includes carrier 22, wire bond pads 21, IC chip 10, bonding wire 12, plastic-sealed body 11 and soldered ball 31, described carrier
22 are made up of Au, Ni, Cu three-layer metal layer successively from bottom, and the centre position of carrier 22 is chip bond regions DAP, and chip bonds
Area DAP is provided with IC chip 10, and described wire bond pads 21 are arranged in carrier 22 surrounding, wire bonding in multiple rows of array way
Pad 21 is made up of multiple layer metal；IC chip 10 is electrically connected with wire bond pads 21 by bonding wire 12；Packaging body 11
For coating a part for IC chip 10, bonding wire 12 and wire bond pads 21 and carrier 22, wherein the bottom leakage of carrier 22
Outside packaging body 11；Soldered ball 31 is arranged at the bottom of packaging body 11, and is connected with wire bond pads 21.
Embodiment 1
A kind of production method of thin array plastic package, its step is as follows：
Step one：Prepare a bronze medal carrier strip 20 first and the barrier layer of one layer of plating is coated on copper carrier strip 20（Photoetching resist）,
Form the graph window of needs through photoetching process over the barrier layer, the copper carrier strip 20 of the window's position is exposed；Then in copper
The window's position plating multiple layers metal of carrier strip 20, plating removes plating barrier layer after completing, form carrier 22, wire bonding weldering
Disk 21 and ground loop 23.Wherein carrier is stacked gradually plating Au, Ni, Cu three-layer metal and constitutes by bottom, and wherein metal layer A u is
2 μm, metal level Ni is 4 μm, and metal level Cu is 79 μm；Ground loop stacks gradually electroplated Ni and Au two metal layers structure by bottom
Become, wherein metal level Ni is 4 μm, metal layer A u is 2 μm；Described wire bond pads by bottom stack gradually plating Au, Ni,
Five layers of metal of Cu, Ni, Au are constituted, and wherein every layer metal layer A u is 2 μm, and every layer of metal level Ni is 4 μm, and metal level Cu is 79 μm；
Step 2：Using standard material, IC chip 10 is bonded in the chip bond regions of carrier 22（DAP）, then adopted with bonding wire 12
Ball-bonding process completes wire bonding, is then molded using compression forming on the copper carrier strip 20 assembling surface after completing to be bonded
Molding, completes the encapsulating to IC chip 10, bonding wire 12 and wire bond pads 21, carrier 22；
Step 3：As shown in figure 4, after molding, the copper carrier strip 20 of plastic-sealed body 11 bottom is removed with the method for chemical etching.?
After copper carrier strip 20 removes, the Au layer of wire bond pads 21 bottom acts as barrier layer, and etching will stop.Now, carry
The bottom of body 22 leaks outside outside plastic-sealed body, can be used as the radiating area of packaging part；
Step 4：Soldered ball 31 is directed at one by one the bottom that wire bond pads 21 are installed to packaging body 11.First in lead during welding
One layer 7 μm of Sn is electroplated in the bottom of bonding welding pad 21, then realizes soldered ball 31 and wire bond pads by the way of Reflow Soldering
21 combination.Finally, whole moulding band is cut, separate and form single IC package product.
Embodiment 2
A kind of production method of thin array plastic package, its step is as follows：
Step one：Prepare a bronze medal carrier strip 20 first and the barrier layer of one layer of plating is coated on copper carrier strip 20（Photoetching resist）,
Form the graph window of needs through photoetching process over the barrier layer, the copper carrier strip 20 of the window's position is exposed；Then in copper
The window's position plating multiple layers metal of carrier strip 20, plating removes plating barrier layer after completing, form carrier 22, wire bonding weldering
Disk 21 and ground loop 23.Wherein carrier, wire bond pads stack gradually plating five layers of metal of Au, Ni, Cu, Ni, Au by bottom
Constitute, wherein metal layer A u is 1 μm, metal level Ni is 4 μm, metal level Cu is 79 μm；
Step 2：Using standard material, IC chip 10 is bonded in the chip bond regions of carrier 22（DAP）, then adopted with bonding wire 12
Ball-bonding process completes wire bonding, is then molded using injection moulding on the copper carrier strip 20 assembling surface after completing to be bonded
Molding, completes the encapsulating to IC chip 10, bonding wire 12 and wire bond pads 21, carrier 22.
Step 3：After molding, with the method for chemical etching, the copper carrier strip 20 of plastic-sealed body 11 bottom is removed.In copper carrier strip
After 20 remove, the Au layer of wire bond pads 21 bottom acts as barrier layer, and etching will stop.Now, carrier 22
Bottom leaks outside outside plastic-sealed body, can be used as the radiating area of packaging part；
Step 4：Soldered ball 31 is directed at one by one the bottom that wire bond pads 21 are installed to packaging body 11.First in lead during welding
One layer 21 μm of Sn is electroplated in the bottom of bonding welding pad 21, then realizes soldered ball 31 and wire bond pads by the way of Reflow Soldering
21 combination.Finally, whole moulding band is cut, separate and form single IC package product.
Embodiment 3
A kind of production method of thin array plastic package, its step is as follows：
Step one：Prepare a bronze medal carrier strip 20 first and the barrier layer of one layer of plating is coated on copper carrier strip 20（Photoetching resist）,
Form the graph window of needs through photoetching process over the barrier layer, the copper carrier strip 20 of the window's position is exposed；Then in copper
The window's position plating multiple layers metal of carrier strip 20, plating removes plating barrier layer after completing, form carrier 22, wire bonding weldering
Disk 21.Wherein carrier, wire bond pads are stacked gradually plating five layers of metal of Au, Ni, Cu, Ni, Au and constitute, wherein by bottom
Metal layer A u is 1 μm, and metal level Ni is 4 μm, and metal level Cu is 79 μm；
Step 2：Using standard material, IC chip 10 is bonded in the chip bond regions of carrier 22（DAP）, then adopted with bonding wire 12
Ball-bonding process completes wire bonding, is then molded using injection moulding on the copper carrier strip 20 assembling surface after completing to be bonded
Molding, completes the encapsulating to IC chip 10, bonding wire 12 and wire bond pads 21, carrier 22.
Step 3：After molding, with the method for chemical etching, the copper carrier strip 20 of plastic-sealed body 11 bottom is removed.In copper carrier strip
After 20 remove, the Au layer of wire bond pads 21 bottom acts as barrier layer, and etching will stop.Now, carrier 22
Bottom leaks outside outside plastic-sealed body, can be used as the radiating area of packaging part；
Step 4：Soldered ball 31 is directed at one by one the bottom that wire bond pads 21 are installed to packaging body 11.First in lead during welding
One layer 21 μm of Sn is electroplated in the bottom of bonding welding pad 21, then realizes soldered ball 31 and wire bond pads by the way of Reflow Soldering
21 combination.Finally, whole moulding band is cut, separate and form single IC package product.
Soldered ball 31 can also directly be formed in the bottom of wire bond pads 21 using methods such as printing, plating, soldered ball can
So that suitable mode is selected according to working condition.
The content of the invention of the present invention is more than described in detail, the major advantage of this packaging part is simple and compact for structure,
With respect to the IC package of the pin leakage such as SSOP, QFP, the erection space required for thin array plastic package and packaging body
Long-pending less.With SSOP, QFP etc. using lead frame as compared with chip bearing, the packing forms of conductive structure, though this encapsulation
In encapsulation process, so employ the copper carrier strip with lead frame phase same material, but do not have copper in final encapsulating structure and carry
Bar, copper carrier strip is intended only as an intermediate tool forming carrier and wire bond pads.Simultaneously as bonding line is shorter and does not have
There is outer pin so that this packaging part has excellent electric property.The packing forms of the present invention 32 pin and 28 traditional pins
PLCC（Plastic Leaded Chip Carrier）As a example encapsulation compares, area (5mm × 5mm) reduces 84%, thickness
(0.9mm) reduce 80%, weight (0.06g) alleviates 95%, and Electronic Packaging ghost effect also improves 50%.This encapsulation tool
Pad pitch is respectively 0.8mm, 0.65mm, 0.5mm and 0.4mm, can provide more than 3 in the case of not using compared with long soldering plate
The pad of row's periphery arrangement, so be especially suitable for applying in mobile phone, digital camera, PDA and other portable miniaturized electronics
High-density printed circuit board on.
In sum although the present invention is disclosed above with embodiment, so it is not limited to the present invention.Institute of the present invention
Belong to and in technical field, have usually intellectual, without departing from the spirit and scope of the present invention, when various changes and profit can be made
Decorations.Therefore, protection scope of the present invention is worked as and is defined depending on those as defined in claim.
Claims (8)
1. a kind of thin array plastic package it is characterised in that：Described packaging part includes carrier（22）, wire bond pads
（21）, ground loop（23）, IC chip（10）, bonding wire（12）, plastic-sealed body（11）And soldered ball（31）, described carrier（22）From bottom according to
Secondary be made up of Au, Ni, Cu three-layer metal layer, described carrier（22）Centre position be chip bond regions DAP, described chip bonding
Area DAP is provided with IC chip（10）, described carrier（22）Edge be provided with ground loop（23）, described ground loop（23）By being superimposed
In carrier（22）On multiple layer metal constitute；Described wire bond pads（21）It is arranged in carrier in multiple rows of array way（22）Four
Week, described wire bond pads（21）It is made up of multiple layer metal；Described IC chip（10）By bonding wire（12）It is electrically connected with
In wire bond pads（21）And ground loop（23）；Described packaging body（11）For coating IC chip（10）, bonding wire（12）And draw
Line bonding pad（21）And carrier（22）A part, wherein carrier（22）Bottom leak outside in packaging body（11）Outside；Described
Soldered ball（31）It is arranged at packaging body（11）Bottom, and same wire bond pads（21）It is connected.
2. a kind of thin array plastic package according to claim 1 it is characterised in that：Described carrier（22）Metal
Layer Au is 1-2 μm, and metal level Ni is 4 μm, and metal level Cu is 79 μm.
3. a kind of thin array plastic package according to claim 1 and 2 it is characterised in that：Described ground loop（23）
It is made up of metal level Ni and Au successively from bottom, wherein metal level Ni is 4 μm, metal layer A u is 1-2 μm.
4. a kind of thin array plastic package according to claim 3 it is characterised in that：Described wire bond pads
（21）Start to be made up of metal layer A u, Ni, Cu, Ni, Au successively from bottom, wherein every layer metal layer A u is 1-2 μm, every layer of metal
Layer Ni is 4 μm, and metal level Cu is 79 μm.
5. a kind of thin array plastic package according to claim 1 it is characterised in that：Described bonding wire（12）For gold thread
Or copper cash or silver alloy wire.
6. a kind of thin array plastic package described in any of the above-described claim production method it is characterised in that step such as
Under：
Step one：Prepare a bronze medal carrier strip first（20）And in copper carrier strip（20）The photoetching resist of upper one layer of plating of coating, passes through
Photoetching process forms the graph window of needs, the copper carrier strip of the window's position over the barrier layer（20）It is exposed；Then carry in copper
Bar（20）The window's position plating multiple layers metal, plating complete after remove plating barrier layer, formed carrier（22）, wire bonding
Pad（21）And ground loop（23）；Described carrier（22）Stacked gradually plating Au, Ni, Cu three-layer metal to constitute, wherein by bottom
Metal layer A u is 1-2 μm, and metal level Ni is 4 μm, and metal level Cu is 79 μm；Described ground loop（23）Electricity is stacked gradually by bottom
Plating Ni and Au two metal layers are constituted, and wherein metal level Ni is 4 μm, and metal layer A u is 1-2 μm；Described wire bond pads
（21）Stacked gradually plating five layers of metal of Au, Ni, Cu, Ni, Au to constitute by bottom, wherein every layer metal layer A u is 1-2 μm, every layer
Metal level Ni is 4 μm, and metal level Cu is 79 μm；
Step 2：Using standard material by IC chip（10）It is bonded in carrier（22）Chip bond regions DAP, then use bonding wire（12）
Wire bonding is completed using ball-bonding process, then completes the copper carrier strip after being bonded（20）Carry out molded on assembling surface,
Complete to IC chip（10）, bonding wire（12）And wire bond pads（21）, carrier（22）Molding encapsulation；
Step 3：After molding, with the method for chemical etching by plastic-sealed body（11）The copper carrier strip of bottom（20）Remove；
Step 4：By soldered ball（31）It is directed at wire bond pads one by one（21）It is installed to packaging body（11）Bottom, to whole mould
Mould band to be cut, isolate single IC package product.
7. a kind of thin array plastic package according to claim 6 production method it is characterised in that：In soldered ball
（31）First in wire bond pads during welding（21）Bottom electroplate one layer 7-21 μm of Sn, then general using Reflow Soldering by the way of
Soldered ball（31）With wire bond pads（21）In conjunction with.
8. a kind of thin array plastic package it is characterised in that：Described packaging part includes carrier（22）, wire bond pads
（21）, IC chip（10）, bonding wire（12）, plastic-sealed body（11）And soldered ball（31）, described carrier（22）From bottom successively by Au, Ni,
Cu three-layer metal layer is constituted, described carrier（22）Centre position be chip bond regions DAP, described chip bond regions DAP setting
There is IC chip（10）, described wire bond pads（21）It is arranged in carrier in multiple rows of array way（22）Surrounding, described lead key
Close pad（21）It is made up of multiple layer metal；Described IC chip（10）By bonding wire（12）It is electrically connected with wire bond pads
（21）；Described packaging body（11）For coating IC chip（10）, bonding wire（12）And wire bond pads（21）And carrier（22）'s
A part, wherein carrier（22）Bottom leak outside in packaging body（11）Outside；Described soldered ball（31）It is arranged at packaging body（11）'s
Bottom, and same wire bond pads（21）It is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611083734.6A CN106409785A (en) | 2016-11-30 | 2016-11-30 | Thin type array plastic packaging part and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611083734.6A CN106409785A (en) | 2016-11-30 | 2016-11-30 | Thin type array plastic packaging part and production method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106409785A true CN106409785A (en) | 2017-02-15 |
Family
ID=58084155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611083734.6A Pending CN106409785A (en) | 2016-11-30 | 2016-11-30 | Thin type array plastic packaging part and production method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106409785A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107146777A (en) * | 2017-05-27 | 2017-09-08 | 江苏长电科技股份有限公司 | One kind exempts from cutting encapsulating structure and its manufacturing process |
| CN111653542A (en) * | 2020-06-17 | 2020-09-11 | 佛山市蓝箭电子股份有限公司 | Semiconductor package lead frame |
| CN111696873A (en) * | 2020-06-17 | 2020-09-22 | 佛山市蓝箭电子股份有限公司 | Semiconductor packaging method and packaged chip |
| WO2021233333A1 (en) * | 2020-05-22 | 2021-11-25 | 东莞链芯半导体科技有限公司 | Semiconductor encapsulation structure and encapsulation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859713A (en) * | 2009-04-10 | 2010-10-13 | 日月光半导体制造股份有限公司 | Advanced quad flat non-leaded package and manufacture method thereof |
| CN102024721A (en) * | 2009-08-06 | 2011-04-20 | 美士美积体产品公司 | Method of forming solderable side-surface terminals of quad no-lead frame (qfn) integrated circuit packages |
| CN102208389A (en) * | 2010-04-28 | 2011-10-05 | 先进封装技术私人有限公司 | Semiconductor package, substrate and manufacturing method thereof |
| CN206282839U (en) * | 2016-11-30 | 2017-06-27 | 天水华天科技股份有限公司 | A kind of thin array plastic package |
-
2016
- 2016-11-30 CN CN201611083734.6A patent/CN106409785A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101859713A (en) * | 2009-04-10 | 2010-10-13 | 日月光半导体制造股份有限公司 | Advanced quad flat non-leaded package and manufacture method thereof |
| CN102024721A (en) * | 2009-08-06 | 2011-04-20 | 美士美积体产品公司 | Method of forming solderable side-surface terminals of quad no-lead frame (qfn) integrated circuit packages |
| CN102208389A (en) * | 2010-04-28 | 2011-10-05 | 先进封装技术私人有限公司 | Semiconductor package, substrate and manufacturing method thereof |
| CN206282839U (en) * | 2016-11-30 | 2017-06-27 | 天水华天科技股份有限公司 | A kind of thin array plastic package |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107146777A (en) * | 2017-05-27 | 2017-09-08 | 江苏长电科技股份有限公司 | One kind exempts from cutting encapsulating structure and its manufacturing process |
| WO2021233333A1 (en) * | 2020-05-22 | 2021-11-25 | 东莞链芯半导体科技有限公司 | Semiconductor encapsulation structure and encapsulation method thereof |
| CN111653542A (en) * | 2020-06-17 | 2020-09-11 | 佛山市蓝箭电子股份有限公司 | Semiconductor package lead frame |
| CN111696873A (en) * | 2020-06-17 | 2020-09-22 | 佛山市蓝箭电子股份有限公司 | Semiconductor packaging method and packaged chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7005327B2 (en) | Process and structure for semiconductor package | |
| US6762118B2 (en) | Package having array of metal pegs linked by printed circuit lines | |
| US7615859B2 (en) | Thin semiconductor package having stackable lead frame and method of manufacturing the same | |
| US7834469B2 (en) | Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame | |
| US20070122940A1 (en) | Method for packaging a semiconductor device | |
| US8367473B2 (en) | Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof | |
| US20070099341A1 (en) | Method of making stacked die package | |
| US20090278243A1 (en) | Stacked type chip package structure and method for fabricating the same | |
| US20080160678A1 (en) | Method for fabricating semiconductor package | |
| TW201209991A (en) | Stackable molded microelectronic packages with area array unit connectors | |
| JP2003332508A (en) | Semiconductor device and its manufacturing method | |
| US7202554B1 (en) | Semiconductor package and its manufacturing method | |
| US6242283B1 (en) | Wafer level packaging process of semiconductor | |
| CN106409785A (en) | Thin type array plastic packaging part and production method thereof | |
| US20080237833A1 (en) | Multi-chip semiconductor package structure | |
| US20130009311A1 (en) | Semiconductor carrier, package and fabrication method thereof | |
| CN103021969B (en) | substrate, semiconductor package and manufacturing method thereof | |
| US6344687B1 (en) | Dual-chip packaging | |
| US6380062B1 (en) | Method of fabricating semiconductor package having metal peg leads and connected by trace lines | |
| CN105161475B (en) | With double-round bump point without pin CSP stack packages and its manufacture method | |
| CN206282839U (en) | A kind of thin array plastic package | |
| US20120097429A1 (en) | Package substrate and fabrication method thereof | |
| US20080237831A1 (en) | Multi-chip semiconductor package structure | |
| US20150084171A1 (en) | No-lead semiconductor package and method of manufacturing the same | |
| US20180247886A1 (en) | Electronic package structure and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170215 |