CN107146777A - One kind exempts from cutting encapsulating structure and its manufacturing process - Google Patents
One kind exempts from cutting encapsulating structure and its manufacturing process Download PDFInfo
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- CN107146777A CN107146777A CN201710391468.1A CN201710391468A CN107146777A CN 107146777 A CN107146777 A CN 107146777A CN 201710391468 A CN201710391468 A CN 201710391468A CN 107146777 A CN107146777 A CN 107146777A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Exempt from cutting encapsulating structure and its manufacturing process the present invention relates to one kind, the structure includes pin（4）And Ji Dao（3）, the pin（4）Ji Dao is arranged around with single group or multigroup mode（3）Around, the Ji Dao（3）Pass through bonding material or solder（5）It is provided with chip（6）, the chip（6）Pass through metal wire（7）With pin（4）It is electrically connected with, the chip（6）, metal wire（7）, Ji Dao（3）And pin（4）Periphery be coated with plastic packaging material（9）, the Ji Dao（3）With pin（4）Lower surface is exposed to plastic packaging material（9）Outside, the plastic packaging material（9）Two parts above and below being divided into sideways, top is divided into sloping portion（10）, bottom is divided into vertical portion（11）.The present invention can make non-exterior pin semiconductor encapsulating structure can be with singulation while saving and cutting this work flow, so as to avoid the problem of pin produces burr in the cutting process present in prior art, the reliability of non-exterior pin semiconductor encapsulating structure is improved.
Description
Technical field
Exempt from cutting encapsulating structure and its manufacturing process the present invention relates to one kind, belong to technical field of semiconductor encapsulation.
Background technology
General existing quad flat non-leaded chip package（QFN）Or small outline no-lead encapsulation（SON）Manufacturing process on, it is first
First need to prepare a flat and untreated metallic plate, then, first time half-etching is carried out to the first surface of the metallic plate
（half-etching）Operation, thus the lower surface of Ji Dao and pin is formed, wherein several pins are with single group or many prescriptions
Formula is arranged around around the Ji Dao.After first time half-etching operation, the is carried out to the second surface of the metallic plate
Secondary half-etching（half-etching）Operation, makes the Ji Dao and the pin separate each other, thus is formed without outer pin type
Lead frame, while the adjacent leads of adjacent cells are temporarily linked together with middle muscle on lead frame.
After lead frame making is completed, chip is fixed in the die pad, and entered using several described bonding wires
Row routing operation, by several connection pads on the chip, described several pins are electrically connected.Then recycle
Plastic packaging material carries out encapsulating operation, plastic packaging material is coated the upper surface of the chip, bonding wire and lead frame, the lead frame
Lower surface is exposed to outside plastic packaging material（Referring to Fig. 1）.After encapsulating operation, the middle muscle portion point of lead frame is cut off using cutter
And the plastic packaging material on middle muscle, so that adjacent unit is separated each other, to complete non-exterior pin semiconductor encapsulating structure monomer
Change.
（Referring to Fig. 2）In above-mentioned non-exterior pin semiconductor encapsulating structure, (quad flat non-leaded chip package or small profile are without drawing
Pin encapsulate) cutting operation when, cutter cut plastic packaging material while can also cut to muscle in lead frame metal, due to cutting
Cutter have with soft metal friction can drawn metal and produce burr, produce horizontal burr is easily in contact with adjacent pin, leads
Cause occur bridge joint phenomenon between pin, if the coplanarity of some pins or certain single pin can be caused by producing longitudinal burr again
It is bad, cause the defect of rosin joint or missing solder occur during welding, in order to which anti-phenomenon here occurs that cutting speed must be reduced, but
Therefore cutting efficiency is caused to reduce；Furthermore, the friction between cutting tool and plastic-sealed body also easily accelerates the consume of cutting tool.
It is therefore necessary to provide a kind of method, to solve the problems of prior art.
The content of the invention
The technical problems to be solved by the invention be for above-mentioned prior art provide one kind exempt from cutting encapsulating structure and its
Manufacturing process, it can make non-exterior pin semiconductor encapsulating structure can be with monomer while saving and cutting this work flow
Change, so as to avoid the problem of pin produces burr in the cutting process present in prior art, raising is partly led without outer pin
The reliability of body encapsulating structure.
Another technical problem to be solved by this invention is to provide one kind for above-mentioned prior art to exempt to cut encapsulating structure
And its manufacturing process, it can realize singulation while saving and cutting this flow chart, can improve plastic packaging body side surface
The efficiency of semiconductor package singulation without outer pin, while can more reduce non-exterior pin semiconductor encapsulating structure monomer
Chemical conversion is originally.
The present invention the used technical scheme that solves the above problems is：One kind exempt from cut encapsulating structure, it include pin and
Ji Dao, the pin is arranged around around Ji Dao with single group or multigroup mode, and the Ji Dao passes through bonding material or solder
Chip is provided with, the chip is electrically connected with by metal wire and pin, the chip, metal wire, Ji Dao and pin
Periphery be coated with plastic packaging material, the Ji Dao is exposed to outside plastic packaging material with pin lower surface, and the plastic packaging material side is divided into
Lower two parts, top is divided into sloping portion, and bottom is divided into vertical portion.
One kind is exempted to cut encapsulating structure, and it, which includes upside-down mounting on pin, the pin, has outside chip, the chip and pin
Enclose and be coated with plastic packaging material, the pin lower surface is exposed to outside plastic packaging material, plastic packaging material side be divided into above and below two parts, on
Part is sloping portion, and bottom is divided into vertical portion.
A kind of manufacturing process for exempting to cut encapsulating structure, the technique comprises the following steps：
Step 1: taking a support plate；
Step 2, pastes on support plate or prints one layer of bonding glue-line；
Step 3, plating Chu Ji islands and pin on bonding glue-line, the pin is arranged around institute with single group or multigroup mode
Around Shu Ji islands；
Step 4: Ji Dao upper surfaces coating bonding material or solder, carry out load and routing operation；
Step 5: carrying out plastic packaging material plastic packaging operation using mould, single product plastic-sealed body is disconnected from each other, and plastic packaging body side surface is divided into
Lower two parts, its middle and upper part is divided into sloping portion, and bottom is divided into vertical portion,；
Step 6: removing the support plate and bonding glue-line at the product back side for completing plastic packaging operation, realization exempts to cut encapsulating structure monomer
Change.
A kind of manufacturing process for exempting to cut encapsulating structure, the technique comprises the following steps：
Step 1: taking a support plate；
Step 2, pastes on support plate or prints one layer of bonding glue-line；
Step 3, pin is electroplated on bonding glue-line；
Step 4: carrying out flip-chip operation on pin；
Step 5: carrying out plastic packaging material plastic packaging operation using mould, single product plastic-sealed body is disconnected from each other, and plastic packaging material side is divided into
Lower two parts, its middle and upper part is divided into sloping portion, and bottom is divided into vertical portion；
Step 6: removing the support plate and bonding glue-line at the product back side for completing plastic packaging operation, realization exempts to cut encapsulating structure monomer
Change.
The material of support plate is copper material, iron material or stainless steel.
The plastic packaging material is using the epoxy resin for having packing material or no-arbitrary pricing material.
Compared with prior art, the advantage of the invention is that：
1st, the present invention can make non-exterior pin semiconductor encapsulating structure can be with monomer while saving and cutting this flow chart
Change, so as to avoid the problem of pin produces burr in the cutting process present in prior art, raising is partly led without outer pin
The reliability of body encapsulating structure；
2nd, the present invention can make non-exterior pin semiconductor encapsulating structure can be with monomer while saving and cutting this flow chart
Change, the efficiency of non-exterior pin semiconductor encapsulating structure singulation can be improved, while non-exterior pin semiconductor encapsulation can be reduced
Structures alone chemical conversion is originally.
Brief description of the drawings
Fig. 1, Fig. 2 make adjacent unit separate schematic diagram each other to carry out cutting to plastic-sealed body in conventional art.
Fig. 3 is a kind of structural representation for exempting to cut encapsulating structure of the present invention.
Fig. 4 ~ Figure 10 is a kind of schematic flow sheet for exempting to cut the manufacturing process of encapsulating structure of the present invention.
Figure 11 is a kind of structural representation for exempting to cut another embodiment of encapsulating structure of the present invention.
Figure 12 ~ Figure 18 is a kind of schematic flow sheet for exempting to cut the manufacturing process of another embodiment of encapsulating structure of the present invention.
Wherein：
Support plate 1
Bond glue-line 2
Base island 3
Pin 4
Bonding material or solder 5
Chip 6
Metal wire 7
Mould 8
Plastic packaging material 9
Sloping portion 10
Vertical portion 11.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment 1：Positive assembling structure
As shown in figure 3, one kind in the present embodiment is exempted to cut encapsulating structure, it includes pin 4 and base island 3, and the pin 4 is with list
Group or multigroup mode are arranged around around base island 3, and the base island 3 is provided with chip 6, institute by bonding material or solder 5
State chip 6 to be electrically connected with pin 4 by metal wire 7, the chip 6, metal wire 7, the periphery of base island 3 and pin 4
Plastic packaging material 9 is coated with, the base island 3 is exposed to outside plastic packaging material 9 with the lower surface of pin 4, above and below the side of plastic packaging material 9 is divided into
Two parts, top is divided into sloping portion, and bottom is divided into vertical portion.
Its manufacturing process comprises the following steps：
Step 1: referring to Fig. 4, taking a support plate, support plate is mainly made for circuit and circuit Rotating fields provide support, this support plate
Material can be copper material, iron material, stainless steel or other metallicses with certain degree of hardness；
Step 2, referring to Fig. 5, pastes on support plate or prints one layer of bonding glue-line；
Step 3, referring to Fig. 6, plating Chu Ji islands and pin on bonding glue-line, the pin is surround with single group or multigroup mode
It is arranged in around the Ji Dao；
Step 4: referring to Fig. 7, Ji Dao upper surfaces coating bonding material or solder carry out load and routing operation；
Step 5: referring to Fig. 8, Fig. 9, carrying out plastic packaging material plastic packaging operation using special dies, single product plastic-sealed body is divided mutually
From, and plastic packaging body side surface be divided into above and below two parts, its middle and upper part is divided into sloping portion, and bottom is divided into vertical portion, the modeling
Envelope material can be using the epoxy resin for having packing material or no-arbitrary pricing material；
Step 6: referring to Figure 10, removing the support plate and bonding glue-line at the product back side for completing plastic packaging operation, diced chip is exempted from realization
Formal dress encapsulating structure singulation.
Embodiment 2：Inverted structure
One kind in such as Figure 11, the present embodiment is exempted to cut encapsulating structure, and it, which includes upside-down mounting on pin 4, the pin 4, chip 6,
The chip 6, the periphery of pin 4 are coated with plastic packaging material 9, and the lower surface of pin 4 is exposed to outside plastic packaging material 9, the plastic packaging
Expect 9 sides be divided into above and below two parts, top is divided into sloping portion 10, and bottom is divided into vertical portion 11.
Its manufacturing process comprises the following steps：
Step 1: referring to Figure 12, taking a support plate, support plate is mainly made for circuit and circuit Rotating fields provide support, this support plate
Material can be copper material, iron material, stainless steel or other materials with certain degree of hardness；
Step 2, referring to Figure 13, pastes on support plate or prints one layer of bonding glue-line；
Step 3, referring to Figure 14, pin is electroplated on bonding glue-line；
Step 4: referring to Figure 15, flip-chip operation is carried out on pin；
Step 5: referring to Figure 16, Figure 17, carrying out plastic packaging material plastic packaging operation using special dies, making single product plastic-sealed body mutual
Separation, and plastic packaging body side surface be divided into above and below two parts, its middle and upper part is divided into sloping portion 10, and bottom is divided into vertical portion 11,
The plastic packaging material can be using the epoxy resin for having packing material or no-arbitrary pricing material；
Step 6: referring to Figure 18, removing the support plate and bonding glue-line at the product back side for completing plastic packaging operation, diced chip is exempted from realization
Flip-chip packaged structures alone.
In addition to the implementation, present invention additionally comprises have other embodiment, all use equivalent transformation or equivalent replacements
The technical scheme that mode is formed, all should fall within the scope of the hereto appended claims.
Claims (6)
1. one kind is exempted to cut encapsulating structure, it is characterised in that：It includes pin（4）And Ji Dao（3）, the pin（4）With single group
Or multigroup mode is arranged around Ji Dao（3）Around, the Ji Dao（3）Pass through bonding material or solder（5）It is provided with chip
（6）, the chip（6）Pass through metal wire（7）With pin（4）It is electrically connected with, the chip（6）, metal wire（7）, Ji Dao
（3）And pin（4）Periphery be coated with plastic packaging material（9）, the Ji Dao（3）With pin（4）Lower surface is exposed to plastic packaging material（9）
Outside, the plastic packaging material（9）Two parts above and below being divided into sideways, top is divided into sloping portion（10）, bottom is divided into vertical portion
（11）.
2. one kind is exempted to cut encapsulating structure, it is characterised in that：It includes pin（4）, the pin（4）Upper upside-down mounting has chip（6）,
The chip（6）And pin（4）Periphery be coated with plastic packaging material（9）, the pin（4）Lower surface is exposed to plastic packaging material（9）It
Outside, the plastic packaging material（9）Two parts above and below being divided into sideways, top is divided into sloping portion（10）, bottom is divided into vertical portion（11）.
3. a kind of manufacturing process for exempting to cut encapsulating structure, it is characterised in that the technique comprises the following steps：
Step 1: taking a support plate；
Step 2, pastes on support plate or prints one layer of bonding glue-line；
Step 3, plating Chu Ji islands and pin on bonding glue-line, the pin is arranged around institute with single group or multigroup mode
Around Shu Ji islands；
Step 4: Ji Dao upper surfaces coating bonding material or solder, carry out load and routing operation；
Step 5: carrying out plastic packaging material plastic packaging operation using mould, single product plastic-sealed body is disconnected from each other, and plastic packaging body side surface is divided into
Lower two parts, its middle and upper part is divided into sloping portion, and bottom is divided into vertical portion；
Step 6: removing the support plate and bonding glue-line at the product back side for completing plastic packaging operation, realization exempts to cut encapsulating structure monomer
Change.
4. a kind of manufacturing process for exempting to cut encapsulating structure, it is characterised in that the technique comprises the following steps：
Step 1: taking a support plate；
Step 2, pastes on support plate or prints one layer of bonding glue-line；
Step 3, pin is electroplated on bonding glue-line；
Step 4: carrying out flip-chip operation on pin；
Step 5: carrying out plastic packaging material plastic packaging operation using mould, single product plastic-sealed body is disconnected from each other, and plastic packaging body side surface is divided into
Lower two parts, its middle and upper part is divided into sloping portion, and bottom is divided into vertical portion；
Step 6: removing the support plate and bonding glue-line at the product back side for completing plastic packaging operation, realization exempts to cut encapsulating structure monomer
Change.
5. a kind of manufacturing process for exempting to cut encapsulating structure according to claim 3 or 4, it is characterised in that：The material of support plate
Matter is copper material, iron material or stainless steel.
6. a kind of manufacturing process for exempting to cut encapsulating structure according to claim 3 or 4, it is characterised in that：The plastic packaging
Material is using the epoxy resin for having packing material or no-arbitrary pricing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710391468.1A CN107146777A (en) | 2017-05-27 | 2017-05-27 | One kind exempts from cutting encapsulating structure and its manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710391468.1A CN107146777A (en) | 2017-05-27 | 2017-05-27 | One kind exempts from cutting encapsulating structure and its manufacturing process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107146777A true CN107146777A (en) | 2017-09-08 |
Family
ID=59779257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710391468.1A Pending CN107146777A (en) | 2017-05-27 | 2017-05-27 | One kind exempts from cutting encapsulating structure and its manufacturing process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107146777A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111162016A (en) * | 2019-12-27 | 2020-05-15 | 长电科技（宿迁）有限公司 | Packaging method for temporary bonding reinforcement of lead frame |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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