CN108109972A - There is semiconductor package and its manufacturing process that pin side wall climbs tin - Google Patents

There is semiconductor package and its manufacturing process that pin side wall climbs tin Download PDF

Info

Publication number
CN108109972A
CN108109972A CN201711467437.6A CN201711467437A CN108109972A CN 108109972 A CN108109972 A CN 108109972A CN 201711467437 A CN201711467437 A CN 201711467437A CN 108109972 A CN108109972 A CN 108109972A
Authority
CN
China
Prior art keywords
pin
support plate
dao
sidewall sections
metal support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711467437.6A
Other languages
Chinese (zh)
Other versions
CN108109972B (en
Inventor
王亚琴
梁志忠
刘恺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201711467437.6A priority Critical patent/CN108109972B/en
Publication of CN108109972A publication Critical patent/CN108109972A/en
Application granted granted Critical
Publication of CN108109972B publication Critical patent/CN108109972B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

The present invention relates to a kind of semiconductor packages and its manufacturing process for having the function of pin side wall and climbing tin, the structure includes Ji Dao and pin, the pin includes planar section and sidewall sections, the sidewall sections are located on the outside of planar section, it is connected smoothly between the planar section and sidewall sections by arch section, the arch section convex surface facing outer downside, base island front is provided with chip, the chip is electrically connected by metal wire and pin, the Ji Dao, pin and chip periphery region are encapsulated with plastic packaging material, the planar section, the outer surface of arch section and sidewall sections is exposed to outside plastic packaging material.The present invention is when welding PCB, scolding tin can be climbed along upright side walls to higher height, so as to increase the bonded area of scolding tin and pin, while the air at pin can be made to be discharged along evagination arc, so as to improve the welding performance of product, the reliability of welding and visual test welded condition.

Description

There is semiconductor package and its manufacturing process that pin side wall climbs tin
Technical field
The present invention relates to a kind of semiconductor packages and its manufacturing process for having the function of pin side wall and climbing tin, belong to half Conductor encapsulation technology field.
Background technology
With the development of modern science and technology, semiconductor packages is widely applied.It is in radar, remote-control romote-sensing, aviation boat The extensive application of it etc. proposes increasingly higher demands to its reliability.And it fails caused by semiconductor welding is bad and also gets over More cause the attention of people, it is irreversible because this failure is often fatal.Therefore, obtained in semicon industry One good soldering reliability is very important, and the tin layers in semiconductor welding face can so that welding is more secured, particularly Automotive electronics.
It is well known that QFN (Quad Flat No-lead Package, four sides are without pin flat package) and DFN (Duad Flat No-lead Package, bilateral is without pin flat package) it is leadless packages, there are one large area is naked for middle position The pad of dew has conductive force, and the conductive welding disk for realizing electrical connection is with outside the encapsulation of big pad.Usual thermal land With being mounted together with conductive welding disk on circuit boards, but exist in the prior art plastic-sealed body cutting after metal pins side because Wuxi bed boundary causes the tin cream on pcb board that can not climb up the metallic region of plastic packaging body side surface.And cause metal pins side empty The problem of weldering or cold welding, clearly can not inspect out in appearance, and the level-one in automotive electronics is especially applied to pacify Entirely on secondary safety, so the side metal pin of plastic-sealed body to climb tin particularly important.
To solve the problems, such as this, industry routine way is cut (referring to Figure 1A), shape to lead frame pin back side outer end Step into a ladder subsequently carries out cutting operation (referring to Figure 1B) again, and so can be obtained by has step in pin side Encapsulating structure (referring to Fig. 1 C), so as to improve its weld PCB when reliability.
But such pin has the hot weld disk in the exposed pads and conductive welding disk and PCB of the encapsulating structure bottom of step When being welded, as shown in A in Fig. 1 D, at pin step easily remaining air can not discharge, and cause scolding tin associativity not It is good.Particularly when product works, the air for remaining in place in step can be because product, which is heated, generates air expansion, and forms Tin layers cracking between PCB pads and plastic-sealed body pin, causes the electrical functionality loose contact of integrated circuit, can also be direct when serious Electrical functionality is caused to be stopped.
In addition, such pin have step encapsulating structure manufacturing process in, it is necessary to first to the lead frame pin back side outside End is cut, and is subsequently carried out cutting operation to the lead frame front for completing encapsulation again, is needed to carry out cutting twice operation, Cutting efficiency can be caused to reduce, also easily accelerate the consume of cutting tool, increase manufacturing cost.
It is that the groove of drops is formed to the outer end half-etching of the lead frame pin back side to also have other way in the industry(Referring to Fig. 1 E), due to etching characteristic, the groove formed by such method can be the circular arc of indent, the pin groove of such structure (referring to Fig. 1 F) can not be discharged by equally easily remaining air, cause scolding tin associativity bad.
In addition also have in the industry a kind of with L-shaped outer pin(See Fig. 1 G)Or J-shaped outer pin(See Fig. 1 H)Encapsulating structure, profit The lead frame encapsulated with traditional outer pin carries out load, routing, encapsulating operation, it is with certain length before processing procedure is punched Outer pin(See Fig. 1 I), it needs to stretch into molding die between outer pin and plastic-sealed body when being punched processing procedure, and by outer pin It is bent towards plastic packaging body side surface and the outer pin of L-shaped outer pin or C-shaped is made, such L-shaped outer pin or C-shaped outer pin envelope Dress can be such that scolding tin edge draws outside because its outer pin has comparable height, when the encapsulating structure is mounted on pcb board Foot because capillary phenomenon climbs to certain height, make its weld PCB when with higher weld strength.
However such encapsulating structure that L-shaped outer pin or C-shaped outer pin are formed by Trim Molding, draw being formed outside L-shaped When foot or C-shaped outer pin, as the same there is also following defects:First, when carrying out outer pin shaping outer pin towards plastic packaging body side surface Bent, under the influence of the interior pin in Fig. 1 G and Fig. 1 H at A can be because of the reaction force of metal, cause metal pins have by The stress that plastic-sealed body is downwardly and outwardly pushed aside, and in the case where this active force is downward, be easy to cause at A in pin upper surface and modeling Envelope material generates lamination between lower surface.It is resulted even under serious situation and forms open circuit at A between bonding wire and interior pin, So as to cause the failure of product;Secondly, this kind of L-shaped outer pin or C-shaped outer pin encapsulating structure are when carrying out outer pin shaping, outside It is to stretch into molding die to carry out bending and molding between outer pin and plastic-sealed body again that pin carries out bending towards plastic packaging body side surface, due to Metal pins have certain coefficient of elasticity, and outer pin can be caused to be stressed the relation that can be sprung back, and outer pin is caused to be formed such as Larger horn opening is formed at B in Fig. 1 J like that, and is hardly formed the shape as being vertically adjacent to plastic packaging body side surface in Fig. 1 G Shape;Finally, this kind of L-shaped outer pin or C-shaped outer pin encapsulating structure have larger volume, due to being to form outer pin bending L-shaped outer pin or C-shaped outer pin encapsulating structure, it is wide with wider packaging body from the point of view of traditional interior pin package Degree is unfavorable for the development trend of small-sized encapsulated body.
The content of the invention
The technical problems to be solved by the invention are to provide one kind for the above-mentioned prior art there is pin side wall to climb tin work( Can semiconductor package, arch section of the pin with evagination and be attached thereto with plastic packaging material with mutually level Sidewall sections, when welding PCB, scolding tin can be climbed along upright side walls part to higher height, so as to increase scolding tin and pin Bonded area, while climb tin state directly from appearance with regard to the state of welding can be clearly distinguished.In addition while tin is climbed The evagination arcuate structure of pin can be such that air at pin is discharged along evagination arc, can be to avoid remaining bubble in scolding tin So as to influence the combination of pin and PCB, so as to improve the welding performance of product, the reliability of welding and visual test welding shape State;The last present invention sets the copper sheet of one piece of thickening at the Ji Dao back sides, further meets the requirement of the high heat dissipation of power semiconductor.
A kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin of the present invention, utilizes and etches work Skill forms the groove with certain depth on support plate, then by electroplated metal layer in a groove, can be formed with upright side walls Pin, due to the upright side walls of its pin be plating formed rather than the outer pin of conventional frame is carried out Trim Molding and Into so the forming process of side wall will not spring back stress because of the metal of metal pins and cause dividing between pin and plastic packaging material Layer, and influence the reliability of product.In addition the present invention does not have to be cut so only needing removal support plate that can realize originally The plastic-sealed body singulation of array, fully saves the equipment cost in more cutting actions, production cost, material cost, Cost of labor and quality cost;The present invention to form the Ji Dao of thickening by electroplating twice, further meets power semiconductor The requirement of height heat dissipation.
A kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin of the present invention, utilizes and etches work Skill forms the groove with certain depth on support plate, and first the position of Ji Dao sets one to thicken copper sheet in a groove, then by Electroplated metal layer in groove can form the pin with upright side walls, since the upright side walls of its pin are that plating is formed, without It is that the outer pin of conventional frame is carried out Trim Molding to form, so the forming process of side wall will not be because of the metal of metal pins Rebound stress causes the layering between pin and plastic packaging material, and influences the reliability of product.In addition the present invention does not have to be cut So only needing removal support plate that can realize the plastic-sealed body singulation of script array, more cutting actions are fully saved In equipment cost, production cost, material cost, cost of labor and quality cost.
Technical solution is used by the present invention solves the above problems:A kind of semiconductor that there is pin side wall and climb tin Encapsulating structure, it includes Ji Dao and pin, and the pin is arranged at around Ji Dao, and base island front is provided with thickening layer, institute Shu Ji islands and thickening layer, which are formed, thickeies Ji Dao, and the height for thickening Ji Dao is higher than the height of pin, and the pin includes plane Part and sidewall sections, the sidewall sections are located on the outside of planar section, pass through arc between the planar section and sidewall sections Shape part is connected smoothly, the arch section convex surface facing outer downside, the thickening base island front is provided with chip, institute It states chip to be electrically connected by metal wire and pin, the pin, Ji Dao and chip periphery region are encapsulated with plastic packaging Material, the height of the sidewall sections are flushed with plastic packaging material, the inner surface cladding of the planar section, arch section and sidewall sections Within plastic packaging material, the outer surface of the planar section, arch section and sidewall sections is both exposed to outside plastic packaging material.
A kind of semiconductor package for having the function of pin side wall and climbing tin, it includes copper sheet, pin and Ji Dao, the copper Piece surface is provided with Ji Dao, and the pin is arranged at around copper sheet, and the pin includes planar section and sidewall sections, the side Wall part is located on the outside of planar section, is connected smoothly between the planar section and sidewall sections by arch section, institute State arch section convex surface facing outer downside, base island front is provided with chip, and the chip passes through metal wire and pin It is electrically connected, the pin, Ji Dao and chip periphery region are encapsulated with plastic packaging material, the height of the sidewall sections and modeling Envelope material flushes, and the inner surface of the planar section, arch section and sidewall sections is coated within plastic packaging material, the planar portions Point, the outer surface of arch section and sidewall sections is both exposed to outside plastic packaging material.
The pin and Ji Dao are the metallic circuit layer that plating is formed.
A kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin, the technique include following step Suddenly:
Step 1: take piece of metal support plate;
Step 2: pasted in metal support plate front and the back side or print the photoresist that can be exposed development, it is aobvious using exposure Shadow equipment is exposed the photoresist on metal support plate surface, develops and removal part photoresist, to expose metal support plate Surface needs to be etched graphics field;
Step 3: the region that exposure imaging is completed in metal support plate front carries out chemical etching, etching forms groove, bottom portion of groove It is plane with side wall, bottom and side wall junction is etched to arc, the photoresistance film on removal metal support plate surface after the completion of etching;
Step 4, the metallic circuit layer in plating in the groove of metal support plate front, forms Ji Dao and pin, and pin includes planar portions Point and sidewall sections, sidewall sections be located at planar section outside, it is smooth by arch section between planar section and sidewall sections Transition connect, the arch section convex surface facing outer downside, the height of sidewall sections is flushed with groove top surface;
Step 5 on the groove Nei Ji islands of metal support plate front electroplates metallic circuit layer, is formed and thicken Ji Dao again;
Step 6: thickening Ji Dao surfaces coating bonding material or solder, chip then is implanted on bonding material or solder, Bond wire line operation is carried out between chip front side and pin front;
Step 7: the metal support plate that step 6 is completed to load and routing operation carries out plastic packaging using plastic packaging material;
Step 8: removal metal support plate, exposes pin and thickeies the outer surface of Ji Dao, and can make the plastic-sealed body of script array It is independent, a kind of semiconductor package that there is pin side and climb tin is made.
A kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin, the technique include following step Suddenly:
Step 1: take piece of metal support plate;
Step 2: pasted in metal support plate front and the back side or print the photoresist that can be exposed development, it is aobvious using exposure Shadow equipment is exposed the photoresist on metal support plate surface, develops and removal part photoresist, to expose metal support plate Surface needs to be etched graphics field;
Step 3: the region that exposure imaging is completed in metal support plate front carries out chemical etching, etching forms groove, bottom portion of groove It is plane with side wall, bottom and side wall junction is etched to arc, the photoresistance film on removal metal support plate surface after the completion of etching;
Step 4, the position that Ji Dao is subsequently electroplated in the groove of metal support plate front set a copper sheet;
Step 5, the copper sheet in the groove of metal support plate front, which powers on, plates metal line layer, forms Ji Dao, in metal support plate just The upper metallic circuit layer of peripheral part plating of copper sheet, forms pin, pin includes planar section and sidewall sections, side in the groove of face Wall part is located on the outside of planar section, is connected smoothly between planar section and sidewall sections by arch section, the arc Shape part convex surface facing outer downside, the height of sidewall sections is flushed with groove top surface;
Step 6: coating bonding material or solder on Ji Dao surfaces, chip then is implanted on bonding material or solder, in chip Bond wire bonding wire operation is carried out between front and pin front;
Step 7: the metal support plate that step 6 is completed to load and routing operation carries out plastic packaging using plastic packaging material;
Step 8: removal metal support plate, exposes the outer surface of pin and copper sheet, and the plastic-sealed body of script array can be made independent It comes, a kind of semiconductor package that there is pin side and climb tin is made.
Etching solution is using copper chloride either iron chloride.
Removal photoresistance film uses the method that chemical medicinal liquid softens and uses high pressure water washing.
Metallic circuit layer material is copper, aluminium or nickel.
The material of metal wire uses gold, silver, copper or aluminium;The shape of metal wire is Filamentous or banding.
The encapsulating mode of plastic packaging material uses mold encapsulating mode, spraying equipment spraying method or brush coating mode, the plastic packaging Material is using the epoxy resin for having packing material or non-filling substance.
Compared with prior art, the advantage of the invention is that:
1st, a kind of semiconductor package and its manufacturing process for having the function of pin side wall and climbing tin of the invention loses in support plate It carves to electroplate in the groove formed and directly forms the arch section with evagination and be attached thereto with plastic packaging material with identical height Sidewall sections pin, when welding PCB, scolding tin can be climbed along upright side walls to higher height, so as to increase scolding tin with The bonded area of pin is climbed tin state and directly just can clearly be found out from appearance, in addition while tin is climbed pin evagination Arcuate structure can be such that the air at pin is discharged along evagination arc, so as to avoid remaining bubble in scolding tin so as to shadow Pin and the combination of PCB are rung, the welding performance of product and the reliability of welding can be improved;
2nd, a kind of semiconductor package and its manufacturing process for having the function of pin side wall and climbing tin of the invention, pin erect Straight sidewall is that plating forms rather than the outer pin progress Trim Molding of conventional frame is formed, and the forming process of side wall is not It can cause the layering between pin and plastic packaging material, so as to influence the reliability of product;
3rd, a kind of semiconductor package and its manufacturing process that there is pin side wall and climb tin of the invention, by twice Plating, which is formed below the Ji Dao Huo Ji islands thickeied, sets a copper sheet thickeied, further meets the high heat dissipation of power semiconductor It is required that;
4th, a kind of semiconductor package and its manufacturing process for having the function of pin side wall and climbing tin of the invention does not have to carry out Cutting is cut into so it can be saved so the plastic-sealed body singulation of script array can be realized by only needing to remove support plate This.
Description of the drawings
Figure 1A -1B are the cutting twice operation schematic diagram for the encapsulating structure that existing manufacture pin has step.
Fig. 1 C are the schematic diagram for the encapsulating structure that existing pin has step.
Fig. 1 D are the schematic diagram that there is existing pin the encapsulating structure of step to be combined with pcb board.
Fig. 1 E are the schematic diagram for the encapsulating structure that existing pin has drops groove.
Fig. 1 F are the schematic diagram that there is existing pin the encapsulating structure of drops groove to be combined with pcb board.
Fig. 1 G are the schematic diagram of the existing encapsulating structure with L-shaped outer pin.
Fig. 1 H are the schematic diagram of the existing encapsulating structure with C-shaped outer pin.
Fig. 1 I are structure of the existing encapsulating structure with L-shaped outer pin or C-shaped outer pin before Trim Molding is carried out Schematic diagram.
Fig. 1 J are structure diagram of the existing encapsulating structure with L-shaped outer pin after Trim Molding.
Fig. 2 is a kind of schematic diagram for having the function of pin side wall and climbing the semiconductor package embodiment 1 of tin of the present invention.
Fig. 3 is a kind of three-dimensional signal for having the function of pin side wall and climbing the semiconductor package embodiment 1 of tin of the present invention Figure.
Fig. 4, which is that the present invention is a kind of, has the function of that pin side wall is climbed the semiconductor package embodiment 1 of tin and combined with pcb board Schematic diagram.
Fig. 5 ~ Figure 15 has the function of that pin side wall climbs the manufacturing process of the semiconductor package of tin for the present invention is a kind of Flow diagram.
Figure 16 is a kind of schematic diagram for having the function of pin side wall and climbing the semiconductor package embodiment 2 of tin of the present invention.
Figure 17 is a kind of three-dimensional signal for having the function of pin side wall and climbing the semiconductor package embodiment 2 of tin of the present invention Figure.
Figure 18, which is that the present invention is a kind of, has the function of that pin side wall climbs the semiconductor package embodiment 2 of tin and pcb board knot The schematic diagram of conjunction.
Figure 19 ~ Figure 29 has the function of that pin side wall climbs the manufacturing process of the semiconductor package of tin for the present invention is a kind of Flow diagram.
Wherein:
Base island 1
Pin 2
Planar section 2.1
Arch section 2.2
Sidewall sections 2.3
Thickening layer 3
Bonding material or solder 4
Chip 5
Metal wire 6
Plastic packaging material 7
Copper sheet 8.
Specific embodiment
The present invention is described in further detail below in conjunction with attached drawing embodiment.
Embodiment 1:Plating twice, which is formed, thickeies Ji Dao
As shown in Figure 2 and Figure 3, a kind of semiconductor package for having the function of pin side wall and climbing tin in the present embodiment, it includes The metallic circuit layer that base island 1 and pin 2, the pin 2 and base island 3 are formed for plating, the pin 2 are arranged at around base island 3, 1 front of base island is provided with thickening layer 3, and the base island 1 and thickening layer 3, which are formed, thickeies Ji Dao, the height for thickening Ji Dao Higher than the height of pin 2, the pin 2 includes planar section 2.1 and sidewall sections 2.3, and the sidewall sections 2.3 are located at plane 2.1 outside of part, is connected smoothly between the planar section 2.1 and sidewall sections 2.3 by arch section 2.2, described Arch section 2.2 convex surface facing outer downside, the thickening base island front is provided with chip 5, institute by bonding material or solder 4 It states chip 5 to be electrically connected by metal wire 6 and pin 2, the pin 2, base island 3 and the encapsulating of 5 peripheral region of chip There is plastic packaging material 7, the height of the sidewall sections 2.3 is flushed with plastic packaging material 7, the planar section 2.1, arch section 2.2 and side The inner surface of wall part 2.3 is coated within plastic packaging material 7, the planar section 2.1, arch section 2.2 and sidewall sections 2.3 Outer surface is both exposed to outside plastic packaging material 7;
Fig. 4 has the function of that pin side wall climbs the schematic diagram that the semiconductor package of tin and pcb board are combined for the present invention is a kind of, this Invention electroplated in support plate etches the groove to be formed directly formed arc with evagination and be attached thereto with plastic packaging material with The pin of identical height side wall, when welding PCB, scolding tin can be climbed along upright side walls to higher height, so as to increase scolding tin With the bonded area of pin, climb tin state and directly just can clearly find out from appearance, in addition while tin is climbed pin it is outer Convex structure can be such that air at pin is discharged along evagination arc, so as to avoid remaining in scolding tin bubble so as to Pin and the combination of PCB are influenced, the welding performance of product and the reliability of welding can be improved.
A kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin, the technique include following step Suddenly:
Step 1: referring to Fig. 5, the suitable metal support plate of a piece of thickness is taken, the purpose that this plate uses is for circuit making and line Road layer structure provides support, and the material of this plate is mainly based on metal material, and the material of metal material can be copper material, iron Material, stainless steel or other metallicses with conducting function;
Step 2: referring to Fig. 6, pasted in metal support plate front and the back side or print the photoresist that can be exposed development, with Protect subsequent etch metal layer process operation.Photoresist can be photoresistance film or photoresist.Referring to Fig. 7, exposure is utilized Photodevelopment equipment is exposed the photoresist on metal support plate surface, develops and removal part photoresist, to expose metal Support plate surface needs to be etched graphics field;
Step 3: referring to Fig. 8, the region that exposure imaging is completed in metal support plate front carries out chemical etching, and etching forms groove, Bottom portion of groove and side wall are plane, and due to etching characteristic, bottom and side wall junction can be etched to arc.Etching solution can be adopted With copper chloride either iron chloride or other liquid medicine that can carry out chemical etching.Referring to Fig. 9, removal metal after the completion of etching The photoresistance film on support plate surface, the method for removing photoresistance film may be employed chemical medicinal liquid and soften and the method for high pressure water washing is used to go Except photoresistance film;
Step 4, referring to Figure 10, metallic circuit layer in plating, forms Ji Dao and pin, pin in the groove of metal support plate front Including planar section and sidewall sections, sidewall sections are located on the outside of planar section, pass through arc between planar section and sidewall sections Shape part is connected smoothly, the arch section convex surface facing outer downside, the height of sidewall sections is flushed with groove top surface, Metallic circuit layer material is typically copper, aluminium, nickel etc. or other conducting metal substances;
Step 5 referring to Figure 11, on the groove Nei Ji islands of metal support plate front electroplates metallic circuit layer, is formed and thickeied again Ji Dao, metallic circuit layer material are typically copper, aluminium, nickel etc. or other conducting metal substances;
Step 6: referring to Figure 12, Ji Dao surfaces coating bonding material or solder are being thickeied, is then being planted on bonding material or solder Enter chip.The progress bond wire bonding wire operation between chip front side and pin front, the material use gold of the metal wire, Silver, copper, the material of aluminium or alloy, the shape of metal wire can be that filiform can also be banding;
Step 7: referring to Figure 13, the metal support plate that step 6 is completed to load and routing operation carries out plastic packaging, modeling using plastic packaging material The encapsulating mode of envelope material may be employed mold encapsulating mode, spraying equipment spraying method or brush coating mode, and the plastic packaging material can be with Using the epoxy resin for having packing material or non-filling substance;
Step 8: referring to Figure 14, Figure 15, metal support plate is removed, expose pin and thickeies the outer surface of Ji Dao, and can be made originally The plastic-sealed body of array is independent, and a kind of semiconductor package for having the function of pin side and climbing tin is made.
The present invention provides a kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin, utilizes etching Technique forms the groove with certain depth on support plate, then by electroplated metal layer in a groove, can be formed with vertical side The pin of wall is plating formation due to the upright side walls of its pin rather than the outer pin of conventional frame is carried out Trim Molding It forms, the forming process of side wall will not cause the layering between pin and plastic packaging material, so as to influence the reliability of product.In addition The present invention does not have to be cut so the plastic-sealed body singulation of script array can be realized by only needing to remove support plate, so its Cutting cost can be saved.
Embodiment 2:Copper sheet is set under chip
As shown in Figure 16, Figure 17, a kind of semiconductor package for having the function of pin side wall and climbing tin in the present embodiment, it is wrapped Copper sheet 8, pin 2, base island 1 are included, 8 surface of copper sheet is provided with the metal that base island 1, the pin 2 and base island 1 are formed for plating Line layer, the pin 2 are arranged at around copper sheet 8, and the pin 2 includes planar section 2.1 and sidewall sections 2.3, the side Wall part 2.3 is located at 2.1 outside of planar section, passes through arch section 2.2 between the planar section 2.1 and sidewall sections 2.3 Be connected smoothly, the arch section 2.2 convex surface facing outer downside, 1 front of base island passes through bonding material or solder 4 Chip 5 is provided with, the chip 5 is electrically connected by metal wire 6 and pin 2, the pin 2, base island 1 and chip 5 peripheral region are encapsulated with plastic packaging material 7, and the height of the sidewall sections 2.3 is flushed with plastic packaging material 7, the planar section 2.1, arc The inner surface of shape part 2.2 and sidewall sections 2.3 is coated within plastic packaging material 7, the planar section 2.1,2.2 and of arch section The outer surface of sidewall sections 2.3 is both exposed to outside plastic packaging material 7;
Figure 18 has the function of that pin side wall climbs the schematic diagram that the semiconductor package of tin and pcb board are combined for the present invention is a kind of, The present invention electroplates directly to form the arc with evagination and be attached thereto in support plate etches the groove to be formed to be had with plastic packaging material There is the pin of identical height side wall, scolding tin can be climbed along upright side walls to higher height when welding PCB, so as to increase weldering The bonded area of tin and pin is climbed tin state and directly just can clearly be found out from appearance, in addition pin while tin is climbed Evagination arcuate structure can be such that air at pin is discharged along evagination arc, so as to avoid remaining in scolding tin bubble from And pin and the combination of PCB are influenced, the welding performance of product and the reliability of welding can be improved.
A kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin, the technique include following step Suddenly:
Step 1: referring to Figure 19, the suitable metal support plate of a piece of thickness is taken, the purpose that this plate uses is for circuit making and line Road layer structure provides support, and the material of this plate is mainly based on metal material, and the material of metal material can be copper material, iron Material, stainless steel or other metallicses with conducting function;
Step 2: referring to Figure 20, pasted in metal support plate front and the back side or print the photoresist that can be exposed development, with Protect subsequent etch metal layer process operation.Photoresist can be photoresistance film or photoresist.Referring to Figure 21, utilize Exposure imaging equipment is exposed the photoresist on metal support plate surface, develops and removal part photoresist, to expose gold Belonging to support plate surface needs to be etched graphics field;
Step 3: referring to Figure 22, the region that exposure imaging is completed in metal support plate front carries out chemical etching, and etching forms recessed Slot, bottom portion of groove and side wall are plane, and due to etching characteristic, bottom and side wall junction can be etched to arc.Etching solution can With using copper chloride either iron chloride or other liquid medicine that can carry out chemical etching.Referring to Figure 23, gone after the completion of etching Except the photoresistance film on metal support plate surface, the method for removing photoresistance film may be employed chemical medicinal liquid and soften and use high pressure water washing Method removes photoresistance film;
Step 4, referring to Figure 24, the position that Ji Dao is subsequently electroplated in the groove of metal support plate front sets a copper sheet;
Step 5, referring to Figure 25, the copper sheet in the groove of metal support plate front, which powers on, plates metal line layer, forms Ji Dao, The upper metallic circuit layer of peripheral part plating of copper sheet in the groove of metal support plate front, forms pin, pin include planar section and Sidewall sections, sidewall sections are located on the outside of planar section, are seamlessly transitted between planar section and sidewall sections by arch section Connection, the arch section convex surface facing outer downside, the height of sidewall sections is flushed with groove top surface, metallic circuit layer material Typically copper, aluminium, nickel etc. or other conducting metal substances;
Step 6: referring to Figure 26, bonding material or solder are coated on Ji Dao surfaces, is then implanted into core on bonding material or solder Piece.Carry out bond wire bonding wire operation between chip front side and pin front, the material of the metal wire using gold, silver, The material of copper, aluminium or alloy, the shape of metal wire can be that filiform can also be banding;
Step 7: referring to Figure 27, the metal support plate that step 6 is completed to load and routing operation carries out plastic packaging, modeling using plastic packaging material The encapsulating mode of envelope material may be employed mold encapsulating mode, spraying equipment spraying method or brush coating mode, and the plastic packaging material can be with Using the epoxy resin for having packing material or non-filling substance;
Step 8: referring to Figure 28, Figure 29, metal support plate is removed, exposes the outer surface of pin and copper sheet, and script array can be made The plastic-sealed body of formula is independent, and a kind of semiconductor package for having the function of pin side and climbing tin is made.
The present invention provides a kind of manufacturing process for having the function of pin side wall and climbing the semiconductor package of tin, utilizes etching Technique forms the groove with certain depth on support plate, and first the position of Ji Dao sets one to thicken copper sheet in a groove, then passes through Electroplated metal layer in a groove can form the pin with upright side walls, since the upright side walls of its pin are that plating is formed, and That the outer pin of conventional frame is carried out Trim Molding to form, the forming process of side wall will not cause pin and plastic packaging material it Between layering, so as to influence the reliability of product.In addition the present invention does not have to be cut so only needing to remove support plate The plastic-sealed body singulation of script array is realized, so it can save cutting cost.
In addition to the implementation, it is all to use equivalent transformation or equivalent replacement present invention additionally comprises there is an other embodiment The technical solution that mode is formed should all be fallen within the scope of the hereto appended claims.

Claims (10)

1. a kind of semiconductor package that there is pin side wall and climb tin, it is characterised in that:It includes Ji Dao(1)And pin (2), the pin(2)It is arranged at Ji Dao(1)Around, the Ji Dao(1)Front is provided with thickening layer(3), the Ji Dao(1)With Thickening layer(3)It is formed and thickeies Ji Dao, the height for thickening Ji Dao is higher than pin(2)Height, the pin(2)Including plane Part(2.1)And sidewall sections(2.3), the sidewall sections(2.3)Positioned at planar section(2.1)Outside, the planar section (2.1)And sidewall sections(2.3)Between pass through arch section(2.2)It is connected smoothly, the arch section(2.2)Convex surface Towards outer downside, the thickening base island front is provided with chip(5), the chip(5)Pass through metal wire(6)With pin(2) It is electrically connected, the pin(2), Ji Dao(1)And chip(5)Peripheral region is encapsulated with plastic packaging material(7), the side of sidewall portion Point(2.3)Height and plastic packaging material(7)It flushes, the planar section(2.1), arch section(2.2)And sidewall sections(2.3)'s Inner surface is coated on plastic packaging material(7)Within, the planar section(2.1), arch section(2.2)And sidewall sections(2.3)It is outer Surface is both exposed to plastic packaging material(7)Outside.
2. a kind of semiconductor package that there is pin side wall and climb tin, it is characterised in that:It includes copper sheet(8), pin (2)And Ji Dao(1), the copper sheet(1)Surface is provided with Ji Dao(1), the pin(2)It is arranged at copper sheet(8)Around, it is described to draw Foot(2)Including planar section(2.1)And sidewall sections(2.3), the sidewall sections(2.3)Positioned at planar section(2.1)Outside, The planar section(2.1)And sidewall sections(2.3)Between pass through arch section(2.2)It is connected smoothly, the curved portion Point(2.2)Convex surface facing outer downside, the Ji Dao(1)Front is provided with chip(5), the chip(5)Pass through metal wire (6)With pin(2)It is electrically connected, the pin(2), Ji Dao(3)And chip(5)Peripheral region is encapsulated with plastic packaging material (7), the sidewall sections(2.3)Height and plastic packaging material(7)It flushes, the planar section(2.1), arch section(2.2)With Sidewall sections(2.3)Inner surface be coated on plastic packaging material(7)Within, the planar section(2.1), arch section(2.2)And side Wall part(2.3)Outer surface be both exposed to plastic packaging material(7)Outside.
3. a kind of semiconductor package for having the function of pin side wall and climbing tin according to claim 1 or 2, feature exist In:The pin(2)And Ji Dao(1)The metallic circuit layer formed for plating.
A kind of 4. manufacturing process that there is pin side wall and climb the semiconductor package of tin, it is characterised in that the technique bag Include following steps:
Step 1: take piece of metal support plate;
Step 2: pasted in metal support plate front and the back side or print the photoresist that can be exposed development, it is aobvious using exposure Shadow equipment is exposed the photoresist on metal support plate surface, develops and removal part photoresist, to expose metal support plate Surface needs to be etched graphics field;
Step 3: the region that exposure imaging is completed in metal support plate front carries out chemical etching, etching forms groove, bottom portion of groove It is plane with side wall, bottom and side wall junction is etched to arc, the photoresistance film on removal metal support plate surface after the completion of etching;
Step 4, the metallic circuit layer in plating in the groove of metal support plate front, forms Ji Dao and pin, and pin includes planar portions Point and sidewall sections, sidewall sections be located at planar section outside, it is smooth by arch section between planar section and sidewall sections Transition connect, the arch section convex surface facing outer downside, the height of sidewall sections is flushed with groove top surface;
Step 5 on the groove Nei Ji islands of metal support plate front electroplates metallic circuit layer, is formed and thicken Ji Dao again;
Step 6: thickening Ji Dao surfaces coating bonding material or solder, chip then is implanted on bonding material or solder, Bond wire bonding wire operation is carried out between chip front side and pin front;
Step 7: the metal support plate that step 6 is completed to load and routing operation carries out plastic packaging using plastic packaging material;
Step 8: removal metal support plate, exposes pin and thickeies the outer surface of Ji Dao, and can make the plastic-sealed body of script array It is independent, a kind of semiconductor package that there is pin side and climb tin is made.
A kind of 5. manufacturing process that there is pin side wall and climb the semiconductor package of tin, it is characterised in that the technique bag Include following steps:
Step 1: take piece of metal support plate;
Step 2: pasted in metal support plate front and the back side or print the photoresist that can be exposed development, it is aobvious using exposure Shadow equipment is exposed the photoresist on metal support plate surface, develops and removal part photoresist, to expose metal support plate Surface needs to be etched graphics field;
Step 3: the region that exposure imaging is completed in metal support plate front carries out chemical etching, etching forms groove, bottom portion of groove It is plane with side wall, bottom and side wall junction is etched to arc, the photoresistance film on removal metal support plate surface after the completion of etching;
Step 4, the position that Ji Dao is subsequently electroplated in the groove of metal support plate front set a copper sheet;
Step 5, the copper sheet in the groove of metal support plate front, which powers on, plates metal line layer, forms Ji Dao, in metal support plate just The upper metallic circuit layer of peripheral part plating of copper sheet, forms pin, pin includes planar section and sidewall sections, side in the groove of face Wall part is located on the outside of planar section, is connected smoothly between planar section and sidewall sections by arch section, the arc Shape part convex surface facing outer downside, the height of sidewall sections is flushed with groove top surface;
Step 6: coating bonding material or solder on Ji Dao surfaces, chip then is implanted on bonding material or solder, in chip Bond wire bonding wire operation is carried out between front and pin front;
Step 7: the metal support plate that step 6 is completed to load and routing operation carries out plastic packaging using plastic packaging material;
Step 8: removal metal support plate, exposes the outer surface of pin and copper sheet, and the plastic-sealed body of script array can be made independent It comes, a kind of semiconductor package that there is pin side and climb tin is made.
6. a kind of manufacture work that there is pin side wall and climb the semiconductor package of tin according to claim 4 or 5 Skill, it is characterised in that:Etching solution is using copper chloride either iron chloride.
7. a kind of manufacture work that there is pin side wall and climb the semiconductor package of tin according to claim 4 or 5 Skill, it is characterised in that:Removal photoresistance film uses the method that chemical medicinal liquid softens and uses high pressure water washing.
8. a kind of manufacture work that there is pin side wall and climb the semiconductor package of tin according to claim 4 or 5 Skill, it is characterised in that:Metallic circuit layer material is copper, aluminium or nickel.
9. a kind of manufacture work that there is pin side wall and climb the semiconductor package of tin according to claim 4 or 5 Skill, it is characterised in that:The material of metal wire uses gold, silver, copper or aluminium;The shape of metal wire is Filamentous or banding.
10. a kind of manufacture work that there is pin side wall and climb the semiconductor package of tin according to claim 4 or 5 Skill, it is characterised in that:The encapsulating mode of plastic packaging material uses mold encapsulating mode, spraying equipment spraying method or brush coating mode, institute Plastic packaging material is stated using the epoxy resin for having packing material or non-filling substance.
CN201711467437.6A 2017-12-29 2017-12-29 Semiconductor packaging structure with pin side wall tin climbing function and manufacturing process thereof Active CN108109972B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711467437.6A CN108109972B (en) 2017-12-29 2017-12-29 Semiconductor packaging structure with pin side wall tin climbing function and manufacturing process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711467437.6A CN108109972B (en) 2017-12-29 2017-12-29 Semiconductor packaging structure with pin side wall tin climbing function and manufacturing process thereof

Publications (2)

Publication Number Publication Date
CN108109972A true CN108109972A (en) 2018-06-01
CN108109972B CN108109972B (en) 2020-03-06

Family

ID=62214458

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711467437.6A Active CN108109972B (en) 2017-12-29 2017-12-29 Semiconductor packaging structure with pin side wall tin climbing function and manufacturing process thereof

Country Status (1)

Country Link
CN (1) CN108109972B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108695172A (en) * 2018-07-13 2018-10-23 江苏长电科技股份有限公司 Monomer bimetallic plates encapsulating structure and its packaging method
CN108899286A (en) * 2018-07-13 2018-11-27 江苏长电科技股份有限公司 Monomer bimetallic plates encapsulating structure and its packaging method
CN109037183A (en) * 2018-06-13 2018-12-18 南通通富微电子有限公司 A kind of semiconductor chip packaging array and semiconductor chip packaging device
CN109037077A (en) * 2018-06-13 2018-12-18 南通通富微电子有限公司 A kind of semiconductor chip packaging method
CN109065519A (en) * 2018-06-13 2018-12-21 南通通富微电子有限公司 A kind of semiconductor chip packaging device
CN109065518A (en) * 2018-06-13 2018-12-21 南通通富微电子有限公司 A kind of semiconductor chip packaging array
CN115719713A (en) * 2023-01-09 2023-02-28 江苏长晶浦联功率半导体有限公司 Flat pin-free element and packaging method thereof

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005209999A (en) * 2004-01-26 2005-08-04 Ricoh Co Ltd Semiconductor device and lead frame, and method for manufacturing semiconductor device
CN101512762A (en) * 2006-08-28 2009-08-19 爱特梅尔公司 Stackable packages for three-dimensional packaging of semiconductor dice
JP2010192847A (en) * 2009-02-20 2010-09-02 Yamaha Corp Lead frame and method of manufacturing semiconductor package using the same
CN102842515A (en) * 2011-06-23 2012-12-26 飞思卡尔半导体公司 Method for assembling semiconductor device
CN103474406A (en) * 2013-09-27 2013-12-25 华天科技(西安)有限公司 Copper-free flat packaging piece of AAQFN frame product and manufacturing process thereof
CN105206596A (en) * 2014-06-06 2015-12-30 飞思卡尔半导体公司 Packaging integration circuit device possessing bending lead wire
CN105405823A (en) * 2014-08-20 2016-03-16 飞思卡尔半导体公司 Semiconductor device with inspectable solder joints
CN105895610A (en) * 2014-11-18 2016-08-24 飞思卡尔半导体公司 Semiconductor device and lead frame with vertical connection strips
CN106169443A (en) * 2015-05-18 2016-11-30 东和株式会社 Semiconductor device and manufacture method thereof
CN106783792A (en) * 2017-03-22 2017-05-31 江苏长电科技股份有限公司 There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance
US20170263538A1 (en) * 2016-03-09 2017-09-14 Freescale Semiconductor, Inc. Packaged semiconductor device having bent leads and method for forming
CN107170716A (en) * 2016-03-08 2017-09-15 株式会社吉帝伟士 The manufacture method of semiconductor package part and semiconductor package part

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005209999A (en) * 2004-01-26 2005-08-04 Ricoh Co Ltd Semiconductor device and lead frame, and method for manufacturing semiconductor device
CN101512762A (en) * 2006-08-28 2009-08-19 爱特梅尔公司 Stackable packages for three-dimensional packaging of semiconductor dice
JP2010192847A (en) * 2009-02-20 2010-09-02 Yamaha Corp Lead frame and method of manufacturing semiconductor package using the same
CN102842515A (en) * 2011-06-23 2012-12-26 飞思卡尔半导体公司 Method for assembling semiconductor device
CN103474406A (en) * 2013-09-27 2013-12-25 华天科技(西安)有限公司 Copper-free flat packaging piece of AAQFN frame product and manufacturing process thereof
CN105206596A (en) * 2014-06-06 2015-12-30 飞思卡尔半导体公司 Packaging integration circuit device possessing bending lead wire
CN105405823A (en) * 2014-08-20 2016-03-16 飞思卡尔半导体公司 Semiconductor device with inspectable solder joints
CN105895610A (en) * 2014-11-18 2016-08-24 飞思卡尔半导体公司 Semiconductor device and lead frame with vertical connection strips
CN106169443A (en) * 2015-05-18 2016-11-30 东和株式会社 Semiconductor device and manufacture method thereof
CN107170716A (en) * 2016-03-08 2017-09-15 株式会社吉帝伟士 The manufacture method of semiconductor package part and semiconductor package part
US20170263538A1 (en) * 2016-03-09 2017-09-14 Freescale Semiconductor, Inc. Packaged semiconductor device having bent leads and method for forming
CN106783792A (en) * 2017-03-22 2017-05-31 江苏长电科技股份有限公司 There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037183A (en) * 2018-06-13 2018-12-18 南通通富微电子有限公司 A kind of semiconductor chip packaging array and semiconductor chip packaging device
CN109037077A (en) * 2018-06-13 2018-12-18 南通通富微电子有限公司 A kind of semiconductor chip packaging method
CN109065519A (en) * 2018-06-13 2018-12-21 南通通富微电子有限公司 A kind of semiconductor chip packaging device
CN109065518A (en) * 2018-06-13 2018-12-21 南通通富微电子有限公司 A kind of semiconductor chip packaging array
CN109037077B (en) * 2018-06-13 2020-12-25 南通通富微电子有限公司 Semiconductor chip packaging method
CN109065519B (en) * 2018-06-13 2020-12-25 南通通富微电子有限公司 Semiconductor chip packaging device
CN108695172A (en) * 2018-07-13 2018-10-23 江苏长电科技股份有限公司 Monomer bimetallic plates encapsulating structure and its packaging method
CN108899286A (en) * 2018-07-13 2018-11-27 江苏长电科技股份有限公司 Monomer bimetallic plates encapsulating structure and its packaging method
CN115719713A (en) * 2023-01-09 2023-02-28 江苏长晶浦联功率半导体有限公司 Flat pin-free element and packaging method thereof

Also Published As

Publication number Publication date
CN108109972B (en) 2020-03-06

Similar Documents

Publication Publication Date Title
CN108109972A (en) There is semiconductor package and its manufacturing process that pin side wall climbs tin
JP5959386B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
CN106783792A (en) There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance
JP2014007363A (en) Method of manufacturing semiconductor device and semiconductor device
US8309401B2 (en) Method of manufacturing non-leaded package structure
CN108206170A (en) There is semiconductor package and its manufacturing process that pin side wall climbs tin
TWI634634B (en) Semiconductor device and method of manufacturing the same
CN108198790A (en) There is stack package structure and its manufacturing process that pin side wall climbs tin
US9659842B2 (en) Methods of fabricating QFN semiconductor package and metal plate
CN108198761A (en) There is semiconductor package and its manufacturing process that pin side wall climbs tin
CN206595254U (en) There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance
US10217699B2 (en) Preformed lead frame
CN108198804A (en) There is stack package structure and its manufacturing process that pin side wall climbs tin
CN109037077A (en) A kind of semiconductor chip packaging method
CN109065519A (en) A kind of semiconductor chip packaging device
CN207834273U (en) The stack package structure of tin function is climbed with pin side wall
CN108198797A (en) There is semiconductor package and its manufacturing process that pin side wall climbs tin
CN207834288U (en) The semiconductor package of tin function is climbed with pin side wall
CN207834289U (en) The semiconductor package of tin function is climbed with pin side wall
CN207834287U (en) The stack package structure of tin function is climbed with pin side wall
CN105206594B (en) One side etches water droplet bump package structure and its process
CN109065518A (en) A kind of semiconductor chip packaging array
CN207834292U (en) The stack package structure of tin function is climbed with pin side wall
JP4400492B2 (en) Electronic equipment
US20210098358A1 (en) Semiconductor package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant