CN108109972B - Semiconductor packaging structure with pin side wall tin climbing function and manufacturing process thereof - Google Patents
Semiconductor packaging structure with pin side wall tin climbing function and manufacturing process thereof Download PDFInfo
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- CN108109972B CN108109972B CN201711467437.6A CN201711467437A CN108109972B CN 108109972 B CN108109972 B CN 108109972B CN 201711467437 A CN201711467437 A CN 201711467437A CN 108109972 B CN108109972 B CN 108109972B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a semiconductor packaging structure with a pin side wall tin-climbing function and a manufacturing process thereof, the structure comprises a base island and a pin, the pin comprises a plane part and a side wall part, the side wall part is positioned outside the plane part, the plane part and the side wall part are in smooth transition connection through an arc part, the convex surface of the arc part faces the outer lower side, a chip is arranged on the front surface of the base island, the chip is electrically connected with the pin through a metal welding wire, a plastic packaging material is packaged in the peripheral area of the base island, the pin and the chip, and the outer surfaces of the plane part, the arc part and the side wall part are exposed outside the plastic packaging material. When the PCB is welded, the soldering tin can climb to a higher height along the vertical side wall, so that the combination area of the soldering tin and the pins is increased, and meanwhile, air at the pins can be discharged along the convex arc, so that the welding performance and the welding reliability of a product are improved, and the welding state is visually checked.
Description
Technical Field
The invention relates to a semiconductor packaging structure with a pin side wall tin-climbing function and a manufacturing process thereof, belonging to the technical field of semiconductor packaging.
Background
With the development of modern technologies, semiconductor packages are widely used. The high-reliability radar antenna has higher and higher requirements on the reliability in a large number of applications such as radar, remote control and remote measurement, aerospace and the like. Failure due to poor semiconductor bonding has also become increasingly important as it is often fatal and irreversible. It is therefore important in the semiconductor industry to achieve a good solder joint reliability, and the tin layer on the solder side of the semiconductor can make the solder joint more robust, especially in automotive electronics.
As is well known, QFN (Quad Flat Package) and DFN (dual Flat Package) are leadless packages, in which a large-area exposed bonding pad is disposed at the center of the Quad Flat Package, and has a thermal conductive function, and a conductive bonding pad for electrical connection is disposed at the periphery of the large-area exposed bonding pad. Usually, the heat conducting bonding pad and the electric conducting bonding pad are attached to the circuit board together, but in the prior art, the side surface of the metal pin after the plastic package body is cut cannot climb up to the metal area of the side surface of the plastic package body due to a tin-free layer interface. The problem of cold soldering or cold soldering on the side surface of the metal pin is that the cold soldering or cold soldering cannot be clearly observed in appearance, and particularly, the method is applied to the first-level safety and the second-level safety in automotive electronics, so that tin climbing of the metal pin on the side surface of the plastic package body is particularly important.
In order to solve the problem, the outer ends of the back sides of the leads of the lead frame are cut by the conventional method in the industry (see fig. 1A) to form step-shaped steps, and then the cutting operation is performed (see fig. 1B), so that a packaging structure with steps on the side surfaces of the leads can be obtained (see fig. 1C), and the reliability of the packaging structure when the PCB is welded is improved.
However, when the exposed bonding pad and the conductive bonding pad at the bottom of the package structure with the step of the lead are soldered to the thermal bonding pad on the PCB, as shown in a portion a in fig. 1D, air is easily remained at the step of the lead and cannot be discharged, so that the solder bondability is poor. Especially, when the product works, the air remained in the step can generate air expansion due to the product heating, so that the tin layer between the PCB pad and the pins of the plastic package body is cracked, the electrical function of the integrated circuit is poor in contact, and the electrical function can be directly stopped working when the electrical function is serious.
In addition, in the manufacturing process of the package structure with the stepped pins, the outer ends of the back surfaces of the pins of the lead frame need to be cut firstly, and then the front surface of the packaged lead frame needs to be cut, so that the cutting efficiency is reduced, the consumption of a cutting tool is easy to accelerate, and the manufacturing cost is increased.
In addition, the outer end of the back of the lead frame is half-etched to form a water-drop-shaped groove (see fig. 1E), due to the etching characteristic, the groove formed by the method is an inward-concave arc, and the pin groove of the structure is also easy to have residual air which cannot be discharged (see fig. 1F), so that the soldering tin bonding property is poor.
In addition, the industry also has a package structure with L-shaped outer pins (shown in figure 1G) or J-shaped outer pins (shown in figure 1H), which utilizes a traditional lead frame packaged by the outer pins to carry out the operations of chip mounting, routing and packaging, the package structure is provided with the outer pins (shown in figure 1I) with a certain length before the punching process, a forming die needs to be extended between the outer pins and a plastic package body during the punching process, and the outer pins are bent towards the side surface of the plastic package body to prepare the L-shaped outer pins or the C-shaped outer pins.
However, the package structure for forming the L-shaped outer lead or the C-shaped outer lead by the rib cutting molding also has the following defects when forming the L-shaped outer lead or the C-shaped outer lead: first, when the outer leads are formed, the outer leads are bent toward the side of the plastic package body, and the inner leads at the position a in fig. 1G and fig. 1H cause stress of the metal leads that are pulled out from the plastic package body downward and outward due to the influence of the rebounding acting force of the metal, and under the condition that the acting force is downward, a delamination phenomenon is easily generated between the upper surface of the inner leads at the position a and the lower surface of the plastic package material. In severe cases, open circuit can be formed between the bonding wire at the position A and the inner pin, so that the product can fail; secondly, when the L-shaped outer pin or C-shaped outer pin packaging structure is used for forming the outer pin, the outer pin is bent towards the side face of the plastic packaging body, namely, a forming die is stretched between the outer pin and the plastic packaging body and then bent and formed, and the outer pin can be in a relation of resilience when stressed due to the fact that the metal pin has a certain elastic coefficient, so that the outer pin forms a larger horn-shaped opening as shown in a position B in a figure 1J, and the outer pin is difficult to form a shape which is vertically attached to the side face of the plastic packaging body as shown in a figure 1G; finally, the L-shaped outer pin or C-shaped outer pin packaging structure has larger volume, and because the outer pin is bent to form the L-shaped outer pin or C-shaped outer pin packaging structure, compared with the traditional inner pin packaging structure, the L-shaped outer pin or C-shaped outer pin packaging structure has wider packaging body width, and is not beneficial to the development trend of miniaturization packaging bodies.
Disclosure of Invention
The present invention provides a semiconductor package structure with a solder-climbing function on a side wall of a lead, in which the lead has an outwardly convex arc-shaped portion and a side wall portion connected to the arc-shaped portion and having the same height as a molding compound, and solder can climb to a higher height along a vertical side wall portion when a PCB is soldered, so as to increase a bonding area between the solder and the lead, and the soldering state can be clearly distinguished from an appearance directly in a solder-climbing state. In addition, the convex arc structure of the pin can enable air at the pin to be discharged along the convex arc while tin is climbed, so that the phenomenon that air bubbles are remained in the tin solder to influence the combination of the pin and the PCB can be avoided, the welding performance and the welding reliability of a product are improved, and the welding state is visually checked; finally, the thickened copper sheet is arranged on the back of the base island, so that the requirement of high heat dissipation of the power semiconductor is further met.
The invention relates to a manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function, which is characterized in that a groove with a certain depth is formed on a carrier plate by utilizing an etching process, and then a metal layer is electroplated in the groove to form a pin with a vertical side wall. In addition, the original array type plastic package body can be individualized only by removing the carrier plate without cutting, so that the equipment cost, the production cost, the material cost, the labor cost and the quality cost in more cutting procedures are fully saved; the thickened base island is formed by electroplating twice, so that the requirement of high heat dissipation of the power semiconductor is further met.
The invention relates to a manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function, which utilizes an etching process to form a groove with a certain depth on a carrier plate, firstly a thickened copper sheet is arranged at the position of a base island in the groove, and then a metal layer is electroplated in the groove to form a pin with a vertical side wall. In addition, the invention can realize the original array type plastic package body singleness only by removing the carrier plate without cutting, thereby fully saving the equipment cost, the production cost, the material cost, the labor cost and the quality cost in more cutting procedures.
The technical scheme adopted by the invention for solving the problems is as follows: a semiconductor packaging structure with a pin side wall tin climbing function comprises a base island and a pin, wherein the pin is arranged around the base island, a thickening layer is arranged on the front surface of the base island, the base island and the thickening layer form a thickened base island, the height of the thickened base island is higher than that of the pin, the pin comprises a plane part and a side wall part, the side wall part is positioned outside the plane part, the plane part and the side wall part are in smooth transition connection through an arc part, the convex surface of the arc part faces the lower side outwards, a chip is arranged on the front surface of the thickened base island and is electrically connected with the pin through a metal welding wire, plastic packaging materials are packaged in the pin, the base island and the peripheral area of the chip, the height of the side wall part is flush with the plastic packaging materials, and the inner surfaces of the plane part, the arc part and the side wall part are packaged, the outer surfaces of the planar portion, the arcuate portion and the sidewall portion are exposed to the exterior of the molding compound.
A semiconductor packaging structure with a pin side wall tin-climbing function comprises a copper sheet, a pin and a base island, the surface of the copper sheet is provided with a base island, the pin is arranged around the copper sheet and comprises a plane part and a side wall part, the side wall part is positioned outside the plane part, the plane part and the side wall part are smoothly transited and connected through the arc part, the convex surface of the arc part faces the lower side outwards, the front surface of the base island is provided with a chip, the chip is electrically connected with the pin through a metal welding wire, the pins, the base islands and the peripheral area of the chip are encapsulated with plastic packaging materials, the height of the side wall parts is flush with the plastic packaging materials, the inner surfaces of the plane part, the arc part and the side wall part are covered in the plastic package material, and the outer surfaces of the plane part, the arc part and the side wall part are exposed out of the plastic package material.
The pins and the base islands are metal circuit layers formed by electroplating.
A manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function comprises the following steps:
step one, taking a metal carrier plate;
step two, coating or printing photoresist materials capable of being exposed and developed on the front surface and the back surface of the metal carrier plate, and exposing, developing and removing part of the photoresist materials on the surface of the metal carrier plate by using exposure and development equipment to expose the area of the surface of the metal carrier plate, which is required to be etched;
chemically etching the area of the front surface of the metal carrier plate subjected to exposure and development to form a groove, wherein the bottom and the side wall of the groove are planes, the joint of the bottom and the side wall is etched to be arc-shaped, and the photoresist film on the surface of the metal carrier plate is removed after etching is finished;
electroplating an upper metal circuit layer in the groove on the front surface of the metal carrier plate to form a base island and a pin, wherein the pin comprises a plane part and a side wall part, the side wall part is positioned outside the plane part, the plane part and the side wall part are connected in a smooth transition mode through an arc part, the convex surface of the arc part faces outwards and downwards, and the height of the side wall part is flush with the top surface of the groove;
electroplating a metal circuit layer on the base island in the groove on the front surface of the metal carrier plate again to form a thickened base island;
coating a bonding material or solder on the surface of the thickened base island, then implanting a chip on the bonding material or solder, and performing bonding metal wire operation between the front surface of the chip and the front surface of the pin;
step seven, the metal carrier plate which is subjected to the chip mounting and routing operation in the step six is plastically packaged by adopting a plastic packaging material;
and step eight, removing the metal carrier plate, exposing the pins and thickening the outer surface of the base island, and independently opening the original array type plastic package body to obtain the semiconductor packaging structure with the pin side surface tin climbing function.
A manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function comprises the following steps:
step one, taking a metal carrier plate;
step two, coating or printing photoresist materials capable of being exposed and developed on the front surface and the back surface of the metal carrier plate, and exposing, developing and removing part of the photoresist materials on the surface of the metal carrier plate by using exposure and development equipment to expose the area of the surface of the metal carrier plate, which is required to be etched;
chemically etching the area of the front surface of the metal carrier plate subjected to exposure and development to form a groove, wherein the bottom and the side wall of the groove are planes, the joint of the bottom and the side wall is etched to be arc-shaped, and the photoresist film on the surface of the metal carrier plate is removed after etching is finished;
step four, arranging a copper sheet at the position of the subsequent electroplating base island in the groove on the front surface of the metal carrier plate;
step five, electroplating a metal line layer on the copper sheet in the groove on the front surface of the metal carrier plate to form a base island, electroplating the metal line layer on the peripheral part of the copper sheet in the groove on the front surface of the metal carrier plate to form a pin, wherein the pin comprises a plane part and a side wall part, the side wall part is positioned outside the plane part, the plane part and the side wall part are in smooth transition connection through an arc part, the convex surface of the arc part faces outwards and downwards, and the height of the side wall part is flush with the top surface of the groove;
coating a bonding substance or solder on the surface of the base island, then implanting a chip on the bonding substance or solder, and carrying out bonding metal wire welding operation between the front surface of the chip and the front surface of the pin;
step seven, the metal carrier plate which is subjected to the chip mounting and routing operation in the step six is plastically packaged by adopting a plastic packaging material;
and step eight, removing the metal carrier plate to expose the outer surfaces of the pins and the copper sheet, and independently opening the original array type plastic package body to obtain the semiconductor packaging structure with the pin side surface tin-climbing function.
The etching liquid adopts copper chloride or ferric chloride.
The photoresist film is removed by softening with chemical solution and washing with high-pressure water.
The metal circuit layer material is copper, aluminum or nickel.
The metal welding wire is made of gold, silver, copper or aluminum; the shape of the metal welding wire is a wire shape or a belt shape.
The encapsulation mode of the plastic package material adopts a mold glue pouring mode, a spraying mode of spraying equipment or a glue brushing mode, and the plastic package material adopts epoxy resin with or without filler substances.
Compared with the prior art, the invention has the advantages that:
1. the invention relates to a semiconductor packaging structure with a pin side wall tin climbing function and a manufacturing process thereof, wherein a groove formed by etching a carrier plate is electroplated with an arc part which protrudes outwards and a pin which is connected with the arc part and has the same height with a side wall part of a plastic packaging material, and soldering tin can climb to a higher height along a vertical side wall when a PCB is welded, so that the combination area of the soldering tin and the pin is increased, the tin climbing state can be clearly seen from the appearance, in addition, the protruding arc structure of the pin can lead the air at the pin to be discharged along the protruding arc when the tin climbs, thereby avoiding that bubbles are remained in the soldering tin to influence the combination of the pin and the PCB, and improving the welding performance and the welding reliability of a product;
2. according to the semiconductor packaging structure with the pin side wall tin-climbing function and the manufacturing process thereof, the vertical side wall of the pin is formed by electroplating instead of cutting ribs of the outer pin of the traditional frame, and the layering between the pin and a plastic packaging material cannot be caused in the forming process of the side wall, so that the reliability of a product is influenced;
3. according to the semiconductor packaging structure with the pin side wall tin climbing function and the manufacturing process thereof, the thickened base island is formed by electroplating twice or the thickened copper sheet is arranged below the base island, so that the requirement of high heat dissipation of a power semiconductor is further met;
4. according to the semiconductor packaging structure with the pin side wall tin-climbing function and the manufacturing process thereof, the original array type plastic packaging body can be singulated by only removing the carrier plate without cutting, so that the cutting cost can be saved.
Drawings
Fig. 1A-1B are schematic diagrams illustrating two-time cutting operations for manufacturing a package structure with a step in the lead.
Fig. 1C is a schematic diagram of a conventional package structure with a step on a lead.
Fig. 1D is a schematic diagram of a conventional package structure with a step on a lead and a PCB.
Fig. 1E is a schematic diagram of a conventional package structure with a pin having a drop-shaped groove.
Fig. 1F is a schematic diagram of a conventional package structure with a pin having a drop-shaped groove and a PCB board.
Fig. 1G is a schematic diagram of a conventional package structure with L-shaped outer leads.
Fig. 1H is a schematic diagram of a conventional package structure with C-shaped outer leads.
Fig. 1I is a schematic structural diagram of a conventional package structure having an L-shaped outer lead or a C-shaped outer lead before rib cutting and molding.
Fig. 1J is a schematic structural view of a conventional package structure with L-shaped outer leads after rib cutting and molding.
Fig. 2 is a schematic view of a semiconductor package structure with a lead sidewall solder climbing function according to an embodiment 1 of the present invention.
Fig. 3 is a schematic perspective view of a semiconductor package structure with a lead sidewall solder-climbing function according to embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of a semiconductor package structure with a lead sidewall solder-climbing function according to an embodiment 1 of the present invention combined with a PCB board.
Fig. 5-15 are schematic flow charts illustrating a manufacturing process of a semiconductor package structure with a lead sidewall solder-climbing function according to the present invention.
Fig. 16 is a schematic view of a semiconductor package structure with a lead sidewall solder climbing function according to embodiment 2 of the present invention.
Fig. 17 is a schematic perspective view of a semiconductor package structure with a lead sidewall solder climbing function according to embodiment 2 of the present invention.
Fig. 18 is a schematic view of a semiconductor package structure with a lead sidewall solder-climbing function according to an embodiment 2 of the present invention combined with a PCB board.
Fig. 19 to 29 are schematic flow charts illustrating a manufacturing process of a semiconductor package structure with a lead sidewall solder-climbing function according to the present invention.
Wherein:
base island 1
Flat part 2.1
Arc-shaped part 2.2
Side wall part 2.3
Adhesive substance or solder 4
Metal bonding wire 6
A copper sheet 8.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example 1: twice electroplating to form thickened base island
As shown in fig. 2 and fig. 3, in this embodiment, a semiconductor package structure with a pin sidewall tin-climbing function includes a base island 1 and a pin 2, the pin 2 and the base island 3 are metal circuit layers formed by electroplating, the pin 2 is disposed around the base island 3, the front surface of the base island 1 is provided with a thickening layer 3, the base island 1 and the thickening layer 3 form a thickened base island, the height of the thickened base island is higher than that of the pin 2, the pin 2 includes a planar portion 2.1 and a sidewall portion 2.3, the sidewall portion 2.3 is located outside the planar portion 2.1, the planar portion 2.1 and the sidewall portion 2.3 are smoothly transitionally connected through an arc portion 2.2, a convex surface of the arc portion 2.2 faces to the outside lower side, the front surface of the thickened base island is provided with a chip 5 through an adhesive substance or solder 4, the chip 5 is electrically connected with the pin 2 through a metal bonding wire 6, a plastic package material 7 is encapsulated in the peripheral areas of the pin 2, the base island 3 and the chip 5, the height of the sidewall part 2.3 is flush with that of the plastic package material 7, the inner surfaces of the plane part 2.1, the arc part 2.2 and the sidewall part 2.3 are coated in the plastic package material 7, and the outer surfaces of the plane part 2.1, the arc part 2.2 and the sidewall part 2.3 are exposed out of the plastic package material 7;
fig. 4 is a schematic diagram of the combination of the semiconductor package structure with the pin side wall tin-climbing function and the PCB of the present invention, the groove formed by etching the carrier plate is directly electroplated with the outward convex arc and the pin connected with the outward convex arc and having the same height side wall as the molding compound, the soldering tin can climb to a higher height along the vertical side wall when the PCB is welded, so as to increase the combination area of the soldering tin and the pin, the tin-climbing state can be clearly seen from the appearance, in addition, the outward convex arc structure of the pin can discharge the air at the pin along the outward convex arc while the tin is climbed, thereby avoiding the air bubble remained in the soldering tin from influencing the combination of the pin and the PCB, and improving the welding performance and the welding reliability of the product.
A manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function comprises the following steps:
step one, referring to fig. 5, a metal carrier plate with a proper thickness is taken, the purpose of the plate is to provide support for circuit manufacturing and circuit layer structure, the material of the plate mainly comprises a metal material, and the material of the metal material can be a copper material, an iron material, a stainless steel material or other metal substances with a conductive function;
step two, referring to fig. 6, a photoresist material capable of being exposed and developed is coated or printed on the front surface and the back surface of the metal carrier to protect the subsequent metal layer etching process. The photoresist material may be a photoresist film or a photoresist. Referring to fig. 7, an exposure and development device is used to expose, develop and remove a portion of the photoresist material on the surface of the metal carrier to expose the area of the metal carrier where the pattern is to be etched;
and step three, referring to fig. 8, performing chemical etching on the area where the front surface of the metal carrier is exposed and developed, etching to form a groove, wherein the bottom and the side wall of the groove are flat, and the joint of the bottom and the side wall is etched to be arc-shaped due to the etching characteristic. The etching liquid can be copper chloride or ferric chloride or other chemical etching liquid. Referring to fig. 9, after the etching is completed, the photoresist film on the surface of the metal carrier is removed, and the photoresist film can be removed by softening with chemical solution and washing with high-pressure water;
step four, referring to fig. 10, a metal circuit layer is electroplated in the groove on the front surface of the metal carrier to form a base island and a pin, wherein the pin comprises a planar portion and a sidewall portion, the sidewall portion is located outside the planar portion, the planar portion and the sidewall portion are in smooth transition connection through an arc portion, a convex surface of the arc portion faces outwards and downwards, a height of the sidewall portion is flush with a top surface of the groove, and the metal circuit layer is usually made of copper, aluminum, nickel and the like, and can also be made of other conductive metal substances;
step five, referring to fig. 11, a metal circuit layer is electroplated on the base island in the groove on the front surface of the metal carrier again to form a thickened base island, wherein the material of the metal circuit layer is usually copper, aluminum, nickel and the like, and can also be other conductive metal substances;
step six, referring to fig. 12, coating an adhesive substance or solder on the surface of the thickened base island, and then implanting a chip on the adhesive substance or solder. Bonding metal bonding wires between the front surface of the chip and the front surfaces of the pins, wherein the metal bonding wires are made of gold, silver, copper, aluminum or alloy materials, and can be in a filiform or a strip shape;
seventhly, referring to fig. 13, plastically packaging the metal carrier plate subjected to the chip mounting and routing operation in the sixth step by using a plastic package material, wherein the plastic package material can be encapsulated in a mold glue filling mode, a spraying mode of spraying equipment or a glue brushing mode, and the plastic package material can be epoxy resin with or without filler substances;
and step eight, referring to fig. 14 and fig. 15, removing the metal carrier plate, exposing the pins and thickening the outer surface of the base island, and independently opening the original array type plastic package body to obtain the semiconductor packaging structure with the pin side surface tin-climbing function.
The invention provides a manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function, which is characterized in that a groove with a certain depth is formed on a carrier plate by utilizing an etching process, and then a metal layer is electroplated in the groove to form a pin with a vertical side wall. In addition, the invention can realize the original array type plastic package body singleness only by removing the carrier plate without cutting, thereby saving the cutting cost.
Example 2: copper sheet arranged under chip
As shown in fig. 16 and 17, in this embodiment, a semiconductor package structure with a pin sidewall solder-climbing function includes a copper sheet 8, a pin 2, and a base island 1, where the base island 1 is disposed on a surface of the copper sheet 8, the pin 2 and the base island 1 are metal wiring layers formed by electroplating, the pin 2 is disposed around the copper sheet 8, the pin 2 includes a planar portion 2.1 and a sidewall portion 2.3, the sidewall portion 2.3 is located outside the planar portion 2.1, the planar portion 2.1 and the sidewall portion 2.3 are connected by a smooth transition through an arc portion 2.2, a convex surface of the arc portion 2.2 faces outward and is located at a lower side, a chip 5 is disposed on a front surface of the base island 1 by an adhesive substance or solder 4, the chip 5 is electrically connected to the pin 2 by a metal wire 6, the pin 2, the base island 1, and a peripheral region of the chip 5 are encapsulated with a molding compound 7, a height of the sidewall portion 2.3 is flush with the molding compound, the inner surfaces of the plane part 2.1, the arc part 2.2 and the side wall part 2.3 are covered in the plastic package material 7, and the outer surfaces of the plane part 2.1, the arc part 2.2 and the side wall part 2.3 are all exposed out of the plastic package material 7;
fig. 18 is a schematic diagram of the combination of the semiconductor package structure with the pin side wall tin-climbing function and the PCB of the present invention, the groove formed by etching the carrier plate is directly electroplated with the outward protruding arc and the pin connected with the outward protruding arc and having the same height as the side wall of the molding compound, the soldering tin can climb to a higher height along the vertical side wall when the PCB is welded, so as to increase the combination area of the soldering tin and the pin, the tin-climbing state of the soldering tin can be clearly seen from the appearance, in addition, the outward protruding arc structure of the pin can make the air at the pin be discharged along the outward protruding arc while the soldering tin is climbed, thereby preventing the air bubble remained in the soldering tin from influencing the combination of the pin and the PCB, and improving the welding performance and the welding reliability of the product.
A manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function comprises the following steps:
step one, referring to fig. 19, a metal carrier plate with a suitable thickness is taken, the purpose of the plate is to provide support for circuit manufacturing and circuit layer structure, the material of the plate mainly comprises a metal material, and the material of the metal material can be a copper material, an iron material, a stainless steel material or other metal substances with a conductive function;
step two, referring to fig. 20, a photoresist material capable of being exposed and developed is coated or printed on the front and back surfaces of the metal carrier to protect the subsequent metal layer etching process. The photoresist material may be a photoresist film or a photoresist. Referring to fig. 21, an exposure and development device is used to expose, develop and remove a portion of the photoresist material on the surface of the metal carrier to expose the area of the metal carrier where the pattern is to be etched;
and step three, referring to fig. 22, performing chemical etching on the area where the front surface of the metal carrier is exposed and developed, and etching to form a groove, wherein the bottom and the side wall of the groove are flat, and the joint of the bottom and the side wall is etched into an arc shape due to the etching characteristic. The etching liquid can be copper chloride or ferric chloride or other chemical etching liquid. Referring to fig. 23, after the etching is completed, the photoresist film on the surface of the metal carrier is removed, and the photoresist film can be removed by softening with chemical solution and washing with high-pressure water;
step four, referring to fig. 24, a copper sheet is arranged at the position of the subsequent electroplating base island in the groove on the front surface of the metal carrier plate;
step five, referring to fig. 25, a metal line layer is electroplated on the copper sheet in the groove on the front surface of the metal carrier plate to form a base island, the metal line layer is electroplated on the peripheral part of the copper sheet in the groove on the front surface of the metal carrier plate to form a pin, the pin comprises a planar part and a side wall part, the side wall part is positioned outside the planar part, the planar part and the side wall part are in smooth transition connection through an arc part, the convex surface of the arc part faces outwards and downwards, the height of the side wall part is flush with the top surface of the groove, and the metal line layer is usually made of copper, aluminum, nickel and the like or other conductive metal substances;
step six, referring to fig. 26, coating an adhesive substance or solder on the surface of the base island, and then implanting a chip on the adhesive substance or solder. Bonding metal bonding wires between the front surface of the chip and the front surfaces of the pins, wherein the metal bonding wires are made of gold, silver, copper, aluminum or alloy materials, and can be in a filiform or a strip shape;
seventhly, referring to fig. 27, plastically packaging the metal carrier plate subjected to the chip mounting and routing operation in the sixth step by using a plastic package material, wherein the plastic package material can be encapsulated in a mold glue filling mode, a spraying mode of spraying equipment or a glue brushing mode, and the plastic package material can be epoxy resin with or without filler substances;
and step eight, referring to fig. 28 and fig. 29, removing the metal carrier plate to expose the outer surfaces of the pins and the copper sheet, and independently opening the original array type plastic package body to obtain the semiconductor packaging structure with the pin side surface tin-climbing function.
The invention provides a manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function, which is characterized in that a groove with a certain depth is formed on a carrier plate by utilizing an etching process, a thickened copper sheet is arranged at the position of a base island in the groove, and then a metal layer is electroplated in the groove to form a pin with a vertical side wall. In addition, the invention can realize the original array type plastic package body singleness only by removing the carrier plate without cutting, thereby saving the cutting cost.
In addition to the above embodiments, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the scope of the claims of the present invention.
Claims (10)
1. The utility model provides a semiconductor package structure with pin lateral wall climbs tin function which characterized in that: it includes base island (1) and pin (2), base island (1) and pin (2) are the metal wiring layer of electroplating formation, pin (2) set up around base island (1), base island (1) openly is provided with thickening layer (3), base island (1) and thickening layer (3) form the thickening base island, the height that highly is higher than pin (2) of thickening base island, pin (2) include planar part (2.1) and lateral wall portion (2.3), lateral wall portion (2.3) are located planar part (2.1) outside, connect through arc part (2.2) smooth transition between planar part (2.1) and lateral wall portion (2.3), the convex surface of arc part (2.2) is towards outside downside, thickening base island openly is provided with chip (5), chip (5) form electric connection through metal bonding wire (6) and pin (2), the lead (2), the base island (1) and the peripheral area of the chip (5) are encapsulated with a plastic package material (7), the height of the side wall part (2.3) is flush with the plastic package material (7), the inner surfaces of the plane part (2.1), the arc part (2.2) and the side wall part (2.3) are wrapped in the plastic package material (7), and the outer surfaces of the plane part (2.1), the arc part (2.2) and the side wall part (2.3) are exposed out of the plastic package material (7).
2. The utility model provides a semiconductor package structure with pin lateral wall climbs tin function which characterized in that: the copper-clad plate comprises a copper sheet (8), a pin (2) and a base island (1), wherein the base island (1) and the pin (2) are metal circuit layers formed by electroplating, the base island (1) is arranged on the surface of the copper sheet (8), the pin (2) is arranged around the copper sheet (8), the pin (2) comprises a plane part (2.1) and a side wall part (2.3), the side wall part (2.3) is positioned on the outer side of the plane part (2.1), the plane part (2.1) and the side wall part (2.3) are in smooth transition connection through an arc part (2.2), the convex surface of the arc part (2.2) faces the lower side outwards, a chip (5) is arranged on the front surface of the base island (1), the chip (5) is electrically connected with the pin (2) through a metal welding wire (6), and a plastic packaging material (7) is packaged in the peripheral areas of the pin (2), the base island (3) and the chip (5, the height of the side wall part (2.3) is flush with that of the plastic package material (7), the inner surfaces of the plane part (2.1), the arc part (2.2) and the side wall part (2.3) are covered in the plastic package material (7), and the outer surfaces of the plane part (2.1), the arc part (2.2) and the side wall part (2.3) are exposed out of the plastic package material (7).
3. The semiconductor package structure with the lead sidewall tin-climbing function according to claim 1 or 2, wherein: the pins (2) and the base islands (1) are metal circuit layers formed by electroplating.
4. A manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function is characterized by comprising the following steps:
step one, taking a metal carrier plate;
step two, coating or printing photoresist materials capable of being exposed and developed on the front surface and the back surface of the metal carrier plate, and exposing, developing and removing part of the photoresist materials on the surface of the metal carrier plate by using exposure and development equipment to expose the area of the surface of the metal carrier plate, which is required to be etched;
chemically etching the area of the front surface of the metal carrier plate subjected to exposure and development to form a groove, wherein the bottom and the side wall of the groove are planes, the joint of the bottom and the side wall is etched to be arc-shaped, and the photoresist film on the surface of the metal carrier plate is removed after etching is finished;
electroplating an upper metal circuit layer in the groove on the front surface of the metal carrier plate to form a base island and a pin, wherein the pin comprises a plane part and a side wall part, the side wall part is positioned outside the plane part, the plane part and the side wall part are connected in a smooth transition mode through an arc part, the convex surface of the arc part faces outwards and downwards, and the height of the side wall part is flush with the top surface of the groove;
electroplating a metal circuit layer on the base island in the groove on the front surface of the metal carrier plate again to form a thickened base island;
coating a bonding substance or solder on the surface of the thickened base island, then implanting a chip on the bonding substance or solder, and carrying out bonding metal wire welding operation between the front surface of the chip and the front surface of the pin;
step seven, the metal carrier plate which is subjected to the chip mounting and routing operation in the step six is plastically packaged by adopting a plastic packaging material;
and step eight, removing the metal carrier plate, exposing the pins and thickening the outer surface of the base island, and independently opening the original array type plastic package body to obtain the semiconductor packaging structure with the pin side surface tin climbing function.
5. A manufacturing process of a semiconductor packaging structure with a pin side wall tin-climbing function is characterized by comprising the following steps:
step one, taking a metal carrier plate;
step two, coating or printing photoresist materials capable of being exposed and developed on the front surface and the back surface of the metal carrier plate, and exposing, developing and removing part of the photoresist materials on the surface of the metal carrier plate by using exposure and development equipment to expose the area of the surface of the metal carrier plate, which is required to be etched;
chemically etching the area of the front surface of the metal carrier plate subjected to exposure and development to form a groove, wherein the bottom and the side wall of the groove are planes, the joint of the bottom and the side wall is etched to be arc-shaped, and the photoresist film on the surface of the metal carrier plate is removed after etching is finished;
step four, arranging a copper sheet at the position of the subsequent electroplating base island in the groove on the front surface of the metal carrier plate;
step five, electroplating a metal line layer on the copper sheet in the groove on the front surface of the metal carrier plate to form a base island, electroplating the metal line layer on the peripheral part of the copper sheet in the groove on the front surface of the metal carrier plate to form a pin, wherein the pin comprises a plane part and a side wall part, the side wall part is positioned outside the plane part, the plane part and the side wall part are in smooth transition connection through an arc part, the convex surface of the arc part faces outwards and downwards, and the height of the side wall part is flush with the top surface of the groove;
coating a bonding substance or solder on the surface of the base island, then implanting a chip on the bonding substance or solder, and carrying out bonding metal wire welding operation between the front surface of the chip and the front surface of the pin;
step seven, the metal carrier plate which is subjected to the chip mounting and routing operation in the step six is plastically packaged by adopting a plastic packaging material;
and step eight, removing the metal carrier plate to expose the outer surfaces of the pins and the copper sheet, and independently opening the original array type plastic package body to obtain the semiconductor packaging structure with the pin side surface tin-climbing function.
6. The manufacturing process of the semiconductor package structure with the lead sidewall tin-climbing function according to claim 4 or 5, wherein: the chemical liquid used for etching is copper chloride or ferric chloride.
7. The manufacturing process of the semiconductor package structure with the lead sidewall tin-climbing function according to claim 4 or 5, wherein: the photoresist film is removed by softening with chemical solution and washing with high-pressure water.
8. The manufacturing process of the semiconductor package structure with the lead sidewall tin-climbing function according to claim 4 or 5, wherein: the metal circuit layer material is copper, aluminum or nickel.
9. The manufacturing process of the semiconductor package structure with the lead sidewall tin-climbing function according to claim 4 or 5, wherein: the metal welding wire is made of gold, silver, copper or aluminum; the shape of the metal welding wire is a wire shape or a belt shape.
10. The manufacturing process of the semiconductor package structure with the lead sidewall tin-climbing function according to claim 4 or 5, wherein: the encapsulation mode of the plastic package material adopts a mold glue pouring mode, a spraying mode of spraying equipment or a glue brushing mode, and the plastic package material adopts epoxy resin with or without filler substances.
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| CN109065518B (en) * | 2018-06-13 | 2020-12-25 | 南通通富微电子有限公司 | Semiconductor chip packaging array |
| CN109037183A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging array and semiconductor chip packaging device |
| CN109065519B (en) * | 2018-06-13 | 2020-12-25 | 南通通富微电子有限公司 | Semiconductor chip packaging device |
| CN109037077B (en) * | 2018-06-13 | 2020-12-25 | 南通通富微电子有限公司 | Semiconductor chip packaging method |
| CN108899286B (en) * | 2018-07-13 | 2020-04-17 | 江苏长电科技股份有限公司 | Single double metal plate packaging structure and packaging method thereof |
| CN108695172B (en) * | 2018-07-13 | 2020-04-28 | 江苏长电科技股份有限公司 | Single double metal plate packaging structure and packaging method thereof |
| CN115719713B (en) * | 2023-01-09 | 2023-05-30 | 江苏长晶浦联功率半导体有限公司 | Flat pin-free element and packaging method thereof |
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| JP4334364B2 (en) * | 2004-01-26 | 2009-09-30 | 株式会社リコー | Semiconductor device and manufacturing method of semiconductor device |
| US7816769B2 (en) * | 2006-08-28 | 2010-10-19 | Atmel Corporation | Stackable packages for three-dimensional packaging of semiconductor dice |
| JP2010192847A (en) * | 2009-02-20 | 2010-09-02 | Yamaha Corp | Lead frame and method of manufacturing semiconductor package using the same |
| CN102842515A (en) * | 2011-06-23 | 2012-12-26 | 飞思卡尔半导体公司 | Method for assembling semiconductor device |
| CN103474406A (en) * | 2013-09-27 | 2013-12-25 | 华天科技（西安）有限公司 | Copper-free flat packaging piece of AAQFN frame product and manufacturing process thereof |
| CN105206596B (en) * | 2014-06-06 | 2018-12-07 | 恩智浦美国有限公司 | Packaging integrated circuit devices with bending lead |
| CN105405823A (en) * | 2014-08-20 | 2016-03-16 | 飞思卡尔半导体公司 | Semiconductor device with inspectable solder joints |
| CN105895610B (en) * | 2014-11-18 | 2019-11-22 | 恩智浦美国有限公司 | Semiconductor device and lead frame with vertical connection strap |
| JP2016219520A (en) * | 2015-05-18 | 2016-12-22 | Ｔｏｗａ株式会社 | Semiconductor device and manufacturing method of the same |
| JP6840466B2 (en) * | 2016-03-08 | 2021-03-10 | 株式会社アムコー・テクノロジー・ジャパン | Semiconductor package and manufacturing method of semiconductor package |
| US9947614B2 (en) * | 2016-03-09 | 2018-04-17 | Nxp Usa, Inc. | Packaged semiconductor device having bent leads and method for forming |
| CN106783792A (en) * | 2017-03-22 | 2017-05-31 | 江苏长电科技股份有限公司 | There is a kind of plastic-sealed body lateral leads side to climb the encapsulating structure of tin performance |
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