CN209896054U - Lead frame, lead frame array and packaging structure - Google Patents
Lead frame, lead frame array and packaging structure Download PDFInfo
- Publication number
- CN209896054U CN209896054U CN201920988965.4U CN201920988965U CN209896054U CN 209896054 U CN209896054 U CN 209896054U CN 201920988965 U CN201920988965 U CN 201920988965U CN 209896054 U CN209896054 U CN 209896054U
- Authority
- CN
- China
- Prior art keywords
- pin
- lead frame
- sub
- lead
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The application provides a lead frame, a lead frame array and a packaging structure, the lead frame comprises a plurality of first pins and at least one second pin, and the second pin comprises a first sub-pin and a second sub-pin electrically connected with the first sub-pin. According to the lead frame, the second pin comprises the first sub-pin and the second sub-pin, the first sub-pin and the second sub-pin can be respectively welded with an external circuit, the welding effect is improved, the desoldering is reduced or even avoided, and therefore the yield of semiconductor products is improved.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a lead frame, a lead frame array and a packaging structure.
Background
Packaging is a very important step in the manufacturing process of electronic devices, and various chips (chip die) can be directly led out by the packaging process so as to be electrically connected with external circuits. For each different chip, a suitable package format is usually selected. Among them, flip chip packaging is a process of mounting a bare chip within a package body.
Specifically, the flip chip designs the front surface of the chip as a metal bump (pilar) and solder cap (solder cap) structure, connects the flip chip with the lead frame through flux (flux), and is cured after reflow to achieve the purpose of electrical conduction. In a lead frame in the existing design, pins positioned at four corners of the lead frame are relatively independent, and when the lead frame is welded to an external circuit, the pins are easy to be detached, so that the yield of products is influenced.
SUMMERY OF THE UTILITY MODEL
The application provides a lead frame, a lead frame array and a packaging structure for improving welding effect.
The application provides a lead frame, the lead frame includes a plurality of first pins and at least one second pin, the second pin includes first sub pin and with first sub pin electric connection's second sub pin.
Further, the first sub-pins and one first pin are arranged along a first direction, and the second sub-pins and the other first pin are arranged along a second direction.
Furthermore, the lead frame comprises a plurality of second pins arranged along the circumferential direction, and a plurality of first pins arranged along the first direction or the second direction are arranged between the two second pins.
Further, the extending direction of the first sub-lead is perpendicular to the extending direction of the second sub-lead.
Further, the lead frame comprises a third pin, the third pin comprises an irregular part, and at least one contour line of the irregular part is a curve.
Furthermore, the lead frame comprises at least two third pins, the two third pins are arranged along the first direction, and the first pin is arranged between the two third pins.
Further, the lead frame includes at least two third pins, one third pin and the first sub-pin are arranged along a first direction, and the other third pin and the second sub-pin are arranged along a second direction.
Furthermore, the lead frame comprises a plurality of half-etched regions connected with the first pins or the second pins, each half-etched region corresponds to the first pins or the second pins, the thickness of each half-etched region is smaller than that of each first pin or each second pin, and the lead frame is not provided with a half-etched region corresponding to the third pin.
The present application further provides a lead frame array, which comprises a plurality of lead frames as described above, a plurality of the lead frames are arranged in a matrix, the first sub-pin of one lead frame is connected to the first sub-pin of the adjacent lead frame, and the second sub-pin of the lead frame is connected to the second sub-pin of the other adjacent lead frame.
The application also provides a packaging structure, packaging structure includes the chip, carries out the packaging body of encapsulation and as before the lead frame to the chip, the chip flip-chip welds on the lead frame.
According to the lead frame, the second pin comprises the first sub-pin and the second sub-pin, the first sub-pin and the second sub-pin can be respectively welded with an external circuit, the welding effect is improved, the desoldering is reduced or even avoided, and therefore the yield of semiconductor products is improved.
Drawings
FIG. 1 is a schematic front view of one embodiment of a lead frame of the present application;
FIG. 2 is a schematic diagram of a front view of one embodiment of a lead frame array of the present application;
FIG. 3 is a schematic front view of another embodiment of a lead frame of the present application;
fig. 4 is a schematic cross-sectional view of an embodiment of the package structure of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the invention belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The application provides a lead frame, the lead frame includes a plurality of first pins and at least one second pin, the second pin includes first sub pin and with first sub pin electric connection's second sub pin.
Referring to fig. 1, in the present embodiment, a lead frame 100 is used for providing mechanical support for a chip and realizing connection between the chip and an external circuit. The lead frame 100 has a first region corresponding to the chip and a second region located outside the first region, where the first region is surrounded by a dotted line in fig. 1, and the second region is a region outside the dotted line. The second area is only used as a narrow reserved edge after chip packaging, which can be used to fill the package to completely wrap the packaged chip. In some embodiments, leadframe 100 has only a first region.
The lead frame 100 includes a plurality of first leads 10 and at least one second lead 20, and the "plurality" in this application can be understood as two or more, and the leads not labeled in fig. 1 are all the first leads. The first lead 10 is substantially in the shape of a long strip. The second lead 20 includes a first sub-lead 21 and a second sub-lead 22 electrically connected to the first sub-lead 21, and an extending direction (first direction X) of the first sub-lead 21 is perpendicular to an extending direction (second direction Y) of the second sub-lead 22, so that the second lead 20 is L-shaped as a whole. The first sub-leads 21 and the plurality of first leads 10 are arranged along a first direction X, and the second sub-leads 22 and the other plurality of first leads 10 are arranged along a second direction Y. In other embodiments, the second pin may further include more sub-pins.
In this embodiment, the lead frame 100 includes four second pins 20, and the second pins 20 extend along the circumferential direction of the lead frame 100 and are disposed at four corners of the lead frame 100. A plurality of first pins 10 arranged along the first direction X or the second direction Y are disposed between any two second pins. In other embodiments, the lead frame may also include two second pins.
Because the second pin 20 includes the first sub-pin 21 and the second sub-pin 22, when the packaged chip structure is welded to an external circuit, the first sub-pin 21 and the second sub-pin 22 can be respectively welded to the external circuit, which is beneficial to improving the welding effect and avoiding poor products caused by desoldering.
In an actual packaging process, a plurality of chips are packaged simultaneously. Therefore, before packaging, the lead frame is not an independent unit, but a plurality of lead frames 100 shown in fig. 1 are arranged in an array to form a lead frame array, and the specific structure is shown in fig. 2. Fig. 2 illustrates four lead frames, i.e., lead frames 100a, 100b, 100c, 100d, a first sub-lead 21a of one second lead of the lead frame 100a is connected to a first sub-lead 21c of one second lead of the adjacent lead frame 100c, and a second sub-lead 22a of one second lead of the lead frame 100a is connected to a second sub-lead 22b of one second lead of the adjacent lead frame 100 b. The adjacent lead frames are connected through a plurality of structures (namely the first sub-pin and the second sub-pin), and the adjacent lead frames are connected through a plurality of structures, so that the single lead frame is not easy to warp, the probability of insufficient soldering caused by reflow curing is reduced, and the qualification rate of products is improved.
Referring to fig. 1, in the present embodiment, the lead frame 100 further includes a third lead 30, and the third lead 30 is also substantially in a long bar shape. The third pin 30 differs from the first pin 10 in that: the third pin 30 includes a shaped portion 31, and two side contour lines of the shaped portion 31 are curved lines. Alternatively, the curve may be a wavy line, a polygonal line, a sinusoidal curve, or the like. When the chip is packaged, two sides of the special-shaped part 31 are covered by the packaging body, and compared with a straight contour line, the special-shaped part 31 and the packaging body have a larger bonding surface, so that the bonding force between the lead frame 100 and the packaging body is increased, and the packaging reliability is improved. In other embodiments, only the contour line of one side edge of the special-shaped portion 31 may be designed to be a curve, and the bonding force between the lead frame and the package body may also be increased to some extent.
In this embodiment, the lead frame 100 includes at least two third leads 30, the two third leads 30 are arranged along the first direction X, and the first lead 10 is disposed between the two third leads 30. In other words, the irregular parts are respectively arranged in different areas in the first direction X, so that the increased bonding force is uniformly distributed, the balance of stress applied to each area in the first direction X of the lead frame is favorably improved, and the lead frame is not easy to warp. Referring to fig. 3, in another embodiment, the lead frame 100 further includes third leads 30a, 30a having the same structure as the third lead 30, except that the third lead 30a extends along the first direction X and the third lead 30 extends along the second direction Y. The third lead 30 is arranged along the first direction X with one first lead 10, and the third lead 30a is arranged along the second direction Y with the other first lead 10. The third lead 30a is provided, which is beneficial to increasing the bonding force between the area of the lead frame 100 in the second direction Y and the package body, and further improving the reliability of the package.
The lead frame 100 further includes a plurality of half-etched regions, each of which corresponds to the first pin 10 or the second pin 20, respectively, and the half-etched regions are connected to the first pin 10 or the second pin 20 and extend toward the center of the lead frame 100. The half-etched region includes a first half-etched region 40 connected to the first lead 10 and a second half-etched region 50 connected to the second lead 20. The thickness of the first half-etched regions 40 is smaller than that of the first pins 10, and the thickness of the second half-etched regions 50 is smaller than that of the second pins 20, in this embodiment, the thickness of the first half-etched regions 40 is about half of that of the first pins 10, and the thickness of the second half-etched regions 50 is about half of that of the second pins 20. After the package body is formed, the lower parts of the first half etching area 40 and the second half etching area 50 are also wrapped by the package body, so that the chip and the pins are not easy to be stripped, and the reliability of the package structure is improved.
It should be noted that, since the third lead 30 includes the special-shaped portion 31, it can ensure that there is sufficient bonding force between the peripheral region and the package body, and therefore, the lead frame is not provided with the half-etched region corresponding to the third lead 3, which can increase the strength of the lead frame and reduce the difficulty of manufacturing the lead frame. And because the third pins are arranged at intervals, the strength of the lead frame can be close, and the stress uniformity is ensured.
In addition, the application also provides a lead frame array. Referring to fig. 2, the lead frame array of the present embodiment includes a plurality of lead frames according to any of the foregoing embodiments arranged in an array. The first sub-lead 21a of one second lead of the lead frame 100a is connected to the first sub-lead 21c of one second lead of the adjacent lead frame 100c, and the second sub-lead 22a of one second lead of the lead frame 100a is connected to the second sub-lead 22b of one second lead of the adjacent lead frame 100 b. The adjacent lead frames are connected through a plurality of structures (namely, the first sub-pin and the second sub-pin), so that the stability of the lead frame array is improved, and for a single lead frame, the lead frame is not easy to warp due to the fact that the single lead frame is connected with the adjacent lead frames through a plurality of structures, and therefore the probability of insufficient soldering caused by reflow curing is reduced.
On the other hand, the application also provides a packaging structure. Referring to fig. 4, the package structure of the present embodiment includes a chip 200, a package body 300 for packaging the chip, and the lead frame 100 of any of the foregoing embodiments, wherein the chip 200 is flip-chip bonded on the lead frame 100 by a ball-bonding 400. In this embodiment, the package 300 is a plastic package, and in other embodiments, the package 300 may also be a ceramic package.
According to the lead frame, the second pin comprises the first sub-pin and the second sub-pin, the first sub-pin and the second sub-pin can be respectively welded with an external circuit, the welding effect is improved, the desoldering is reduced or even avoided, and therefore the yield of semiconductor products is improved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. A lead frame is characterized by comprising a plurality of first pins and at least one second pin, wherein the second pin comprises a first sub-pin and a second sub-pin electrically connected with the first sub-pin.
2. The lead frame of claim 1, wherein: the first sub-pins and one first pin are arranged along a first direction, and the second sub-pins and the other first pin are arranged along a second direction.
3. The lead frame of claim 2, wherein: the lead frame comprises a plurality of second pins which are arranged along the circumferential direction, and a plurality of first pins which are arranged along the first direction or the second direction are arranged between the two second pins.
4. The lead frame of claim 1, wherein: the extending direction of the first sub-pin is perpendicular to the extending direction of the second sub-pin.
5. The lead frame according to any one of claims 1 to 4, wherein: the lead frame comprises a third pin, the third pin comprises an abnormal-shaped part, and at least one contour line of the abnormal-shaped part is a curve.
6. The lead frame of claim 5, wherein: the lead frame comprises at least two third pins, the two third pins are arranged along a first direction, and a first pin is arranged between the two third pins.
7. The lead frame of claim 5, wherein: the lead frame comprises at least two third pins, one third pin and the first sub-pin are arranged along a first direction, and the other third pin and the second sub-pin are arranged along a second direction.
8. The lead frame of claim 5, wherein: the lead frame comprises a plurality of half-etched regions connected with a first pin or a second pin, each half-etched region corresponds to the first pin or the second pin, the thickness of each half-etched region is smaller than that of the first pin or the second pin, and the lead frame is not provided with a half-etched region corresponding to a third pin.
9. A lead frame array comprising a plurality of lead frames according to any one of claims 1 to 8, the plurality of lead frames being arranged in a matrix, the first sub-lead of a lead frame being connected to the first sub-lead of an adjacent one of the lead frames, and the second sub-lead of a lead frame being connected to the second sub-lead of another adjacent lead frame.
10. A package structure comprising a chip, a package body encapsulating the chip, and the lead frame according to any one of claims 1 to 8, wherein the chip is flip-chip bonded to the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920988965.4U CN209896054U (en) | 2019-06-27 | 2019-06-27 | Lead frame, lead frame array and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920988965.4U CN209896054U (en) | 2019-06-27 | 2019-06-27 | Lead frame, lead frame array and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209896054U true CN209896054U (en) | 2020-01-03 |
Family
ID=69021552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920988965.4U Active CN209896054U (en) | 2019-06-27 | 2019-06-27 | Lead frame, lead frame array and packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209896054U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112180643A (en) * | 2020-09-25 | 2021-01-05 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
| CN113362715A (en) * | 2021-06-17 | 2021-09-07 | 合肥维信诺科技有限公司 | Pin binding structure, array substrate and display panel |
-
2019
- 2019-06-27 CN CN201920988965.4U patent/CN209896054U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112180643A (en) * | 2020-09-25 | 2021-01-05 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
| CN112180643B (en) * | 2020-09-25 | 2022-10-21 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
| CN113362715A (en) * | 2021-06-17 | 2021-09-07 | 合肥维信诺科技有限公司 | Pin binding structure, array substrate and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6812063B2 (en) | Semiconductor package and fabricating method thereof | |
| JP5227501B2 (en) | Stack die package and method of manufacturing the same | |
| US20140179063A1 (en) | Resin sealing type semiconductor device and method of manufacturing the same, and lead frame | |
| US20030214048A1 (en) | Semiconductor package and fabricating method thereof | |
| US20040080026A1 (en) | Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same | |
| US20100178734A1 (en) | Leadless Semiconductor Package with Electroplated Layer Embedded in Encapsulant and the Method for Manufacturing the Same | |
| US20050260795A1 (en) | Method for fabricating leadless packages with mold locking characteristics | |
| US6777262B2 (en) | Method of packaging a semiconductor device having gull-wing leads with thinner end portions | |
| KR200492009Y1 (en) | Preformed lead frame and lead frame package made from the same | |
| CN109390310B (en) | Patterned lead frame | |
| JP5404083B2 (en) | Semiconductor device | |
| CN209896054U (en) | Lead frame, lead frame array and packaging structure | |
| JP6695156B2 (en) | Resin-sealed semiconductor device | |
| CN212182312U (en) | Semiconductor package | |
| US6692991B2 (en) | Resin-encapsulated semiconductor device and method for manufacturing the same | |
| JP4547086B2 (en) | Semiconductor device | |
| US8178971B2 (en) | Semiconductor device and method of manufacturing the same | |
| KR20090013564A (en) | Semiconductor package apparatus and manufacturing method the same | |
| US7619307B1 (en) | Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package | |
| US10290593B2 (en) | Method of assembling QFP type semiconductor device | |
| CN115995440A (en) | Semiconductor packaging structure and manufacturing method thereof | |
| US20210098358A1 (en) | Semiconductor package | |
| CN111276407A (en) | Semiconductor packaging structure and manufacturing method thereof | |
| CN218160365U (en) | Packaging structure | |
| US11869831B2 (en) | Semiconductor package with improved board level reliability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |