CN216413073U - Lead frame with built-in substrate - Google Patents
Lead frame with built-in substrate Download PDFInfo
- Publication number
- CN216413073U CN216413073U CN202123041684.4U CN202123041684U CN216413073U CN 216413073 U CN216413073 U CN 216413073U CN 202123041684 U CN202123041684 U CN 202123041684U CN 216413073 U CN216413073 U CN 216413073U
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- China
- Prior art keywords
- lead
- substrate
- chip
- bonding
- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model belongs to the technical field of semiconductor packaging, and particularly relates to a lead frame with a built-in substrate, wherein a chip lead is bonded on a lead substrate, and the lead substrate is bonded on the lead frame.
Description
Technical Field
The utility model belongs to the technical field of semiconductor packaging, and particularly relates to a lead frame with a built-in substrate.
Background
QFP, a Quad Flat Package (QFP), is one of surface mount packages, and leads are led out from four sides to present a gull-wing shape. There are three types of packaging materials, ceramic, metal and plastic, and plastic packaging is generally used. The pin pitch is generally 1.00mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and the like; in the direction of integrated circuit products, for the compatibility of downstream client product development, different chips sometimes need to adopt the same packaging specification, at this moment, because of the difference with the last generation chip, the chip size is too small, at this moment, it often is difficult to realize on the process of connecting the chip pad and the frame pin by adopting a simple lead bonding mode, how to match the fixed packaging specification is a problem to be solved urgently, because the size of the QFP64 frame is 10mmx10mm, the chip size is only 3mmx3mm, and the design of inner and outer rows of pads is adopted, the inner and outer ring routing process is difficult to realize by directly adopting the lead bonding process, and the routing is too long, so that the risk is very high;
the prior art has the problems that the existing wire bonding process has certain complexity, so that the lead of a chip is too long and the process is complex.
SUMMERY OF THE UTILITY MODEL
The utility model provides a lead frame with a built-in substrate, which aims to solve the problems that the existing lead bonding process in the prior art has certain complexity, so that the lead of a chip is overlong and the process is complex.
The technical problem solved by the utility model is realized by adopting the following technical scheme: the lead frame with the built-in substrate comprises a chip, wherein a lead substrate is built between the chip and the lead frame, the chip is in lead bonding with the lead substrate, and the lead substrate is in lead bonding with the lead frame.
Furthermore, the chip is arranged in the lead substrate, and the lead substrate is arranged in the lead frame.
Further, the chip lead is bonded on the lead substrate and comprises a chip first-level bonding and a first-level routing on the lead substrate, and a first-level lead bonding structure is formed;
the lead substrate lead bonding on the lead frame comprises the second-stage bonding of the lead substrate and the second-stage routing on the lead frame, and a second-stage lead bonding structure is formed.
Further, the chip includes a package or die.
Further, the package preferably includes: QFP series packages or LQFP series packages.
Further, the package preferably has an application range of: 0.65 mm-0.5 mm.
Further, the lead substrate reserves a chip space or an element space.
The beneficial technical effects are as follows:
1. this patent adopts built-in lead wire substrate between chip and lead frame, chip lead bonding is in lead substrate, lead substrate lead bonding is in the lead frame, owing to adopt built-in lead substrate between chip and lead frame, prior art adopts the outer lane routing technology to hardly realize and the routing overlength in the direct adoption lead bonding technology, has very high risk, increases one deck lead substrate, is convenient for match fixed encapsulation specification, chip lead bonding is in lead substrate, lead substrate lead bonding is in the lead frame, owing to through the two-stage routing, chip to lead substrate, lead substrate to the two-stage lead bonding of lead frame promptly, through adopting base plate and LQFP64 frame hybrid package structure. The chip is bonded to the built-in substrate, and then the substrate is bonded to the frame, so that the realization of the process is ensured, and the process risk is reduced.
2. This patent place in the lead wire base plate in the chip, place in the lead wire base plate in the lead wire frame, owing to increase one deck lead wire base plate, when the fixed but chip size of encapsulation specification is too small, through the encapsulation scheme design of the built-in base plate of QFP, solved the technology realization degree of difficulty of the direct lead bonding of chip pad to frame, guaranteed the quality of product.
3. This patent adopts the chip is including encapsulation or wafer, the encapsulation is preferably suitable for the structure and is included: a QFP series package or an LQFP series package; the preferred application range of the encapsulation is as follows: 0.65 mm-0.5 mm; and the method is compatible with the traditional packaging process, and the complexity of the packaging process is reduced.
4. This patent adopts lead wire base plate reserves chip space or component space, because can also integrate more chips or devices in the space that the base plate still left.
Drawings
FIG. 1 is a schematic structural diagram of a lead frame with a built-in substrate according to the present invention;
FIG. 2 is a schematic block diagram of a lead frame with a built-in substrate according to the present invention;
Detailed Description
The utility model is further described below with reference to the accompanying drawings:
in the figure:
1-chip, 2-lead substrate, 3-lead frame, 4-first level lead bonding structure and 5-second level lead bonding structure; example (b):
in this embodiment: as shown in fig. 1 and 2, a lead frame with a built-in substrate includes a chip 1, a lead substrate 2 is built between the chip 1 and the lead frame 3, the chip 1 is wire-bonded to the lead substrate 2, and the lead substrate 2 is wire-bonded to the lead frame 3.
The chip 1 is arranged in the lead substrate 2, and the lead substrate 2 is arranged in the lead frame 3.
The chip 1 is in lead bonding with the lead substrate 2, the chip 1 comprises a first-stage bonding and a first-stage routing on the lead substrate 2, and a first-stage lead bonding structure 4 is formed;
the lead bonding of the lead substrate 2 to the lead frame 3 comprises the second-stage bonding of the lead substrate 2 and the second-stage routing of the lead substrate to the lead frame 3, and a second-stage lead bonding structure 5 is formed.
The chip 1 comprises a package or die.
The preferred applicable structure of the package includes: QFP series packages or LQFP series packages.
The preferred application range of the encapsulation is as follows: 0.65 mm-0.5 mm.
The lead substrate 2 reserves a chip 1 space or an element space.
The working principle is as follows:
this patent is through adopting built-in lead wire substrate between chip and lead frame, chip lead bonding is in lead substrate, lead substrate lead bonding is in the lead frame, owing to adopt built-in lead substrate between chip and lead frame, prior art adopts the outer lane routing technology to hardly realize and the routing overlength in the direct adoption lead bonding technology, has very high risk, increases one deck lead substrate, is convenient for match fixed encapsulation specification, chip lead bonding is in lead substrate, lead substrate lead bonding is in the lead frame, owing to through the two-stage routing, chip to lead substrate, lead substrate to the two-stage lead bonding of lead frame promptly, through adopting base plate and LQFP64 frame hybrid package structure. The chip is bonded to the built-in substrate firstly, and then the substrate is bonded to the frame, so that the realization of the process is ensured, and the process risk is reduced.
The technical solutions of the present invention or similar technical solutions designed by those skilled in the art based on the teachings of the technical solutions of the present invention are all within the scope of the present invention to achieve the above technical effects.
Claims (7)
1. The lead frame with the built-in substrate is characterized by comprising a chip, wherein a lead substrate is built between the chip and the lead frame, the chip is in lead bonding with the lead substrate, and the lead substrate is in lead bonding with the lead frame.
2. The leadframe according to claim 1, wherein the chip is embedded in a lead substrate, the lead substrate being embedded in the leadframe.
3. The lead frame of claim 1, wherein the die wire bonding to the lead substrate comprises a first level bonding of the die and a first level wire bonding to the lead substrate, and forming a first level wire bonding structure;
the lead substrate lead bonding on the lead frame comprises the second-stage bonding of the lead substrate and the second-stage routing on the lead frame, and a second-stage lead bonding structure is formed.
4. The leadframe according to claim 1, wherein the chip comprises a package or a die.
5. The leadframe according to claim 4, wherein the package compliant structure comprises: QFP series packages or LQFP series packages.
6. The lead frame of claim 4, wherein the package has a range of applications: 0.65 mm-0.5 mm.
7. The lead frame of claim 1, wherein the lead substrate reserves chip space or component space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123041684.4U CN216413073U (en) | 2021-12-06 | 2021-12-06 | Lead frame with built-in substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123041684.4U CN216413073U (en) | 2021-12-06 | 2021-12-06 | Lead frame with built-in substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216413073U true CN216413073U (en) | 2022-04-29 |
Family
ID=81304485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123041684.4U Active CN216413073U (en) | 2021-12-06 | 2021-12-06 | Lead frame with built-in substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216413073U (en) |
-
2021
- 2021-12-06 CN CN202123041684.4U patent/CN216413073U/en active Active
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